aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2022-06-30arm64: dts: qcom: sdm660: Add initial Inforce IFC6560 board supportDmitry Baryshkov2-0/+462
The IFC6560 is a board from Inforce Computing, built around the SDA660 SoC. This patch describes core clocks, some regulators from the two PMICs, debug uart, storage, bluetooth and audio DSP remoteproc. The regulator settings are inherited from prior work by Konrad Dybcio and AngeloGioacchino Del Regno. Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Co-developed-by: Bjorn Andersson <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-29ARM: dts: qcom: align gpio-key node names with dtschemaKrzysztof Kozlowski10-28/+28
The node names should be generic and DT schema expects certain pattern (e.g. with key/button/switch). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-29ARM: dts: qcom: adjust whitespace around '='Krzysztof Kozlowski9-196/+196
Fix whitespace coding style: use single space instead of tabs or multiple spaces around '=' sign in property assignment. No functional changes (same DTB). Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-29ARM: dts: qcom: ipq4019: fix Micron SPI NOR compatibleKrzysztof Kozlowski2-2/+2
The proper compatible for Micron n25q128a11 SPI NOR flash should include vendor-prefix and use jedec,spi-nor fallback. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-29ARM: dts: qcom: apq8064: add unit addresses to QFPROM regionsKrzysztof Kozlowski1-2/+2
QFPROM children have 'reg' so they must have unit address. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-29ARM: dts: qcom: cleanup QFPROM nodesKrzysztof Kozlowski3-7/+7
Cleanup coding style of QFPROM nodes - put compatible as first property and drop tabs before '=' character. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-29ARM: dts: qcom: use dedicated QFPROM compatiblesKrzysztof Kozlowski4-4/+4
Use dedicated compatibles for QFPROM on APQ8064, IPQ8064 and MSM9874, which is expected by the bindings. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-29ARM: dts: qcom: replace gcc PXO with pxo_board fixed clockAnsuel Smith1-1/+1
Replace gcc PXO phandle to pxo_board fixed clock declared in the dts. gcc driver doesn't provide PXO_SRC as it's a fixed-clock. This cause a kernel panic if any driver actually try to use it. Fixes: 40cf5c884a96 ("ARM: dts: qcom: add L2CC and RPM for IPQ8064") Signed-off-by: Ansuel Smith <[email protected]> Reviewed-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-29ARM: dts: r9a06g032-rzn1d400-db: Add switch descriptionClément Léger1-0/+115
Add the description for the switch, GMAC2 and MII converter. With these definitions, the switch ports 0 and 1 (MII ports 5 and 4) are working on the RZ/N1D-DB board. Signed-off-by: Clément Léger <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-06-29dt-bindings: net: pcs: add bindings for Renesas RZ/N1 MII converterClément Léger2-0/+204
This MII converter can be found on the RZ/N1 processor family. The MII converter ports are declared as subnodes which are then referenced by users of the PCS driver such as the switch. Signed-off-by: Clément Léger <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-06-29ARM: dts: r9a06g032: Describe switchClément Léger1-0/+51
Add the description of the switch that is present on the RZ/N1 SoC. This description includes ethernet-port descriptions for all the ports that are present on the switch along with their connection to the MII converter ports and to the GMAC for the CPU port. Signed-off-by: Clément Léger <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-06-29ARM: dts: r9a06g032: Describe GMAC2Clément Léger1-0/+18
The RZ/N1 SoC includes two MACs named GMACx that are compatible with the "snps,dwmac" driver. GMAC1 is connected directly to the MII converter port 1. GMAC2 however can be used as the MAC for the switch CPU management port or can be muxed to be connected directly to the MII converter port 2. This commit adds the description for the GMAC2 which will be used by the switch description. Signed-off-by: Clément Léger <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-06-29ARM: dts: r9a06g032: Describe MII converterClément Léger1-0/+39
Add the MII converter node which describes the MII converter that is present on the RZ/N1 SoC. Signed-off-by: Clément Léger <[email protected]> Reviewed-by: Florian Fainelli <[email protected]> Reviewed-by: Vladimir Oltean <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-06-29arm64: dts: renesas: r9a07g054l2-smarc: Correct SoC name in commentChris Paterson1-1/+1
This dts is for the RZ/V2L SMARC EVK, not RZ/G2L. Fixes: f91c4c74796a ("arm64: dts: renesas: Add initial device tree for RZ/V2L SMARC EVK") Signed-off-by: Chris Paterson <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Geert Uytterhoeven <[email protected]>
2022-06-29ARM: dts: renesas: Fix DA9063 watchdog subnode namesGeert Uytterhoeven8-8/+8
make dtbs_check: arch/arm/boot/dts/r8a7791-koelsch-single-memory-node.dtb: pmic@58: 'wdt' does not match any of the regexes: 'pinctrl-[0-9]+' From schema: Documentation/devicetree/bindings/mfd/dlg,da9063.yaml ... Change the watchdog child node names to match the DA9063 DT bindings and the Generic Names Recommendation in the Devicetree Specification. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/1dafdce285f7d14bec9e2033ac87fb30135895db.1655818230.git.geert+renesas@glider.be
2022-06-29arm64: dts: renesas: r8a779m8: Drop operating points above 1.5 GHzGeert Uytterhoeven1-0/+5
The highest-performance mode for the Cortex-A57 CPU cores supported on R-Car H3Ne (R8A779M8) is the Power Optimized (1.5 GHz) mode. The Normal (1.6 GHz) and High Performance (1.7 GHz) modes are not supported. Hence drop the "turbo-mode" entries from the operating points table inherited from r8a77951.dtsi. Fixes: 6e87525d751fac57 ("arm64: dts: renesas: Add Renesas R8A779M8 SoC support") Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/aeb4530f7fbac8329b334dcb169382c836a5f32d.1655458564.git.geert+renesas@glider.be
2022-06-29MAINTAINERS: Add Renesas SoC DT bindings to Renesas Architecture sectionsGeert Uytterhoeven1-0/+2
While Renesas SoC DT bindings documents started to appear under Documentation/devicetree/bindings/soc/renesas, these are not yet covered by the file and directory patterns in the Renesas ARM/ARM64 Architecture sections. Add the missing patterns. Signed-off-by: Geert Uytterhoeven <[email protected]> Link: https://lore.kernel.org/r/f99c03a95a103517418f0b23d3da45e0dd0ffb3b.1655456310.git.geert+renesas@glider.be
2022-06-29arm64: dts: juno: Add cache-level property to L2 cachesSudeep Holla3-0/+6
Add the missing cache-level property to L2 caches. This is needed if we need to find the last level cache directly from the device tree cache node. Link: https://lore.kernel.org/r/[email protected] Cc: Liviu Dudau <[email protected]> Cc: Lorenzo Pieralisi <[email protected]> Acked-by: Liviu Dudau <[email protected]> Signed-off-by: Sudeep Holla <[email protected]>
2022-06-28dt-bindings: arm: qcom: document sda660 SoC and ifc6560 boardDmitry Baryshkov1-0/+6
Add binding documentation for the Inforce IFC6560 board which uses Snapdragon SDA660. Reviewed-by: Marijn Suijten <[email protected]> Reviewed-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm660: move SDHC2 card detect pinconf to board filesDmitry Baryshkov3-12/+32
This results in dts duplication, but per mutual agreement card detect pin configuration belongs to the board files. Move it from the SoC dtsi to the board DT files. Suggested-by: Marijn Suijten <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm636-sony-xperia-ganges-mermaid: correct sdc2 pinconfDmitry Baryshkov1-1/+1
Fix the device tree node in the &sdc2_state_on override. The sdm630 uses 'clk' rather than 'pinconf-clk'. Fixes: 4c1d849ec047 ("arm64: dts: qcom: sdm630-xperia: Retire sdm630-sony-xperia-ganges.dtsi") Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm630: fix gpu's interconnect pathDmitry Baryshkov1-1/+2
ICC path for the GPU incorrectly states <&gnoc 1 &bimc 5>, which is a path from SLAVE_GNOC_BIMC to SLAVE_EBI. According to the downstream kernel sources, the GPU uses MASTER_OXILI here, which is equivalent to <&bimc 1 ...>. While we are at it, use defined names instead of the numbers for this interconnect path. Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration") Reported-by: Marijn Suijten <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm630: add second (HS) USB host supportDmitry Baryshkov1-0/+55
Add DT entries for the second DWC3 USB host, which is limited to the USB2.0 (HighSpeed), and the corresponding QUSB PHY. Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm630: rename qusb2phy to qusb2phy0Dmitry Baryshkov3-4/+4
In preparation to adding second USB host/PHY pair, change first USB PHY's label to qusb2phy0. Suggested-by: Marijn Suijten <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm630: fix the qusb2phy ref clockDmitry Baryshkov1-1/+1
According to the downstram DT file, the qusb2phy ref clock should be GCC_RX0_USB2_CLKREF_CLK, not GCC_RX1_USB2_CLKREF_CLK. Fixes: c65a4ed2ea8b ("arm64: dts: qcom: sdm630: Add USB configuration") Cc: Konrad Dybcio <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm630: disable GPU by defaultDmitry Baryshkov1-0/+2
The SoC's device tree file disables gpucc and adreno's SMMU by default. So let's disable the GPU too. Moreover it looks like SMMU might be not usable without additional patches (which means that GPU is unusable too). No board uses GPU at this moment. Fixes: 5cf69dcbec8b ("arm64: dts: qcom: sdm630: Add Adreno 508 GPU configuration") Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm660: disable dsi1/dsi1_phy by defaultDmitry Baryshkov1-0/+3
Follow the typical practice and keep DSI1/DSI1 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Reviewed-by: Marijn Suijten <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: sdm630: disable dsi0/dsi0_phy by defaultDmitry Baryshkov1-0/+3
Follow the typical practice and keep DSI0/DSI0 PHY disabled by default. They should be enabled in the board DT files. No existing boards use them at this moment. Suggested-by: Marijn Suijten <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Reviewed-by: Marijn Suijten <[email protected]> Signed-off-by: Dmitry Baryshkov <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: correct interrupt controller on PM8916 and PMS405Krzysztof Kozlowski2-16/+4
The PM8916 and PMS405 PMIC GPIOs are interrupt controllers, as described in the bindings and used by the driver. Drop the interrupts (apparently copied from downstream tree), just like in commit 61d2ca503d0b ("arm64: dts: qcom: fix pm8150 gpio interrupts"): qcs404-evb-4000.dtb: gpio@c000: 'interrupts' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' qcs404-evb-4000.dtb: gpio@c000: 'interrupt-controller' is a required property Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-28arm64: dts: qcom: add missing gpio-ranges in PMIC GPIOsKrzysztof Kozlowski10-0/+10
The new Qualcomm PMIC GPIO bindings require gpio-ranges property: sm8250-sony-xperia-edo-pdx203.dtb: gpio@c000: 'gpio-ranges' is a required property Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27arm64: dts: qcom: sdm630: order interrupts according to bindingsKrzysztof Kozlowski1-8/+8
The CAMSS DTSI device node, which came after the bindings were merged, got the interrupts ordered differently then specified in the bindings: sdm630-sony-xperia-nile-pioneer.dtb: camss@ca00000: interrupt-names:0: 'csid0' was expected Reordering them to match bindings should not cause ABI issues, because the driver relies on names, not ordering. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27arm64: dts: qcom: sdm630: order regs according to bindingsKrzysztof Kozlowski1-12/+12
The CAMSS DTSI device node, which came after the bindings were merged, got the regs ordered differently then specified in the bindings: sdm636-sony-xperia-ganges-mermaid.dtb: camss@ca00000: reg-names:0: 'csi_clk_mux' was expected Reordering them to match bindings should not cause ABI issues, because the driver relies on names, not ordering. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27arm64: dts: qcom: sdm630: order clocks according to bindingsKrzysztof Kozlowski1-84/+84
The CAMSS DTSI device node, which came after the bindings were merged, got the clocks ordered differently then specified in the bindings: sdm636-sony-xperia-ganges-mermaid.dtb: camss@ca00000: reg-names:4: 'csid3' was expected Reordering them to match bindings should not cause ABI issues, because the driver relies on names, not ordering. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: add missing gpio-ranges in PMIC GPIOsKrzysztof Kozlowski2-0/+2
The new Qualcomm PMIC GPIO bindings require gpio-ranges property: qcom-sdx55-telit-fn980-tlb.dtb: gpio@c000: 'gpio-ranges' is a required property Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: pmx65: add fallback compatible to PMIC GPIOKrzysztof Kozlowski1-1/+1
The bindings require all PMIC GPIO nodes to have two compatibles - specific followed by SPMI or SSBI fallback. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: mdm9615: add missing PMIC GPIO regKrzysztof Kozlowski1-0/+1
'reg' property is required in SSBI children: qcom-mdm9615-wp8548-mangoh-green.dtb: gpio@150: 'reg' is a required property Fixes: 2c5e596524e7 ("ARM: dts: Add MDM9615 dtsi") Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: align PMIC GPIO pin configuration with DT schemaKrzysztof Kozlowski11-37/+37
DT schema expects PMIC GPIO pin configuration nodes to be named with '-state' suffix. Optional children should be either 'pinconf' or followed with '-pins' suffix. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27arm64: dts: qcom: msm8994-msft-lumia-octagon: add PM8994 pin propertiesKrzysztof Kozlowski1-3/+6
The bindings require that every pin configuration comes with 'function' property. There is also no 'drive-strength' property but 'qcom,drive-strength': msm8994-msft-lumia-octagon-cityman.dtb: gpios@c000: amsel-high-state: 'oneOf' conditional failed, one must be fixed: 'drive-strength' does not match any of the regexes: 'pinctrl-[0-9]+' 'bias-pull-up', 'drive-strength', 'function', 'pins' do not match any of the regexes: '(pinconf|-pins)$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27arm64: dts: qcom: apq8096-db820c: add PM8994 pin functionKrzysztof Kozlowski1-0/+1
The bindings require that every pin configuration comes with 'function' property. Add such to PM8994 GPIO5. Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27arm64: dts: qcom: add fallback compatible to PMIC GPIOsKrzysztof Kozlowski13-13/+13
The bindings require all PMIC GPIO nodes to have two compatibles - specific followed by SPMI or SSBI fallback. Add the fallback to fix warnings like: msm8916-samsung-serranove.dtb: gpios@c000: compatible: ['qcom,pm8916-gpio'] is too short Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27arm64: dts: qcom: align PMIC GPIO pin configuration with DT schemaKrzysztof Kozlowski22-86/+86
DT schema expects PMIC GPIO pin configuration nodes to be named with '-state' suffix. Optional children should be either 'pinconf' or followed with '-pins' suffix. This fixes dtbs_check warnings like: sdm845-xiaomi-beryllium.dtb: gpios@c000: 'vol-up-active' does not match any of the regexes: '-state$', 'pinctrl-[0-9]+' Signed-off-by: Krzysztof Kozlowski <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27arm64: dts: qcom: sdm845-akatsuki: Round down l22a regulator voltageMarijn Suijten1-2/+3
2700000 is not a multiple of pmic4_pldo's step size of 8000 (with base voltage 1664000), resulting in pm8998-rpmh-regulators not probing. Just as we did with MSM8998's Sony Yoshino Poplar [1], round the voltages down to err on the cautious side and leave a comment in place to document this discrepancy wrt downstream sources. [1]: https://lore.kernel.org/linux-arm-msm/[email protected]/ Fixes: 30a7f99befc6 ("arm64: dts: qcom: Add support for SONY Xperia XZ2 / XZ2C / XZ3 (Tama platform)") Signed-off-by: Marijn Suijten <[email protected]> Reviewed-by: Konrad Dybcio <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: sdx65: Add Watchdog supportRohit Agarwal1-0/+6
Enable Watchdog support for Application Processor Subsystem (APSS) block on SDX65 platform. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: sdx65: Add pshold supportRohit Agarwal1-0/+5
Add support for pshold block to drive pshold towards the PMIC, which is used to trigger a configurable event such as reboot or poweroff of the SDX65 platform. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: sdx65-mtp: Enable modemRohit Agarwal1-0/+5
Enable modem on SDX65 MTP board. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: sdx65: Add Modem remoteproc nodeRohit Agarwal1-0/+33
Add modem support to SDX65 using the PAS remoteproc driver. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: sdx65: Add SCM nodeRohit Agarwal1-0/+6
Add SCM node to enable SCM functionality on SDX65 platform. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: sdx65: Add IMEM and PIL info regionRohit Agarwal1-0/+13
Add a simple-mfd representing IMEM on SDX65 and define the PIL relocation info region, so that post mortem tools will be able to locate the loaded remoteproc. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: sdx65: Add modem SMP2P nodeRohit Agarwal1-0/+31
Add SMP2P nodes for the SDX65 platform to communicate with the modem. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
2022-06-27ARM: dts: qcom: sdx65: Add CPUFreq supportRohit Agarwal1-0/+29
Add CPUFreq support to SDX65 platform using the cpufreq-dt driver. There is no dedicated hardware block available on this platform to carry on the CPUFreq duties. Hence, it is accomplished using the CPU clock and regulators tied together by the operating points table. Signed-off-by: Rohit Agarwal <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Link: https://lore.kernel.org/r/[email protected]
Powered by cgit, Gruvboxed by Blaster4385.