aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2019-09-13drm/i915/tgl: Limit ourselves to just rcs0Chris Wilson2-2/+7
More pruning away of features until we have a stable system and a basis for debugging what's missing. v2: Fixup vdbox/vebox fusing Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-13drm/i915: Don't mix srcu tag and negative error codesChris Wilson3-10/+6
While srcu may use an integer tag, it does not exclude potential error codes and so may overlap with our own use of -EINTR. Use a separate outparam to store the tag, and report the error code separately. Fixes: 2caffbf11762 ("drm/i915: Revoke mmaps and prevent access to fence registers across reset") Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-13drm/i915/display/icl: Bump up the plane/fb heightManasi Navare1-3/+18
On ICL+, the max supported plane height is 4320, so bump it up To support 4320, we need to increase the number of bits used to read plane_height to 13 as opposed to older 12 bits. v4: * Adjust the width mask also since extra bits are mbz (Ville) v3: * Use 0xffff for mask as extra bits are mbz (Ville) v2: * ICL plane height supported is 4320 (Ville) * Add a new line between max width and max height (Jose) Cc: Maarten Lankhorst <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-13drm/i915/display/icl: Bump up the hdisplay and vdisplay as per transcoder limitsManasi Navare1-2/+7
On ICL+, the vertical limits for the transcoders are increased to 8192 and horizontal limits are bumped to 16K so bump up limits in intel_mode_valid() v4: * Increase the hdisplay to 16K (Ville) v3: * Supported starting ICL (Ville) * Use the higher limits from TRANS_VTOTAL register (Ville) v2: * Checkpatch warning (Manasi) Cc: Maarten Lankhorst <[email protected]> Cc: Ville Syrjälä <[email protected]> Signed-off-by: Manasi Navare <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-13drm/i915/gtt: Make sure the gen6 ppgtt is bound before first useChris Wilson2-19/+25
As we remove the struct_mutex protection from around the vma pinning, counters need to be atomic and aware that there may be multiple threads simultaneously active. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915/selftests: Keep the engine awake while we keep for preemptionChris Wilson1-0/+10
Keep the engine awake to ensure that we don't inject any pm-idle requests. References: https://bugs.freedesktop.org/show_bug.cgi?id=111108 Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Acked-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915: Get the correct wakeref for reading HOTPLUG_EN et al.Arkadiusz Hiler1-1/+4
Without it we get: Unclaimed read from register 0x1e1110 WARNING: CPU: 2 PID: 1029 at drivers/gpu/drm/i915/intel_uncore.c:1101 __unclaimed_reg_debug+0x40/0x50 [i915] Call Trace: fwtable_read32+0x233/0x300 [i915] i915_interrupt_info+0xa73/0xd60 [i915] seq_read+0xdb/0x3c0 full_proxy_read+0x51/0x80 vfs_read+0x9e/0x160 ksys_read+0x8f/0xe0 do_syscall_64+0x55/0x1c0 entry_SYSCALL_64_after_hwframe+0x49/0xbe Cc: Chris Wilson <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=109824 Signed-off-by: Arkadiusz Hiler <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915/tgl: Disable preemption while being debuggedChris Wilson2-0/+4
We see failures where the context continues executing past a preemption event, eventually leading to situations where a request has executed before we have event submitted it to HW! It seems like tgl is ignoring our RING_TAIL updates, but more likely is that there is a missing update required for our semaphore waits around preemption. v2: And disable internal semaphore usage Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Acked-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915/pmu: Use GT parked for estimating RC6 while asleepChris Wilson5-121/+170
As we track when we put the GT device to sleep upon idling, we can use that callback to sample the current rc6 counters and record the timestamp for estimating samples after that point while asleep. v2: Stick to using ktime_t v3: Track user_wakerefs that interfere with the new intel_gt_pm_wait_for_idle v4: No need for parked/unparked estimation if !CONFIG_PM v5: Keep timer park/unpark logic as was v6: Refactor duplicated estimate/update rc6 logic v7: Pull intel_get_pm_get_if_awake() out from the pmu->lock. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105010 Signed-off-by: Chris Wilson <[email protected]> Cc: Tvrtko Ursulin <[email protected]> Reviewed-by: Tvrtko Ursulin <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915: convert device info num_pipes to pipe_maskJani Nikula4-20/+20
Replace device info number of pipes with a bit mask of available pipes. This will prove handy in the future. There's still a bunch of future work to do to actually allow a non-consecutive mask of pipes, but it's a start. No functional changes. Cc: Chris Wilson <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Acked-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915/pmu: Skip busyness sampling when and where not neededTvrtko Ursulin1-0/+4
Since d0aa694b9239 ("drm/i915/pmu: Always sample an active ringbuffer") the cost of sampling the engine state on execlists platforms became a little bit higher when both engine busyness and one of the wait states are being monitored. (Previously the busyness sampling on legacy platforms was done via seqno comparison so there was no cost of mmio read.) We can avoid that by skipping busyness sampling when engine supports software busy stats and so avoid the cost of potential mmio read and sample accumulation. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915/execlists: Ensure the context is reloaded after a GPU resetChris Wilson1-0/+1
After we manipulate the context to allow replay after a GPU reset, force that context to be reloaded. This should be a layer of paranoia, for if the GPU was reset, the context will no longer be resident! Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Acked-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915/execlists: Add a paranoid flush of the CSB pointers upon resetChris Wilson1-0/+4
After a GPU reset, we need to drain all the CS events so that we have an accurate picture of the execlists state at the time of the reset. Be paranoid and force a read of the CSB write pointer from memory. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915: Disable FBC if BIOS reserved memory (stolen) is unavailableChris Wilson1-0/+3
The FBC requires a couple of contiguous buffers, which we allocate from stolen memory. If stolen memory is unavailable, we cannot allocate those buffers and so cannot support FBC. Mark it so. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915: Remove duplicated bxt/cnl/icl .modeset_calc_cdclk() funcsVille Syrjälä1-37/+9
Reuse the same .modeset_calc_cdclk() function for all bxt+. The only difference in between the cnl/icl and the bxt variants is the call to cnl_compute_min_voltage_level(). We can do that call just fine on older platforms since they leave min_voltage_level[] zeroed. Let's rename the function to bxt_compute_min_voltage_level() just so it stays consistent with the rest of the naming scheme. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915: Reuse cnl_modeset_calc_cdclk() on icl+Ville Syrjälä1-35/+2
The cnl and icl .modeset_calc_cdclk() functions are identical. Drop one copy. Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915: Fix CD2X pipe select masking during cdclk sanitationVille Syrjälä1-19/+23
We're forgetting to mask off all three pipe select bits from the CDCLK_CTL value on icl+ which may lead to the extra bit being left in. That will cause us to consider the current hardware cdclk state as invalid, and we proceed to sanitize it even though the hardware may have active pipes and whatnot. Fix up the mask so we get rid of all three pipe select bits and thus hopefully no longer sanitize cdclk when it's already correctly programmed. Cc: Matt Roper <[email protected]> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111641 Fixes: 0c1279b58fc7 ("drm/i915: Consolidate {bxt,cnl,icl}_init_cdclk") Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-12drm/i915: Fix cdclk bypass freq readout for tgl/bxt/glkVille Syrjälä1-1/+2
On tgl/bxt/glk the cdclk bypass frequency depends on the PLL reference clock. So let's read out the ref clock before we try to compute the bypass clock. Cc: Matt Roper <[email protected]> Fixes: 71dc367e2bc3 ("drm/i915: Consolidate bxt/cnl/icl cdclk readout") Signed-off-by: Ville Syrjälä <[email protected]> Reviewed-by: Matt Roper <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: add INTEL_NUM_PIPES() and use itJani Nikula6-14/+16
Abstract away direct access to ->num_pipes to allow further refactoring. No functional changes. Cc: Chris Wilson <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Ville Syrjälä <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Acked-by: Ville Syrjälä <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Squeeze iommu status into debugfs/i915_capabilitiesChris Wilson1-0/+7
There's no easy way of checking whether iommu is enabled for the GPU (you can grep dmesg if you know the device, or you can grep i915_gpu_info if that's available). We do have a central i915_capabilities with the intent of listing such pertinent information, so add the iommu status. Suggested-by: Martin Peres <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Cc: Martin Peres <[email protected]> Cc: Tomi Sarvela <[email protected]> Cc: Mika Kuoppala <[email protected]> Acked-by: Martin Peres <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915/tgl: Disable read-only ppgtt supportChris Wilson1-1/+3
The same read-only affliction as befell Icelake is affecting Tigerlake. Disable the read-only support as clearly it was not fixed. Testcase: igt/i915_selftests/live_gem_context References: 3936867dbc1e ("drm/i915: Disable read only ppgtt support for gen11") Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Remove pointless planes_changed=true assignmentVille Syrjälä1-7/+0
i915 doesn't use the crtc_state->plane_changed flag for anything, so setting it is pointless. Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Stanislav Lisovskiy <[email protected]>
2019-09-11drm/i915: Use a high priority wq for nonblocking plane updatesVille Syrjälä2-1/+7
system_unbound_wq can't keep up sometimes and we get dropped frames. Switch to a high priority variant. Reported-by: Heinrich Fink <[email protected]> Tested-by: Heinrich Fink <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Reviewed-by: Chris Wilson <[email protected]>
2019-09-11drm/i915/display: Add glk_cdclk_tableChris Wilson1-1/+4
Commit 736da8112fee ("drm/i915: Use literal representation of cdclk tables") pushed the cdclk logic into tables, adding glk_cdclk_table but not using yet: drivers/gpu/drm/i915/display/intel_cdclk.c:1173:38: error: ‘glk_cdclk_table’ defined but not used [-Werror=unused-const-variable=] Fixes: 736da8112fee ("drm/i915: Use literal representation of cdclk tables") Signed-off-by: Chris Wilson <[email protected]> Cc: Ville Syrjälä <[email protected]> Cc: Matt Roper <[email protected]> Cc: Jani Nikula <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Make i915_vma.flags atomic_t for mutex reductionChris Wilson6-49/+64
In preparation for reducing struct_mutex stranglehold around the vm, make the vma.flags atomic so that we can acquire a pin on the vma atomically before deciding if we need to take the mutex. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Whitelist COMMON_SLICE_CHICKEN2Kenneth Graunke1-0/+3
This allows userspace to use "legacy" mode for push constants, where they are committed at 3DPRIMITIVE or flush time, rather than being committed at 3DSTATE_BINDING_TABLE_POINTERS_XS time. Gen6-8 and Gen11 both use the "legacy" behavior - only Gen9 works in the "new" way. Conflating push constants with binding tables is painful for userspace, we would like to be able to avoid doing so. Signed-off-by: Kenneth Graunke <[email protected]> Cc: [email protected] Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Make shrink/unshrink be atomicChris Wilson5-17/+26
Add an atomic counter and always take the spinlock around the pin/unpin events, so that we can perform the list manipulation concurrently. Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Make pm_notify take intel_gtTvrtko Ursulin1-4/+4
These notifications operate on intel_gt so make the code take what it needs. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Avoid round-trip via i915 in intel_gt_parkTvrtko Ursulin1-3/+3
Both in the container_of and getting to gt->awake there is no need to go via i915 since both the wakeref and awake are members of gt. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Make wait_for_timelines take struct intel_gtTvrtko Ursulin1-5/+6
Timelines live in struct intel_gt so make wait_for_timelines take exactly what it needs. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-11drm/i915: Move GT init to intel_gt.cTvrtko Ursulin8-97/+98
Code in i915_gem_init_hw is all about GT init so move it to intel_gt.c renaming to intel_gt_init_hw. Existing intel_gt_init_hw is renamed to intel_gt_init_hw_early since it is currently called from driver probe. Signed-off-by: Tvrtko Ursulin <[email protected]> Cc: Andi Shyti <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Consolidate {bxt,cnl,icl}_init_cdclkMatt Roper1-63/+2
The BXT and CNL functions were already basically identical, whereas ICL's function tried to do its own sanitization rather than calling bxt_sanitize_cdclk. This should actually fix a bug in our ICL initialization where it would consider the /2 CD2X divider invalid and force an unnecessary sanitization (we now have valid clock frequencies that use this divider). Cc: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Enhance cdclk sanitizationMatt Roper1-2/+32
When reading out the BIOS-programmed cdclk state, let's make sure that the cdclk value is on the valid list for the platform, ensure that the VCO matches the cdclk, and ensure that the CD2X divider was set properly. Cc: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Add calc_voltage_level display vfuncMatt Roper2-49/+27
With all of the cdclk function consolidation, we can cut down on a lot of platform if/else logic by creating a vfunc that's initialized at startup. Cc: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Consolidate {bxt,cnl,icl}_uninit_cdclkMatt Roper1-34/+14
The uninitialize flow is the same on all of these platforms, aside from calculating a different frequency level. v2: Reverse platform conditional order for consistency. (Ville) Cc: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Kill cnl_sanitize_cdclk()Matt Roper1-44/+2
The CNL variant of this function is identical to the BXT variant aside from not needing to handle SSA precharge. Cc: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Combine bxt_set_cdclk and cnl_set_cdclkMatt Roper1-148/+119
We'd previously combined ICL/TGL logic into the cnl_set_cdclk function, but BXT is pretty similar as well. Roll the cnl/icl/tgl logic back into the bxt function; the only things we really need to handle separately are punit notification and calling different functions to enable/disable the cdclk PLL. Cc: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Use literal representation of cdclk tablesMatt Roper3-203/+110
The bspec lays out legal cdclk frequencies, PLL ratios, and CD2X dividers in an easy-to-read table for most recent platforms. We've been translating the data from that table into platform-specific code logic, but it's easy to overlook an area we need to update when adding new cdclk values or enabling new platforms. Let's just add a form of the bspec table to the code and then adjust our functions to pull what they need directly out of the table. v2: Fix comparison when finding best cdclk. v3: Another logic fix for calc_cdclk. v4: - Use named initializers for cdclk tables. (Ville) - Include refclk as a field in the table instead of adding all three ratios for each entry. (Ville) - Terminate tables with an empty entry to avoid needing to store the table size. (Ville) - Don't try so hard to return reasonable values from our lookup functions if we get impossible inputs; just WARN and return 0. (Ville) - Keep a bxt_ prefix on the lookup functions since they're still only used on bxt+ for now. We can rename them later if we extend this table-based approach back to older platforms. (Ville) v5: - Fix cnl table's ratios for 24mhz refclk. (Ville) - Don't miss the named initializers on the cnl table. (Ville) - Represent refclk in table as u16 rather than u32. (Ville) Cc: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Consolidate bxt/cnl/icl cdclk readoutMatt Roper1-187/+138
Aside from a few minor register changes and some different clock values, cdclk design hasn't changed much since gen9lp. Let's consolidate the handlers for bxt, cnl, and icl to keep the codeflow consistent. Also, while we're at it, s/bxt_de_pll_update/bxt_de_pll_readout/ since "update" makes me think we should be writing to hardware rather than reading from it. v2: - Fix icl_calc_voltage_level() limits. (Ville) - Use CNL_CDCLK_PLL_RATIO_MASK rather than BXT_DE_PLL_RATIO_MASK on gen10+ to avoid confusion. (Ville) v3: - Also fix ehl_calc_voltage_level() limits. (Ville) Cc: Ville Syrjälä <[email protected]> Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Ville Syrjälä <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/tgl: Disable rc6 for debuggingChris Wilson2-2/+2
Empirical evidence from CI tells us that our rc6 setup for Tigerlake is off. Disable rc6 on tgl temporary so that we gain CI coverage as we prepare a fix. It also appears that the BIOS on our tgl leaves rc6 enabled, so we have to explicitly disable it on init. References: https://bugs.freedesktop.org/show_bug.cgi?id=111593 Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Acked-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/selftests: Tighten the timeout testing for partial mmapsChris Wilson1-32/+223
Currently, if there is time remaining before the start of the loop, we do one full iteration over many possible different chunks within the object. A full loop may take 50+s (depending on speed of indirect GTT mmapings) and we try separately with LINEAR, X and Y -- at which point igt times out. If we check more frequently, we will interrupt the loop upon our timeout -- it is hard to argue for as this significantly reduces the test coverage as we dramatically reduce the runtime. In practical terms, the coverage we should prioritise is in using different fence setups, forcing verification of the tile row computations over the current preference of checking extracting chunks. Though the exhaustive search is great given an infinite timeout, to improve our current coverage, we also add a randomised smoketest of partial mmaps. So let's do both, add a randomised smoketest of partial tiling chunks and the exhaustive (though time limited) search for failures. Even in adding another subtest, we should shave 100s off BAT! (With, hopefully, no loss in coverage, at least over multiple runs.) Signed-off-by: Chris Wilson <[email protected]> Cc: Matthew Auld <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/selftests: Take runtime wakeref for igt_ggtt_lowlevelChris Wilson1-4/+6
Being a "low-level" test, we opt to bypass the normal bind/unbind hooks for the lower level insert_entries/clear_range. For ggtt, the bind/unbind hooks provide the runtime wakeref and so we must also handle this in exercising the low level hooks. <4> [538.151672] RPM raw-wakeref not held <4> [538.151825] WARNING: CPU: 0 PID: 11 at ./drivers/gpu/drm/i915/intel_runtime_pm.h:107 fwtable_read32+0x1be/0x300 [i915] <4> [538.151830] Modules linked in: i915(+) amdgpu gpu_sched ttm vgem snd_hda_codec_hdmi snd_hda_codec_realtek snd_hda_codec_generic mei_hdcp btusb btrtl btbcm x86_pkg_temp_thermal coretemp btintel crct10dif_pclmul bluetooth crc32_pclmul snd_intel_nhlt snd_hda_codec ecdh_generic ghash_clmulni_intel ecc snd_hwdep snd_hda_core lpc_ich r8169 realtek snd_pcm mei_me mei prime_numbers pinctrl_broxton pinctrl_intel [last unloaded: i915] <4> [538.151861] CPU: 0 PID: 11 Comm: migration/0 Tainted: G U 5.3.0-rc7-CI-Trybot_4938+ #1 <4> [538.151864] Hardware name: Intel corporation NUC6CAYS/NUC6CAYB, BIOS AYAPLCEL.86A.0056.2018.0926.1100 09/26/2018 <4> [538.151960] RIP: 0010:fwtable_read32+0x1be/0x300 [i915] <4> [538.151965] Code: e8 e7 f9 5f e0 e9 0b ff ff ff 80 3d d5 8d 26 00 00 0f 85 81 fe ff ff 48 c7 c7 ef 01 bd a0 c6 05 c1 8d 26 00 01 e8 b2 e4 6a e0 <0f> 0b e9 67 fe ff ff 80 3d ad 8d 26 00 00 0f 85 65 fe ff ff 48 c7 <4> [538.151969] RSP: 0018:ffffc9000007be10 EFLAGS: 00010086 <4> [538.151972] RAX: 0000000000000000 RBX: ffff88826be10d50 RCX: 0000000000000002 <4> [538.151975] RDX: 0000000080000002 RSI: 0000000000000000 RDI: 00000000ffffffff <4> [538.151978] RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000000 <4> [538.151981] R10: 0000000000000000 R11: ffffc9000007bcb0 R12: 0000000000101008 <4> [538.151984] R13: 0000000000000000 R14: ffffc9000036f638 R15: 0000000000000002 <4> [538.151987] FS: 0000000000000000(0000) GS:ffff888277a00000(0000) knlGS:0000000000000000 <4> [538.151990] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 <4> [538.151993] CR2: 00007fd48e7052f8 CR3: 0000000005210000 CR4: 00000000003406f0 <4> [538.151995] Call Trace: <4> [538.152106] bxt_vtd_ggtt_clear_range__cb+0x38/0x40 [i915] Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915: Perform GGTT restore much earlier during resumeChris Wilson3-3/+11
As soon as we re-enable the various functions within the HW, they may go off and read data via a GGTT offset. Hence, if we have not yet restored the GGTT PTE before then, they may read and even *write* random locations in memory. Detected by DMAR faults during resume. Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Cc: Martin Peres <[email protected]> Cc: Joonas Lahtinen <[email protected]> Cc: [email protected] Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/ringbuffer: Flush writes before RING_TAIL updateChris Wilson1-0/+1
Be paranoid and make sure we flush any and all writes out of the WCB before performing the UC mmio to update the RING_TAIL. (An UC write should itself be enough to do the flush, hence the paranoia here.) Quite infrequently, we see problems where the GPU seems to overshoot the RING_TAIL and so executes garbage, hence the speculation. References: https://bugs.freedesktop.org/show_bug.cgi?id=111598 References: https://bugs.freedesktop.org/show_bug.cgi?id=111417 References: https://bugs.freedesktop.org/show_bug.cgi?id=111034 Signed-off-by: Chris Wilson <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/execlists: Ignore lost completion eventsChris Wilson1-45/+18
Icelake hit an issue where it missed reporting a completion event and instead jumped straight to a idle->active event (skipping over the active->idle and not even hitting the lite-restore preemption). 661497511us : process_csb: rcs0 cs-irq head=11, tail=0 661497512us : process_csb: rcs0 csb[0]: status=0x10008002:0x00000020 [lite-restore] 661497512us : trace_ports: rcs0: preempted { 28cc8:11052, 0:0 } 661497513us : trace_ports: rcs0: promote { 28cc8:11054, 0:0 } 661497514us : __i915_request_submit: rcs0 fence 28cc8:11056, current 11052 661497514us : __execlists_submission_tasklet: rcs0: queue_priority_hint:-2147483648, submit:yes 661497515us : trace_ports: rcs0: submit { 28cc8:11056, 0:0 } 661497530us : process_csb: rcs0 cs-irq head=0, tail=1 661497530us : process_csb: rcs0 csb[1]: status=0x10008002:0x00000020 [lite-restore] 661497531us : trace_ports: rcs0: preempted { 28cc8:11054!, 0:0 } 661497535us : trace_ports: rcs0: promote { 28cc8:11056, 0:0 } 661497540us : __i915_request_submit: rcs0 fence 28cc8:11058, current 11054 661497544us : __execlists_submission_tasklet: rcs0: queue_priority_hint:-2147483648, submit:yes 661497545us : trace_ports: rcs0: submit { 28cc8:11058, 0:0 } 661497553us : process_csb: rcs0 cs-irq head=1, tail=2 661497553us : process_csb: rcs0 csb[2]: status=0x10000001:0x00000000 [idle->active] 661497574us : process_csb: process_csb:1538 GEM_BUG_ON(*execlists->active) Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/display: Extract chv_read_luts()Swati Sharma2-0/+46
For cherryview, add hw read out to create hw blob of gamma lut values. Review comments from previous series: https://patchwork.freedesktop.org/patch/328252 v4: -No need to initialize *blob [Jani] -Removed right shifts [Jani] -Dropped dev local var [Jani] v5: -Returned blob instead of assigning it internally within the function [Ville] -Renamed function cherryview_get_color_config() to chv_read_luts() -Renamed cherryview_get_gamma_config() to chv_read_cgm_gamma_lut() [Ville] v9: -80 character limit [Uma] -Made read func para as const [Ville, Uma] -Renamed chv_read_cgm_gamma_lut() to chv_read_cgm_gamma_lut() [Ville, Uma] Signed-off-by: Swati Sharma <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/display: Extract i965_read_luts()Swati Sharma2-0/+54
For i965, add hw read out to create hw blob of gamma lut values. Review comments from old series: https://patchwork.freedesktop.org/series/58039/ v4: -No need to initialize *blob [Jani] -Removed right shifts [Jani] -Dropped dev local var [Jani] v5: -Returned blob instead of assigning it internally within the function [Ville] -Renamed i965_get_color_config() to i965_read_lut() [Ville] -Renamed i965_get_gamma_config_10p6() to i965_read_gamma_lut_10p6() [Ville] v9: -Typo and 80 character limit [Uma] -Made read func para as const [Ville, Uma] -Renamed i965_read_gamma_lut_10p6() to i965_read_lut_10p6() [Ville, Uma] v10: -Swapped ldw and udw while creating hw blob [Jani] -Added last index rgb lut value from PIPEGCMAX to h/w blob [Jani] Signed-off-by: Swati Sharma <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/display: Add gamma precision function for CHVSwati Sharma1-6/+19
intel_color_get_gamma_bit_precision() is extended for cherryview by adding chv_gamma_precision(), i965 will use existing i9xx_gamma_precision() func only. Signed-off-by: Swati Sharma <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Signed-off-by: Jani Nikula <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-10drm/i915/execlists: Clear STOP_RING bit on resetChris Wilson2-0/+14
During reset, we try to ensure no forward progress of the CS prior to the reset by setting the STOP_RING bit in RING_MI_MODE. Since gen9, this register is context saved and do we end up in the odd situation where we save the STOP_RING bit and so try to stop the engine again immediately upon resume. This is quite unexpected and causes us to complain about an early CS completion event! Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=111514 Signed-off-by: Chris Wilson <[email protected]> Cc: Mika Kuoppala <[email protected]> Reviewed-by: Mika Kuoppala <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-09-09drm/i915: include GTT page-size info in error stateMatthew Auld3-1/+12
It might prove useful in the future to know if the vma is utilising huge-GTT-pages. Related to this is the GTT cache, where there is some HW "quirkiness" where it must be disabled if using 2M pages, so include that for good measure. Suggested-by: Chris Wilson <[email protected]> Signed-off-by: Matthew Auld <[email protected]> Cc: Chris Wilson <[email protected]> Reviewed-by: Chris Wilson <[email protected]> Signed-off-by: Chris Wilson <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Powered by cgit, Gruvboxed by Blaster4385.