diff options
| author | Chris Wilson <[email protected]> | 2019-09-12 14:23:13 +0100 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2019-09-12 20:45:23 +0100 |
| commit | ee73e2795b416b829f0e00e7c43154922dff495b (patch) | |
| tree | 302ee1146ecbfc8b2cc95b4b7e0e626d6a5bbbc1 | |
| parent | 16ffe73c186b7897a1a6888ffb4949a8b4026624 (diff) | |
drm/i915/tgl: Disable preemption while being debugged
We see failures where the context continues executing past a
preemption event, eventually leading to situations where a request has
executed before we have event submitted it to HW! It seems like tgl is
ignoring our RING_TAIL updates, but more likely is that there is a
missing update required for our semaphore waits around preemption.
v2: And disable internal semaphore usage
Signed-off-by: Chris Wilson <[email protected]>
Cc: Mika Kuoppala <[email protected]>
Acked-by: Mika Kuoppala <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/gt/intel_lrc.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/i915/i915_pci.c | 1 |
2 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c index 47d766ccea71..a3f0e4999744 100644 --- a/drivers/gpu/drm/i915/gt/intel_lrc.c +++ b/drivers/gpu/drm/i915/gt/intel_lrc.c @@ -2939,6 +2939,9 @@ void intel_execlists_set_default_submission(struct intel_engine_cs *engine) engine->flags |= I915_ENGINE_HAS_PREEMPTION; } + if (INTEL_GEN(engine->i915) >= 12) /* XXX disabled for debugging */ + engine->flags &= ~I915_ENGINE_HAS_SEMAPHORES; + if (engine->class != COPY_ENGINE_CLASS && INTEL_GEN(engine->i915) >= 12) engine->flags |= I915_ENGINE_HAS_RELATIVE_MMIO; } diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 698116276441..9236fccb3a83 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -798,6 +798,7 @@ static const struct intel_device_info intel_tigerlake_12_info = { .engine_mask = BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2), .has_rc6 = false, /* XXX disabled for debugging */ + .has_logical_ring_preemption = false, /* XXX disabled for debugging */ }; #undef GEN |