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2015-09-03Merge branches 'cleanup', 'fixes', 'misc', 'omap-barrier' and 'uaccess' into ↵Russell King314-2196/+6590
for-linus
2015-09-03Merge branch '4.2-fixes' into mips-for-linux-nextRalf Baechle3-19/+20
2015-09-03drm/i915: Add locks around audio component bind/unbindDavid Henningsson1-0/+4
This will make sure that audio callbacks do not race with component bind/unbind. [Note: this is an update patch to commit [51e1d83cab99: drm/i915: Call audio pin/ELD notify function] where I mistakenly applied the older version. Jani and Daniel's review tags were to the latest version, so I add them below, too -- tiwai] Signed-off-by: David Henningsson <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Takashi Iwai <[email protected]>
2015-09-03MIPS: UAPI: Fix unrecognized opcode WSBH/DSBH/DSHD when using MIPS16.Yousong Zhou1-3/+9
The nomips16 has to be added both as function attribute and assembler directive. When only function attribute is specified, the compiler will inline the function with -Os optimization. The generated assembly code cannot be correctly assembled because ISA mode switch has to be done through jump instruction. When only ".set nomips16" directive is used, the generated assembly code will use MIPS32 code for the inline assembly template and MIPS16 for the function return. The compiled binary is invalid: 00403100 <__arch_swab16>: 403100: 7c0410a0 wsbh v0,a0 403104: e820ea31 swc2 $0,-5583(at) while correct code should be: 00402650 <__arch_swab16>: 402650: 7c0410a0 wsbh v0,a0 402654: 03e00008 jr ra 402658: 3042ffff andi v0,v0,0xffff Signed-off-by: Yousong Zhou <[email protected]> Cc: Chen Jie <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/11087/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03drm/i915: Drop port_mst_index parameter from pin/eld callbackDavid Henningsson3-5/+4
The port_mst_index parameter was reserved for future use, but maintainers prefer to add it later when it is actually used. [Note: this is an update patch to commit [51e1d83cab99: drm/i915: Call audio pin/ELD notify function] where I mistakenly applied the older version. Jani and Daniel's review tags were to the latest version, so I add them below, too -- tiwai] Signed-off-by: David Henningsson <[email protected]> Reviewed-by: Jani Nikula <[email protected]> Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Takashi Iwai <[email protected]>
2015-09-03MIPS: Fix alignment of quiet build output for vmlinuz linkAlex Smith1-1/+1
The "LD vmlinuz" line in the quiet build output is misaligned with the rest of the output. Fix this. Signed-off-by: Alex Smith <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/11019/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Remove unused handle_dsemul function declarationMarkos Chandras1-1/+0
handle_dsemul does not exist and it's not being used in the code at all so remove its declaration. The deliberate DS emulation exception is handled by the do_dsemulret C code. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10950/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the MIPS R6 MAX{, A} FPU instructionMarkos Chandras5-2/+480
MIPS R6 introduced the following instruction: Scalar Floating-Point Maximum and Scalar Floating-Point argument with Maximum Absolute Value MAX.fmt writes the maximum value of the inputs fs and ft to the destination fd. MAXA.fmt takes input arguments fs and ft and writes the argument with the maximum absolute value to the destination fd. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10961/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the MIPS R6 MIN{, A} FPU instructionMarkos Chandras5-2/+480
MIPS R6 introduced the following instruction: Scalar Floating-Point Minimum and Scalar Floating-Point argument with Minimum Absolute Value MIN.fmt writes the minimum value of the inputs fs and ft to the destination fd. MINA.fmt takes input arguments fs and ft and writes the argument with the minimum absolute value to the destination fd. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10960/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the MIPS R6 CLASS FPU instructionMarkos Chandras5-2/+138
MIPS R6 introduced the following instruction: Stores in fd a bit mask reflecting the floating-point class of the floating point scalar value fs. CLASS.fmt: FPR[fd] = class(FPR[fs]) Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10959/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the MIPS R6 RINT FPU instructionMarkos Chandras1-0/+24
MIPS R6 introduced the following instruction: Floating-Point Round to Integral Scalar floating-point round to integral floating point value. RINT.fmt: FPR[fd] = round_int(FPR[fs]) Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10958/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the MIPS R6 MSUBF FPU instructionMarkos Chandras5-2/+559
MIPS R6 introduced the following instruction: Floating Point Fused Multiply Subtract: MSUBF.fmt To perform a fused multiply-subtract of FP values. MSUBF.fmt: FPR[fd] = FPR[fd] - (FPR[fs] x FPR[ft]) Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10957/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the MIPS R6 MADDF FPU instructionMarkos Chandras5-2/+553
MIPS R6 introduced the following instruction: Floating Point Fused Multiply Add: MADDF.fmt To perform a fused multiply-add of FP values. MADDF.fmt: FPR[fd] = FPR[fd] + (FPR[fs] x FPR[ft]) Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10956/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the MIPS R6 SELNEZ FPU instructionMarkos Chandras1-0/+22
MIPS R6 introduced the following instruction: SELNEZ.fmt: FPR[fd]  FPR[ft].bit0 ? FPR[fs] : 0 Add support for emulating the single and double precision formats of the said instruction. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10955/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the MIPS R6 SELEQZ FPU instructionMarkos Chandras1-0/+23
MIPS R6 introduced the following instruction: SELEQZ.fmt: FPR[fd]  FPR[ft].bit0 ? 0 : FPR[fs] Add support for emulating the single and double precision formats of the said instruction. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10954/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: math-emu: Add support for the CMP.condn.fmt R6 instructionMarkos Chandras1-9/+121
Add support for emulating the new CMP.condn.fmt R6 instructions and return SIGILL for the old C.cond.fmt if R2 emulation is not enabled since it's not supported by R6. The functionality of the new CMP.condn.fmt is the following one: If the comparison specified by the condn field of the instruction is true for the operand values, the result is true; otherwise, the result is false. If no exception is taken, the result is written into FPR fd; true is all 1s and false is all 0s repeated the operand width of fmt. All other bits beyond the operand width fmt are UNPREDICTABLE. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10953/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: inst.h: Add new MIPS R6 FPU opcodesMarkos Chandras1-2/+7
Add opcodes for the new MIPS R6 FPU instructions. Signed-off-by: Markos Chandras <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10952/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Fix management port MII address on Kontron S1901Aaro Koskinen2-0/+8
Management port MII address is incorrect on Kontron S1901 resulting in broken networking. Fix by providing definitions for the in-tree DT pruning code. Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10914/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: BCM47xx: Use kmemdup rather than duplicating its implementationAndrzej Hajda1-2/+1
The patch was generated using fixed coccinelle semantic patch scripts/coccinelle/api/memdup.cocci [1]. [1]: http://permalink.gmane.org/gmane.linux.kernel/2014320 Signed-off-by: Andrzej Hajda <[email protected]> Acked-by: Hauke Mehrtens <[email protected]> Cc: Hauke Mehrtens <[email protected]> Cc: Rafał Miłecki <[email protected]> Cc: Andrzej Hajda <[email protected]> Cc: Bartlomiej Zolnierkiewicz <[email protected]> Cc: Marek Szyprowski <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10898/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03STAGING: Octeon: Use common helpers for determining interface and portJanne Huttunen1-11/+11
Currently the Octeon Ethernet driver hardcodes the mapping between interface/port and IPD port number. Since we have generic helpers for the very same purpose, we might as well use them instead. This prevents having the same information in multiple places. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10975/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Support interfaces 4 and 5Janne Huttunen1-0/+12
Add the support for mapping between interface/port numbers and IPD port numbers also for the additional interfaces some Octeon II models have. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10967/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Set up 1:1 mapping between CN68XX PKO queues and portsJanne Huttunen1-0/+3
Use the internal port number also as the queue number on CN68XX. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10962/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Initialize CN68XX PKOJanne Huttunen1-5/+144
CN68XX requires a different PKO configuration. This patch provides just enough setup to get the XAUI interfaces on CN6880 working with default parameters. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10974/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03STAGING: Octeon: Support CN68XX style WQEJanne Huttunen5-98/+304
CN68XX has a bit different WQE structure. This patch provides the new definitions and converts the code to use the proper variant based on the actual model. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10973/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03STAGING: Octeon: Increase output command buffersJanne Huttunen1-1/+1
The Octeon II models have more interfaces and thus require more output command buffers. Increase the allocation to support these models. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10965/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03STAGING: Octeon: Set SSO group mask properly on CN68XXAaro Koskinen1-4/+17
CN68XX uses SSO instead of POW. Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10966/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03STAGING: Octeon: Properly enable/disable SSO WQE interruptsAaro Koskinen2-16/+43
The Octeon models with SSO instead of POW need to use a different register for configuring the WQE interrupt thresholds. Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10964/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Add definitions for setting up SSOJanne Huttunen1-0/+29
Some Octeon II models have SSO instead of POW and use a different register for setting the interrupt thresholds. Add the necessary definitions for configuring the interrupts also on those models. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10972/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Configure minimum PKO packet sizes on CN68XXJanne Huttunen1-0/+15
CN68XX has common minimum packet size filters that need to be configured for the traffic to work. Just set them to a default value. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10963/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Configure XAUI pkindsJanne Huttunen1-0/+7
Configure the pkinds of XAUI interfaces on Octeon models that have them. This simple configuration uses 1:1 mapping between the PIP input port number and the selected pkind. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10971/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Support all PIP input ports on CN68XXJanne Huttunen1-1/+1
CN68XX has 48 PIP input ports. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10969/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Support additional interfaces on CN68XXJanne Huttunen1-0/+2
CN68XX has 9 interfaces. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10968/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Octeon: Fix CN6880 hang on XAUI initJanne Huttunen1-1/+6
Some CN68XX series Octeon II chips seem to hang if a reset is issued on XAUI initialization. Avoid the hang by disabling the reset on affected models. Tested on Cavium EBB6800 evaluation board and Kontron S1901 board. Signed-off-by: Janne Huttunen <[email protected]> Signed-off-by: Aaro Koskinen <[email protected]> Acked-by: David Daney <[email protected]> Cc: David Daney <[email protected]> Cc: [email protected] Cc: Janne Huttunen <[email protected]> Cc: Aaro Koskinen <[email protected]> Cc: Greg Kroah-Hartman <[email protected]> Cc: [email protected] Patchwork: http://patchwork.linux-mips.org/patch/10970/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: pistachio: Allow to enable the external timer based clocksourceEzequiel Garcia2-0/+14
This commit introduces a new config, so the user can choose to enable the General Purpose Timer based clocksource. This option is required to have CPUFreq support. Signed-off-by: Ezequiel Garcia <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: James Hartley <[email protected]> Cc: Govindraj Raja <[email protected]> Cc: Damien Horsley <[email protected]> Cc: James Hogan <[email protected]> Cc: Ezequiel Garcia <[email protected]> Cc: Ezequiel Garcia <[email protected]> Patchwork: http://patchwork.linux-mips.org/patch/10887/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03CLOCKSOURCE: Add Pistachio clocksource-only driverEzequiel Garcia3-0/+222
The Pistachio SoC provides four general purpose timers, and allow to implement a clocksource driver. This driver can be used as a replacement for the MIPS GIC and MIPS R4K clocksources and sched clocks, which are clocked from the CPU clock. Given the general purpose timers are clocked from an independent clock, this new clocksource driver will be useful to introduce CPUFreq support for Pistachio machines. Signed-off-by: Ezequiel Garcia <[email protected]> Signed-off-by: Govindraj Raja <[email protected]> Reviewed-by: Thomas Gleixner <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Andrew Bresticker <[email protected]> Cc: James Hartley <[email protected]> Cc: Damien Horsley <[email protected]> Cc: James Hogan <[email protected]> Cc: Ezequiel Garcia <[email protected]> Cc: Ezequiel Garcia <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10899/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03Documentation: dt: Add Pistachio SoC general purpose timer binding documentEzequiel Garcia1-0/+28
Add a device-tree binding document for the clocksource driver provided by Pistachio SoC general purpose timers. Signed-off-by: Ezequiel Garcia <[email protected]> Reviewed-by: Andrew Bresticker <[email protected]> Cc: [email protected] Cc: [email protected] Cc: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: James Hartley <[email protected]> Cc: Govindraj Raja <[email protected]> Cc: Damien Horsley <[email protected]> Cc: James Hogan <[email protected]> Cc: Ezequiel Garcia <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10783/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03CLOCKSOURCE: mips-gic: Update clockevent frequency on clock rate changesEzequiel Garcia1-1/+30
This commit introduces the clockevent frequency update, using a clock notifier. It will be used to support CPUFreq on platforms using MIPS GIC based clockevents. Signed-off-by: Ezequiel Garcia <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: Andrew Bresticker <[email protected]> Cc: James Hartley <[email protected]> Cc: Govindraj Raja <[email protected]> Cc: Damien Horsley <[email protected]> Cc: James Hogan <[email protected]> Cc: Ezequiel Garcia <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10782/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Kconfig: Enable common clock framework for Malta and SEAD3Guenter Roeck1-0/+2
Now that we're ready to enable COMMON_CLK for GIC platforms do so for Malta and SEAD3. The only other user of the GIC Pistachio does already do so. [[email protected]: Rewrite the commit message because applied in the right order there is no breakage thus no fix required.] Signed-off-by: Guenter Roeck <[email protected]> Cc: Ezequiel Garcia <[email protected]> Cc: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/11038/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03CLOCKSOURCE: mips-gic: Split clocksource and clockevent initializationEzequiel Garcia1-5/+8
This is preparation work for the introduction of clockevent frequency update with a clock notifier. This is only possible when the device is passed a clk struct, so let's split the legacy and devicetree initialization. Reviewed-by: Andrew Bresticker <[email protected]> Signed-off-by: Ezequiel Garcia <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: James Hartley <[email protected]> Cc: Govindraj Raja <[email protected]> Cc: Damien Horsley <[email protected]> Cc: James Hogan <[email protected]> Cc: Ezequiel Garcia <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10781/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03CLOCKSOURCE: mips-gic: Add missing error returns checksEzequiel Garcia1-3/+13
This commit adds the required checks on the functions that return an error. Some of them are not critical, so only a warning is printed. Signed-off-by: Ezequiel Garcia <[email protected]> Reviewed-by: Andrew Bresticker <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: James Hartley <[email protected]> Cc: Govindraj Raja <[email protected]> Cc: Damien Horsley <[email protected]> Cc: James Hogan <[email protected]> Cc: Ezequiel Garcia <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10780/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03CLOCKSOURCE: mips-gic: Enable the clock before using itEzequiel Garcia1-1/+6
For the clock to be used (e.g. get its rate through clk_get_rate) it should be prepared and enabled first. Also, while the clock is enabled the driver must hold a reference to it, so let's remove the call to clk_put. Reviewed-by: Andrew Bresticker <[email protected]> Signed-off-by: Ezequiel Garcia <[email protected]> Acked-by: Daniel Lezcano <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: Thomas Gleixner <[email protected]> Cc: James Hartley <[email protected]> Cc: Govindraj Raja <[email protected]> Cc: Damien Horsley <[email protected]> Cc: James Hogan <[email protected]> Cc: Ezequiel Garcia <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10779/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Tidy up FPU context switchingPaul Burton3-65/+18
Rather than saving the scalar FP or vector context in the assembly resume function, reuse the existing C code we have in fpu.h to do exactly that. This reduces duplication, results in a much easier to read resume function & should allow the compiler to optimise out more MSA code due to is_msa_enabled()/cpu_has_msa being known-zero at compile time for kernels without MSA support. Signed-off-by: Paul Burton <[email protected]> Cc: [email protected] Cc: Leonid Yegoshin <[email protected]> Cc: Maciej W. Rozycki <[email protected]> Cc: [email protected] Cc: James Hogan <[email protected]> Cc: Markos Chandras <[email protected]> Cc: Manuel Lauss <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/10830/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Netlogic: Fix 0x0x prefixes.Antonio Ospite1-1/+1
Fix the 0x0x prefix in integer constants, in this case the registers interval is actually 0x8065 .. 0x80A4 as confirmed some lines above in the code. Signed-off-by: Antonio Ospite <[email protected]> Cc: [email protected] Cc: Jiri Kosina <[email protected]> Patchwork: https://patchwork.linux-mips.org/patch/9908/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03Documentation: MIPS now supports uprobes.Ralf Baechle1-1/+1
Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Add uprobes support.Ralf Baechle11-2/+597
Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Set trap_no field in thread_struct on exception.Ralf Baechle4-18/+21
This reverts commit 7281cd22973008a782860e48ed8d85d00204168c and adds actual functionality to use the field.
2015-09-03MIPS: Netlogic: NAND IRQ mappingSubhendu Sekhar Behera1-0/+2
Add NAND IRQ mapping for XLP9xx processor. Signed-off-by: Subhendu Sekhar Behera <[email protected]> Signed-off-by: Jayachandran C <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10820/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Netlogic: set ARCH_REQUIRE_GPIOLIB for XLP platformKamlakant Patel1-0/+1
This is needed to enable GPIO framework support for Netlogic XLP platform. Signed-off-by: Kamlakant Patel <[email protected]> Signed-off-by: Jayachandran C <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10818/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Netlogic: add device tree entry for XLP GPIOKamlakant Patel5-0/+58
Add GPIO entries to the Netlogic XLP device tree files. Signed-off-by: Kamlakant Patel <[email protected]> Signed-off-by: Jayachandran C <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10819/ Signed-off-by: Ralf Baechle <[email protected]>
2015-09-03MIPS: Netlogic: Use chip_data for irq_chip methodsKamlakant Patel2-16/+16
Update mips/netlogic/common/irq.c and mips/pci/msi-xlp.c to use chip_data to store interrupt controller data pointer. It uses handler_data now, and that causes errors when an API (like the GPIO subsystem) tries to use the handler data. Signed-off-by: Kamlakant Patel <[email protected]> Signed-off-by: Jayachandran C <[email protected]> Cc: [email protected] Patchwork: https://patchwork.linux-mips.org/patch/10817/ Signed-off-by: Ralf Baechle <[email protected]>
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