aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2020-03-20dt-bindings: phy: qcom-qusb2: Add support for overriding Phy tuning parametersSandeep Maheswaram1-1/+31
Add support for overriding QUSB2 V2 phy tuning parameters in device tree bindings. Signed-off-by: Sandeep Maheswaram <[email protected]> Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: qcom-qusb2: Add generic QUSB2 V2 PHY supportSandeep Maheswaram1-9/+9
Add generic QUSB2 V2 PHY table so the respective phys can use the same table. Signed-off-by: Sandeep Maheswaram <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy: qcom,qusb2: Add compatibles for QUSB2 V2 phy and SC7180Sandeep Maheswaram1-4/+10
Add compatibles for generic QUSB2 V2 phy which can be used for sdm845 and sc7180. Signed-off-by: Sandeep Maheswaram <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy: qcom,qusb2: Convert QUSB2 phy bindings to yamlSandeep Maheswaram2-68/+149
Convert QUSB2 phy bindings to DT schema format using json-schema. Signed-off-by: Sandeep Maheswaram <[email protected]> Reviewed-by: Matthias Kaehlcke <[email protected]> Reviewed-by: Stephen Boyd <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: rk-inno-usb2: Decrease verbosity of repeating log.Christoph Muellner1-1/+1
phy-rockchip-inno-usb2 logs the message "phy-ff2c0000.syscon:[email protected]: charger = INVALID_CHARGER" constantly with a frequency of about 1 Hz and a verbosity level of INFO. As this is clearly annoying, this patch decreases the log level to DEBUG. Signed-off-by: Christoph Muellner <[email protected]> Reviewed-by: Heiko Stuebner <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: amlogic: Add Amlogic A1 USB2 PHY DriverHanjie Lin1-26/+59
This adds support for the USB2 PHY found in the Amlogic A1 SoC Family. It supports host mode only. Signed-off-by: Yue Wang <[email protected]> Signed-off-by: Hanjie Lin <[email protected]> Reviewed-by: Martin Blumenstingl <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy: Add Amlogic A1 USB2 PHY BindingsHanjie Lin1-0/+14
Add the Amlogic A1 Family USB2 PHY Bindings It supports Host mode only. Signed-off-by: Yue Wang <[email protected]> Signed-off-by: Hanjie Lin <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: ti: gmii-sel: add support for am654x/j721e socGrygorii Strashko1-0/+19
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding support for TI AM654x/J721E SoCs PHY interface selection. Signed-off-by: Grygorii Strashko <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy: ti: gmii-sel: add support for am654x/j721e socGrygorii Strashko1-0/+1
TI AM654x/J721E SoCs have the same PHY interface selection mechanism for CPSWx subsystem as TI SoCs (AM3/4/5/DRA7), but registers and bit-fields placement is different. This patch adds corresponding compatible strings to enable support for TI AM654x/J721E SoCs. Signed-off-by: Grygorii Strashko <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: qualcomm: usb: Add SuperSpeed PHY driverJorge Ramirez-Ortiz3-0/+256
Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the 20nm and 28nm process nodes. Based on Sriharsha Allenki's <[email protected]> original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by: Jorge Ramirez-Ortiz <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Cc: Sriharsha Allenki's <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Philipp Zabel <[email protected]> Cc: [email protected] Cc: [email protected] Reviewed-by: Philipp Zabel <[email protected]> Tested-by: Bjorn Andersson <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: Add Qualcomm USB SuperSpeed PHY bindingsJorge Ramirez-Ortiz1-0/+83
Binding description for Qualcomm's Synopsys 1.0.0 SuperSpeed PHY. This PHY appears in a number of SoCs on various flavors of 20nm and 28nm nodes. This commit adds information related to the 28nm node only. Based on Sriharsha Allenki's <[email protected]> original definitions. [bod: converted to yaml format] Signed-off-by: Jorge Ramirez-Ortiz <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Cc: [email protected] Cc: [email protected] Reviewed-by: Rob Herring <[email protected]> Tested-by: Bjorn Andersson <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driverShawn Guo3-0/+427
Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. The PHY can come in two flavours femtoPHY or picoPHY. This commit adds support for the femtoPHY with the possibility of extending to the picoPHY with additional future commits. Both PHYs are on a 28 nanometer process node. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and from driver name Extended commit log to mention femtoPHY and picoPHY for future reference.] Signed-off-by: Shawn Guo <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Philipp Zabel <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Cc: [email protected] Cc: [email protected] Tested-by: Bjorn Andersson <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY bindingSriharsha Allenki1-0/+90
Adds bindings for Qualcomm's 28 nm USB PHY supporting Low-Speed, Full-Speed and Hi-Speed USB connectivity on Qualcomm chipsets. [bod: Converted to YAML. Changed name dropping snps, 28nm components] Signed-off-by: Sriharsha Allenki <[email protected]> Signed-off-by: Anu Ramanathan <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Shawn Guo <[email protected]> Reviewed-by: Rob Herring <[email protected]> Tested-by: Bjorn Andersson <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy: remove qcom-dwc3-usb-phyJorge Ramirez-Ortiz1-37/+0
This binding is not used by any driver. Signed-off-by: Jorge Ramirez-Ortiz <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: phy-mtk-tphy: add a new reference clockChunfeng Yun1-1/+18
Usually the digital and analog phys use the same reference clock, but some platforms have two separate reference clocks for each of them, so add another optional clock to support them. In order to keep the clock names consistent with PHY IP's, change the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: phy-mtk-tphy: remove unused u3phya_ref clockChunfeng Yun1-18/+0
The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it, this can avoid confusion when support new platforms Signed-off-by: Chunfeng Yun <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: phy-mtk-tphy: make the ref clock optionalChunfeng Yun1-1/+1
Sometimes the reference clock of USB3 PHY comes from oscillator directly, and no need refer to a fixed-clock in DTS anymore if make it optional. Signed-off-by: Chunfeng Yun <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: phy-mtk-tphy: add a property for internal resistanceChunfeng Yun1-2/+14
This is used to tune J-K voltage by internal R (resistance), the range is [0, 31], the resistance value is about 6.9K ohm for 0, 3.8K ohm for 31, and the step is 1K ohm Signed-off-by: Chunfeng Yun <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: phy-mtk-tphy: add a property for disconnect thresholdChunfeng Yun1-2/+15
This is used to tune the threshold of disconnect, the index range is [0, 15], the threshold voltage is about 400mV for 0, 700mV for 15, and the step is 20mV. Signed-off-by: Chunfeng Yun <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy-mtk-tphy: add the properties about address mappingChunfeng Yun1-0/+10
Add three required properties about the address mapping, including '#address-cells', '#size-cells' and 'ranges' Signed-off-by: Chunfeng Yun <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy-mtk-tphy: add a new reference clockChunfeng Yun1-2/+5
Usually the digital and analog phys use the same reference clock, but on some platforms, they are separated, so add another optional clock to support it. In order to keep the clock names consistent with PHY IP's, use the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy-mtk-tphy: remove unused u3phya_ref clockChunfeng Yun1-4/+0
The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it to avoid confusion Signed-off-by: Chunfeng Yun <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy-mtk-tphy: make the ref clock optionalChunfeng Yun1-6/+7
Make the ref clock optional, then we no need refer to a fixed-clock in DTS anymore when the clock of USB3 PHY comes from oscillator directly Signed-off-by: Chunfeng Yun <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy-mtk-tphy: add two optional properties for u2phyChunfeng Yun1-0/+2
Add two optional properties, one for tuning J-K voltage by INTR, another for disconnect threshold, both of them are related with connect detection Signed-off-by: Chunfeng Yun <[email protected]> Acked-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: amlogic: G12A: Fix misuse of GENMASK macroJoe Perches1-1/+1
Arguments are supposed to be ordered high then low. Signed-off-by: Joe Perches <[email protected]> Reviewed-by: Neil Armstrong <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: qcom: qmp: Use power_on/off ops for PCIeBjorn Andersson1-3/+3
The PCIe PHY initialization requires the attached device to be present, which is primarily achieved by the PCI controller driver. So move the logic from init/exit to power_on/power_off. Signed-off-by: Bjorn Andersson <[email protected]> Reviewed-by: John Stultz <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-pcie: Add SoC-dependent phy-mode function supportKunihiko Hayashi1-7/+10
Since this phy is shared by multiple devices including USB and PCIe, it is necessary to determine which device use this phy. This patch adds SoC-dependent functions to determine a device using this phy. When there is 'socionext,syscon' property in the pcie-phy node, the driver calls SoC-dependt function instead of checking .has_syscon in SoC-dependent data. The function configures the system controller to use phy for PCIe. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-pcie: Add legacy SoC support for Pro5Kunihiko Hayashi1-11/+72
Add legacy SoC support that needs to manage gio clock and reset and to skip setting unimplemented phy parameters. This supports Pro5. This specifies only 1 port use because Pro5 doesn't set it in the power-on sequence. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-usb3hs: Change Rx sync mode to avoid communication failureKunihiko Hayashi1-4/+16
In case of using default parameters, communication failure might occur in rare cases. This sets Rx sync mode parameter to avoid the issue. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-usb3hs: Add legacy SoC support for Pro5Kunihiko Hayashi1-15/+53
Add legacy SoC support that needs to manage gio clock and reset. This supports Pro5. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: uniphier-usb3ss: Add Pro5 supportKunihiko Hayashi1-0/+4
Pro5 SoC has same scheme of USB3 ss-phy as Pro4, so the data for Pro5 is equivalent to Pro4. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy: socionext: Add Pro5 support and remove Pro4 from usb3-hsphyKunihiko Hayashi3-9/+15
This adds compatible string for Pro5 SoC that needs to manage gio clock and reset. And Pro4 SoC uses USB2 PHY instead of USB3 HS-PHY, so this removes Pro4 description from usb3-hsphy. Signed-off-by: Kunihiko Hayashi <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: socionext: Use devm_platform_ioremap_resource()Kunihiko Hayashi3-9/+3
Use devm_platform_ioremap_resource() to simplify the code. Signed-off-by: Kunihiko Hayashi <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: qcom-qmp: Add MSM8996 UFS QMP supportBjorn Andersson2-0/+111
The support for the 14nm MSM8996 UFS PHY is currently handled by the UFS-specific 14nm QMP driver, due to the earlier need for additional operations beyond the standard PHY API. Add support for this PHY to the common QMP driver, to allow us to remove the old driver. Acked-by: Rob Herring <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Add support for subnode bindingsSwapnil Jakhade1-75/+217
Implement single link subnode support to the phy driver. Add reset support including PHY reset and individual lane reset. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Add platform dependent initialization structureSwapnil Jakhade1-0/+9
Add platform dependent initialization data for Torrent PHY used in TI's J721E SoC. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Use regmap to read and write DPTX PHY registersSwapnil Jakhade1-69/+100
Use regmap to read and write DPTX specific PHY registers. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Use regmap to read and write Torrent PHY registersSwapnil Jakhade1-369/+650
Use regmap for accessing Torrent PHY registers. Modify register offsets as defined in Torrent PHY user guide. Abstract address calculation using regmap APIs. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Implement PHY configure APIsSwapnil Jakhade1-5/+431
Add support for PHY configuration APIs. These will mainly reconfigure link rate, number of lanes, voltage swing and pre-emphasis values. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Add 19.2 MHz reference clock supportSwapnil Jakhade1-17/+441
Add configuration functions for 19.2 MHz refclock support. Add register configurations for SSC support. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Refactor code for reusabilitySwapnil Jakhade1-93/+137
Add a separate function to set different power state values. Use uniform polling timeout value. Also check return values of functions for proper error handling. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Add wrapper for DPTX register accessSwapnil Jakhade1-21/+50
Add wrapper functions to read, write DisplayPort specific PHY registers to improve code readability. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Add wrapper for PHY register accessSwapnil Jakhade1-65/+77
Add a wrapper function to write Torrent PHY registers to improve code readability. Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-torrent: Adopt Torrent nomenclatureSwapnil Jakhade1-53/+58
- Change private data struct cdns_dp_phy to cdns_torrent_phy - Change module description and registration accordingly - Generic torrent functions have prefix cdns_torrent_phy_* - Functions specific to Torrent phy for DisplayPort are prefixed as cdns_torrent_dp_* Signed-off-by: Swapnil Jakhade <[email protected]> Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20phy: cadence-dp: Rename to phy-cadence-torrentYuti Amonkar3-5/+5
Rename Cadence DP PHY driver from phy-cadence-dp to phy-cadence-torrent to make it more generic for future use. Modifiy Makefile and Kconfig accordingly. Also, change driver compatible from "cdns,dp-phy" to "cdns,torrent-phy".This will not affect ABI as the driver has never been functional, and therefore do not exist in any active use case. Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-20dt-bindings: phy: Add Cadence MHDP PHY bindings in YAML format.Yuti Amonkar1-0/+143
- Add Cadence MHDP PHY bindings in YAML format. - Add Torrent PHY reference clock bindings. - Add sub-node bindings for each group of PHY lanes based on PHY type. Each sub-node includes properties such as master lane number, link reset, phy type, number of lanes etc. - Add reset support including PHY reset and individual lane reset. - Add a new compatible string used for TI SoCs using Torrent PHY. This will not affect ABI as the driver has never been functional, and therefore do not exist in any active use case. Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-03-05dt-bindings: phy: Remove Cadence MHDP PHY dt bindingYuti Amonkar1-30/+0
Remove the Cadence MHDP PHY bindings. The binding is added in next commit in YAML format. It is renamed to adopt torrent nomenclature. This will not affect ABI as the driver has never been functional, and therefore do not exist in any active use case. Signed-off-by: Yuti Amonkar <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-02-21phy: qcom: qmp: Add SDM845 QHP PCIe PHYBjorn Andersson2-0/+271
Add the GEN3 QHP PCIe PHY found in SDM845. Tested-by: Julien Massot <[email protected]> Tested-by: Vinod Koul <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-02-21phy: qcom: qmp: Add SDM845 PCIe QMP PHY supportBjorn Andersson1-0/+156
qcom_qmp_phy_init() is extended to support the additional register writes needed in PCS MISC and the appropriate sequences and resources are defined for the GEN2 PCIe QMP PHY found in SDM845. Tested-by: Vinod Koul <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
2020-02-21dt-bindings: phy-qcom-qmp: Add SDM845 PCIe to bindingBjorn Andersson1-0/+10
Add the compatible and define necessary clocks and resets for the SDM845 GEN2 QMP PCIe phy and GEN3 QHP PCIe phy. Reviewed-by: Rob Herring <[email protected]> Reviewed-by: Vinod Koul <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.