aboutsummaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorSriharsha Allenki <[email protected]>2020-03-11 19:13:55 +0000
committerKishon Vijay Abraham I <[email protected]>2020-03-20 19:34:29 +0530
commit8c51ec666d415d084922bc129a8c19ea6bfb4b2c (patch)
treee92c7b027188e5092dd6cc9f070250021081d8cb
parent1969c0d9ce963244a16e3161025c77ed14376ddd (diff)
dt-bindings: phy: Add Qualcomm Synopsys Hi-Speed USB PHY binding
Adds bindings for Qualcomm's 28 nm USB PHY supporting Low-Speed, Full-Speed and Hi-Speed USB connectivity on Qualcomm chipsets. [bod: Converted to YAML. Changed name dropping snps, 28nm components] Signed-off-by: Sriharsha Allenki <[email protected]> Signed-off-by: Anu Ramanathan <[email protected]> Signed-off-by: Bjorn Andersson <[email protected]> Signed-off-by: Shawn Guo <[email protected]> Reviewed-by: Rob Herring <[email protected]> Tested-by: Bjorn Andersson <[email protected]> Cc: Andy Gross <[email protected]> Cc: Bjorn Andersson <[email protected]> Cc: Kishon Vijay Abraham I <[email protected]> Cc: Rob Herring <[email protected]> Cc: Mark Rutland <[email protected]> Cc: Jorge Ramirez-Ortiz <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Bryan O'Donoghue <[email protected]> Signed-off-by: Kishon Vijay Abraham I <[email protected]>
-rw-r--r--Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml90
1 files changed, 90 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
new file mode 100644
index 000000000000..ca6a0836b53c
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,usb-hs-28nm.yaml
@@ -0,0 +1,90 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,usb-hs-28nm.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm Synopsys DesignWare Core 28nm High-Speed PHY
+
+maintainers:
+ - Bryan O'Donoghue <[email protected]>
+
+description: |
+ Qualcomm Low-Speed, Full-Speed, Hi-Speed 28nm USB PHY
+
+properties:
+ compatible:
+ enum:
+ - qcom,usb-hs-28nm-femtophy
+
+ reg:
+ maxItems: 1
+
+ "#phy-cells":
+ const: 0
+
+ clocks:
+ items:
+ - description: rpmcc ref clock
+ - description: PHY AHB clock
+ - description: Rentention clock
+
+ clock-names:
+ items:
+ - const: ref
+ - const: ahb
+ - const: sleep
+
+ resets:
+ items:
+ - description: PHY core reset
+ - description: POR reset
+
+ reset-names:
+ items:
+ - const: phy
+ - const: por
+
+ vdd-supply:
+ description: phandle to the regulator VDD supply node.
+
+ vdda1p8-supply:
+ description: phandle to the regulator 1.8V supply node.
+
+ vdda3p3-supply:
+ description: phandle to the regulator 3.3V supply node.
+
+required:
+ - compatible
+ - reg
+ - "#phy-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdd-supply
+ - vdda1p8-supply
+ - vdda3p3-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-qcs404.h>
+ #include <dt-bindings/clock/qcom,rpmcc.h>
+ usb2_phy_prim: phy@7a000 {
+ compatible = "qcom,usb-hs-28nm-femtophy";
+ reg = <0x0007a000 0x200>;
+ #phy-cells = <0>;
+ clocks = <&rpmcc RPM_SMD_LN_BB_CLK>,
+ <&gcc GCC_USB_HS_PHY_CFG_AHB_CLK>,
+ <&gcc GCC_USB2A_PHY_SLEEP_CLK>;
+ clock-names = "ref", "ahb", "sleep";
+ resets = <&gcc GCC_USB_HS_PHY_CFG_AHB_BCR>,
+ <&gcc GCC_USB2A_PHY_BCR>;
+ reset-names = "phy", "por";
+ vdd-supply = <&vreg_l4_1p2>;
+ vdda1p8-supply = <&vreg_l5_1p8>;
+ vdda3p3-supply = <&vreg_l12_3p3>;
+ };
+...