aboutsummaryrefslogtreecommitdiff
AgeCommit message (Collapse)AuthorFilesLines
2023-09-11drm/amd/display: do not attempt ODM power optimization if minimal transition ↵Wenjing Liu2-257/+306
doesn't exist [why] In some cases such as 8k desktop surface with 144Hz timing, we decide to enable ODM power optimization but this surface doesn't have a minimum transition state. Therefore we cannot switch off ODM power optimization seamlessly This creates path depedency on ODM power optimization decision. i.e whether or not we should switch off ODM power optimization is dependent on if the transition to switch off ODM power optimization from current state is seamless. We don't desire a path dependent power optimization policy as it is too dynamic and difficult to maintain. [how] Attempt ODM power optimization only after we can validate new state without using pipe combine. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: remove a function that does complex calculation in every ↵Wenjing Liu3-90/+0
frame but not used [why] The result of predict_pipe_split calculation is no longer used but the function is not removed. This will cause unnecessary calculation of pipe split prediction in every frame update. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdkfd: Checkpoint and restore queues on GFX11David Francis1-0/+41
The code in kfd_mqd_manager_v11.c to support criu dump and restore of queue state was missing. Added it; should be equivalent to kfd_mqd_manager_v10.c. CC: Felix Kuehling <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Add DCHUBBUB callback to report MALL statusAurabindo Pillai6-6/+34
[Why&How] For enabling automated testing, add a hook to DCHUBBUB interface so that mall status can be queried by userspace through debugfs. This removes dependence on requiring a userspace tool like UMR for querying status for MALL static screen IGT test. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Add new logs for AutoDPMTestEthan Bitnun3-1/+41
[Description] - Add new logs to be used by the AutoDPMTest - Enclose AutoDPMTest logs in settings - Add logging definition Reviewed-by: Alvin Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Ethan Bitnun <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: support main link off before specific vertical linePaul Hsieh3-3/+12
[Why] Some panels request main link off before specific vertical line. If source turn off main link after specific vertical line then panel defect will be exposed. [How] Add interface to support turn off main link before specific vertical line Reviewed-by: Robin Chen <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Adjust the MST resume flowWayne Lin1-13/+80
[Why] In drm_dp_mst_topology_mgr_resume() today, it will resume the mst branch to be ready handling mst mode and also consecutively do the mst topology probing. Which will cause the dirver have chance to fire hotplug event before restoring the old state. Then Userspace will react to the hotplug event based on a wrong state. [How] Adjust the mst resume flow as: 1. set dpcd to resume mst branch status 2. restore source old state 3. Do mst resume topology probing For drm_dp_mst_topology_mgr_resume(), it's better to adjust it to pull out topology probing work into a 2nd part procedure of the mst resume. Will have a follow up patch in drm. Reviewed-by: Chao-kai Wang <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Fix 2nd DPIA encoder AssignmentMustapha Ghaddar1-3/+1
[HOW & Why] There seems to be an issue with 2nd DPIA acquiring link encoder for tiled displays. Solution is to remove check for eng_id before we get first dynamic encoder for it Reviewed-by: Cruise Hung <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Acked-by: Stylon Wang <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: Rename KGD_MAX_QUEUES to AMDGPU_MAX_QUEUESMukul Joshi5-10/+10
Rename KGD_MAX_QUEUES to AMDGPU_MAX_QUEUES to conform with the naming convention followed in amdgpu_gfx.h. No functional change. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: do not block ODM + OPM on one side of the screenWenjing Liu1-7/+0
[why] build scaling param is overriding validation policy regarding small viewport support. Even if ODM + windowed MPO is not supported. The decision has to be made at the time of validation. When building scaling params, we might be building an initial dc state as an input to DML validation. The initial state is not supposed to be always valid and we rely on DML to modify the initial dc state and determine the final validation result. This check is pre judging validation result when building the initial dc state. This causes an issue where we are transitioning from desktop only ODM combine 2:1 to ODM bypass with 2 planes. In this case we are building an initial state with with ODM 2:1 combine + 2 planes. This is indeed not supported but DML is about to modify the state so it no longer uses ODM combine. Before it reaches DML, dc resource already fails validation because it checks that the initial state is not supported by our policy. This overrides the ODM decision to validate this state with ODM combine disabled. Therefore causes an unexpected validation failure when the secondary plane is added on one side of the screen. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Fix DML calculation errorsNicholas Susanto1-0/+2
[Why] DML calculations differ with DCN3.1 spreadsheet values due to translations errors from the visual basic code [How] Add missing calculations that set the value for DSCDelay Reviewed-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Nicholas Susanto <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: print more address info of UMC bad pageTao Zhou1-3/+9
Print out row, column and bank value of UMC error address for UMC v12. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: fallback to old RAS error message for aqua_vanjaramHawking Zhang1-2/+4
So driver doesn't generate incorrect message until the new format is settled down for aqua_vanjaram Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu/nbio4.3: set proper rmmio_remap.reg_offset for SR-IOVAlex Deucher1-0/+3
Needed for HDP flush to work correctly. Reviewed-by: Timmy Tsai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu/soc21: don't remap HDP registers for SR-IOVAlex Deucher1-1/+1
This matches the behavior for soc15 and nv. Acked-by: Christian König <[email protected]> Reviewed-by: Timmy Tsai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: [FW Promotion] Release 0.0.181.0Anthony Koo1-0/+2
- Add new params to dmub_feature_caps for checking replay support in FW Acked-by: Stylon Wang <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Don't check registers, if using AUX BL controlSwapnil Patel1-1/+3
[Why] Currently the driver looks DCN registers to access if BL is on or not. This check is not valid if we are using AUX based brightness control. This causes driver to not send out "backlight off" command during power off sequence as it already thinks it is off. [How] Only check DCN registers if we aren't using AUX based brightness control. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Swapnil Patel <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: fix retry loop testDan Carpenter1-1/+1
This loop will exit with "retry" set to -1 if it fails but the code checks for if "retry" is zero. Fix this by changing post-op to a pre-op. --retry vs retry--. Fixes: e01eeffc3f86 ("drm/amd/pm: avoid driver getting empty metrics table for the first time") Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Add dirty rect support for ReplayBhawanpreet Lakha1-1/+2
Dirty rect can be used with replay, so enable them to allow for more powersaving. Reviewed-by: Sun peng Li <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: set default return value for ODM Combine debugfsAurabindo Pillai1-1/+1
[Why&How] Set a default return value of -ENOTSUPP to indicate that the hardware does not support querying ODM Combine mode. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11Revert "drm/amd: Disable S/G for APUs when 64GB or more host memory"Hamza Mahfooz3-29/+3
This reverts commit 70e64c4d522b732e31c6475a3be2349de337d321. Since, we now have an actual fix for this issue, we can get rid of this workaround as it can cause pin failures if enough VRAM isn't carved out by the BIOS. Cc: [email protected] # 6.1+ Acked-by: Harry Wentland <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: fix the white screen issue when >= 64GB DRAMYifan Zhang1-5/+9
Dropping bit 31:4 of page table base is wrong, it makes page table base points to wrong address if phys addr is beyond 64GB; dropping page_table_start/end bit 31:4 is unnecessary since dcn20_vmid_setup will do that. Also, while we are at it, cleanup the assignments using upper_32_bits()/lower_32_bits() and AMDGPU_GPU_PAGE_SHIFT. Cc: [email protected] Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2354 Fixes: 81d0bcf99009 ("drm/amdgpu: make display pinning more flexible (v2)") Acked-by: Harry Wentland <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Co-developed-by: Hamza Mahfooz <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Don't lock phantom pipe on disablingAlvin Lee1-1/+2
[Description] - When disabling a phantom pipe, we first enable the phantom OTG so the double buffer update can successfully take place - However, want to avoid locking the phantom otherwise setting DPG_EN=1 for the phantom pipe is blocked (without this we could hit underflow due to phantom HUBP being blanked by default) Reviewed-by: Samson Tam <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Blank phantom OTG before enablingAlvin Lee6-49/+68
[Description] Before enabling the phantom OTG for an update we must enable DPG to avoid underflow. Reviewed-by: Samson Tam <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdkfd: Update CU masking for GFX 9.4.3Mukul Joshi7-28/+56
The CU mask passed from user-space will change based on different spatial partitioning mode. As a result, update CU masking code for GFX9.4.3 to work for all partitioning modes. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdkfd: Update cache info reporting for GFX v9.4.3Mukul Joshi3-37/+51
Update cache info reporting in sysfs to report the correct number of CUs and associated cache information based on different spatial partitioning modes. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: add channel index table for UMC v12Tao Zhou3-0/+20
Get UMC phyical channel index according to node id, umc instance and channel instance. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/pm: enable smu_v13_0_6 mca debug mode when UMC RAS feature is enabledYang Wang2-1/+28
v1: enable smu_v13_0_6 mca debug mode when UMC RAS feature is enabled. v2: use amdgpu_ras_is_supported() helper function instead bitmask check. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/pm: update smu_v13_0_6 smu headerYang Wang2-1/+5
update smu firmware header to support smu mca debug feature. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: add address conversion for UMC v12Tao Zhou3-1/+159
Convert MCA error address to physical address and find out all pages in one physical row. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: Use default reset method handlerLijo Lazar1-9/+7
When reset method is not passed in reset context, look for the handler for default reset method. On Aldebaran, default reset method for SOCs connected to CPU over XGMI is MODE2. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Tested-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: Store CU info from all XCCs for GFX v9.4.3Mukul Joshi14-65/+60
Currently, we store CU info only for a single XCC assuming that it is the same for all XCCs. However, that may not be true. As a result, store CU info for all XCCs. This info is later used for CU masking. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd: Fix the flag setting code for interrupt requestMa Jun1-19/+26
[1] Remove the irq flags setting code since pci_alloc_irq_vectors() handles these flags. [2] Free the msi vectors in case of error. Signed-off-by: Ma Jun <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: fix unsigned error codesLang Yu1-4/+3
Fixes: 5d5eac7e8303 ("drm/amdgpu: add selftest framework for UMSCH") Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reported-by: Dan Carpenter <[email protected]> Link: https://lore.kernel.org/all/ZPhddADtKmOuVyDq@lang-desktop Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdkfd: Fix unaligned 64-bit doorbell warningMukul Joshi1-0/+2
This patch fixes the following unaligned 64-bit doorbell warning seen when submitting packets on HIQ on GFX v9.4.3 by making the HIQ doorbell 64-bit aligned. The warning is seen when GPU is loaded in any mode other than SPX mode. [ +0.000301] ------------[ cut here ]------------ [ +0.000003] Unaligned 64-bit doorbell [ +0.000030] WARNING: /amdkfd/kfd_doorbell.c:339 write_kernel_doorbell64+0x72/0x80 [ +0.000003] RIP: 0010:write_kernel_doorbell64+0x72/0x80 [ +0.000004] RSP: 0018:ffffc90004287730 EFLAGS: 00010246 [ +0.000005] RAX: 0000000000000000 RBX: 0000000000000000 RCX: 0000000000000000 [ +0.000003] RDX: 0000000000000001 RSI: ffffffff82837c71 RDI: 00000000ffffffff [ +0.000003] RBP: ffffc90004287748 R08: 0000000000000003 R09: 0000000000000001 [ +0.000002] R10: 000000000000001a R11: ffff88a034008198 R12: ffffc900013bd004 [ +0.000003] R13: 0000000000000008 R14: ffffc900042877b0 R15: 000000000000007f [ +0.000003] FS: 00007fa8c7b62000(0000) GS:ffff889f88400000(0000) knlGS:0000000000000000 [ +0.000004] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ +0.000003] CR2: 000056111c45aaf0 CR3: 00000001414f2002 CR4: 0000000000770ee0 [ +0.000003] PKRU: 55555554 [ +0.000002] Call Trace: [ +0.000004] <TASK> [ +0.000006] kq_submit_packet+0x45/0x50 [amdgpu] [ +0.000524] pm_send_set_resources+0x7f/0xc0 [amdgpu] [ +0.000500] set_sched_resources+0xe4/0x160 [amdgpu] [ +0.000503] start_cpsch+0x1c5/0x2a0 [amdgpu] [ +0.000497] kgd2kfd_device_init.cold+0x816/0xb42 [amdgpu] [ +0.000743] amdgpu_amdkfd_device_init+0x15f/0x1f0 [amdgpu] [ +0.000602] amdgpu_device_init.cold+0x1813/0x2176 [amdgpu] [ +0.000684] ? pci_bus_read_config_word+0x4a/0x80 [ +0.000012] ? do_pci_enable_device+0xdc/0x110 [ +0.000008] amdgpu_driver_load_kms+0x1a/0x110 [amdgpu] [ +0.000545] amdgpu_pci_probe+0x197/0x400 [amdgpu] Fixes: c31866651086 ("drm/amdgpu: use doorbell mgr for kfd kernel doorbells") Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdkfd: Fix reg offset for setting CWSR grace periodMukul Joshi7-16/+8
This patch fixes the case where the code currently passes absolute register address and not the reg offset, which HWS expects, when sending the PM4 packet to set/update CWSR grace period. Additionally, cleanup the signature of build_grace_period_packet_info function as it no longer needs the inst parameter. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Jonathan Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: clean up one inconsistent indentingYang Li1-2/+2
drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn35/dcn35_fpu.c:260 dcn35_update_bw_bounding_box_fpu() warn: inconsistent indenting Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Add umc v12_0 ras functionsCandice Li4-3/+328
Add umc v12_0 ras error querying. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Fix refclk reporting for SMU v13.0.6Lijo Lazar1-1/+2
SMU v13.0.6 SOCs have 100MHz reference clock. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Correct se_num and reg_inst for gfx v9_4_3 ras countersHawking Zhang1-20/+20
gfx_v9_4_3_ue|ce_reg_list is an array per gfx core instance correct the settings of se_num and reg_inst for some of gfx ras counters so all the available register instances can be polled for ras status. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Restrict bootloader wait to SMUv13.0.6Lijo Lazar1-4/+14
Restrict the wait for boot loader steady state only to SMUv13.0.6. For older SOCs, ASIC init has a longer wait period and that takes care. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Add only valid firmware version nodesLijo Lazar1-4/+29
Show only firmware version attributes that have valid version. Hide others. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: fix incompatible types in conditional expressionLang Yu2-2/+4
Use proper type. Fixes: 9d4346bdbc64 ("drm/amdgpu: add VPE 6.1.0 support") Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Solomon Chiu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reported-by: kernel test robot <[email protected]> Link: https://lore.kernel.org/oe-kbuild-all/[email protected] Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Use min_t to replace minSrinivasan Shanmugam6-14/+14
Use min_t to replace min, min_t is a bit fast because min use twice typeof. And using min_t is cleaner here since the min/max macros do a typecheck while min_t()/max_t() to an explicit type cast. Fixes the below checkpatch warning: WARNING: min() should probably be min_t() Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd: Add umc v12_0_0 ip headersCandice Li2-0/+128
Add umc v12_0_0 ip headers. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Update amdgpu_device_indirect_r/wreg_extCandice Li1-2/+2
Only calculate pcie_index_hi for register address greater than 32bits. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Add RREG64_PCIE_EXT/WREG64_PCIE_EXT functionsCandice Li3-0/+128
Add 64bits register access support on register whose address is greater than 32bits. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Declare array with strings as pointers constantSrinivasan Shanmugam2-5/+5
This warning is for the declaration of a static array, and it is recommended to declare it as type "static const char * const" instead of "static const char *". an array pointer declared as type "static const char *" can point to a different character constant because the pointer is mutable. However, if it is declared as type "static const char * const", the pointer will point to an immutable character constant, preventing it from being modified which can better ensure the safety and stability of the program. Fixes the below: WARNING: static const char * array should probably be static const char * const Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06amdgpu/pm: Optimize emit_clock_levels for aldebaran - part 3Darren Powell1-55/+27
split switch statement into two and consolidate the common code for printing most of the types of clock speeds Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06amdgpu/pm: Optimize emit_clock_levels for aldebaran - part 2Darren Powell1-14/+13
Use variables to remove ternary expression in print statement and improve readability. This will help to optimize the code duplication in the switch statement Also Changed: replaced single_dpm_table->count as iterator in for loops with safer clocks_num_levels value replaced dpm_table.value usage with local var clocks_mhz Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.