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2023-09-20drm/amd/display: Add z8_marks related in dml for DCN35Charlene Liu2-1/+36
Add z8 watermarks to struct for DCN35. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Fix dig register undefinedDuncan Ma1-1/+1
[Why] Some of the stream encoder registers have register offset address 0. It is causing no display in some scenarios due to DIG_FE was not setup correctly and was not enabled. [How] Fix stream encoder register define list. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: fix the ability to use lower resolution modes on eDPHamza Mahfooz1-2/+2
On eDP we can receive invalid modes from dm_update_crtc_state() for entirely new streams for which drm_mode_set_crtcinfo() shouldn't be called on. So, instead of calling drm_mode_set_crtcinfo() from within create_stream_for_sink() we can instead call it from amdgpu_dm_connector_mode_valid(). Since, we are guaranteed to only call drm_mode_set_crtcinfo() for valid modes from that function (invalid modes are rejected by that callback) and that is the only user of create_validate_stream_for_sink() that we need to call drm_mode_set_crtcinfo() for (as before commit cb841d27b876 ("drm/amd/display: Always pass connector_state to stream validation"), that is the only place where create_validate_stream_for_sink()'s dm_state was NULL). Cc: [email protected] Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2693 Fixes: cb841d27b876 ("drm/amd/display: Always pass connector_state to stream validation") Tested-by: Mark Broadworth <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Temporarily disable clock gatingCharlene Liu1-0/+1
Temporarily disable dchubbub clock gating, registers: .DISPCLK_R_DCHUBBUB_GATE_DIS .DCFCLK_R_DCHUBBUB_GATE_DIS need to follow up with sequence issue. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Leo Chen <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: disable clock gating logicMuhammad Ahmed1-2/+2
Disable clock gating logic. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Add reset for SYMCLKC_FE_SRC_SELTaimur Hassan1-10/+15
To prevent confusion after symclk has already been disabled. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Taimur Hassan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Rework coredump to use memory dynamicallyAndré Almeida2-28/+49
Instead of storing coredump information inside amdgpu_device struct, move if to a proper separated struct and allocate it dynamically. This will make it easier to further expand the logged information. Signed-off-by: André Almeida <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Remove unused display_content_supportJoshua Ashton2-15/+0
This was never filled in and thus never truly used. Checking the EDID for content_type support is not required for sending the avi infoframe packet. v2: - rebase to amd-staging-drm-next Reviewed-by: Melissa Wen <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/display: Hook up 'content type' property for HDMIJoshua Ashton3-48/+54
Implements the 'content type' property for HDMI connectors. Verified by checking the avi infoframe on a connected TV. This also simplifies a lot of the code in that area as well, there were a lot of temp variables doing very little and unnecessary logic that was quite confusing. It is not necessary to check for support in the EDID before sending a 'content type' value in the avi infoframe also. v2: - rebase to amd-staging-drm-next - mark CRTC state for reset if content_type differs Reviewed-by: Harry Wentland <[email protected]> (v1) Signed-off-by: Joshua Ashton <[email protected]> Co-developed-by: Melissa Wen <[email protected]> Signed-off-by: Melissa Wen <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: fix a memory leak in amdgpu_ras_feature_enableCong Liu1-0/+1
This patch fixes a memory leak in the amdgpu_ras_feature_enable() function. The leak occurs when the function sends a command to the firmware to enable or disable a RAS feature for a GFX block. If the command fails, the kfree() function is not called to free the info memory. Fixes: 9f051d6ff13f ("drm/amdgpu: Free ras cmd input buffer properly") Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Cong Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Fix vbios version string searchLijo Lazar1-1/+18
Search for vbios version string in STRING_OFFSET-ATOM_ROM_HEADER region first. If those offsets are not populated, use the hardcoded region. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20Revert "drm/amdgpu: Report vbios version instead of PN"Lijo Lazar1-1/+1
This reverts commit 7748ce5b69581325cae40c2134088820f0957902. vbios_version sysfs node is used to identify Part Number also. Revert to the same so that it doesn't break scripts/software which parse this. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/pm: add smu_13_0_6 mca dump supportYang Wang2-0/+559
v1: implement smu_v13_0_6 mca bank interface. v2: - remove unnecessary lock - move MCMP1_* macros to mp_13_0_6_sh_mask.h file Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/pm: update smu_v13_0_6 ppsmc headerYang Wang4-2/+100
update smu header to support mca dump interface. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Add EXT_COHERENT memory allocation flagsDavid Francis8-3/+30
These flags (for GEM and SVM allocations) allocate memory that allows for system-scope atomic semantics. On GFX943 these flags cause caches to be avoided on non-local memory. On all other ASICs they are identical in functionality to the equivalent COHERENT flags. Corresponding Thunk patch is at https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/pull/88 Reviewed-by: David Yat Sin <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdkfd: fix add queue process context clear without runtime enableJonathan Kim1-2/+4
There are cases where HSA runtime is not enabled through the AMDKFD_IOC_RUNTIME_ENABLE call when adding queues and the MES ADD_QUEUE API should clear the MES process context instead of SET_SHADER_DEBUGGER. Such examples are legacy HSA runtime builds that do not support the current exception handling and running KFD tests. The only time ADD_QUEUE.skip_process_ctx_clear is required is for debugger use cases where a debugged process is always runtime enabled when adding a queue. Tested-by: Shikai Guo <[email protected]> Signed-off-by: Jonathan Kim <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: add amdgpu mca debug sysfs supportYang Wang3-0/+120
add amdgpu mca debug sysfs support. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: add VPE IP discovery info to HW IP info queryAlex Deucher1-0/+4
Add missing IP discovery info. Reviewed-by: Christian König <[email protected]> Reviewed-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: add amdgpu smu mca dump feature supportYang Wang2-0/+129
add amdgpu smu mca dump feature support. Signed-off-by: Yang Wang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20Documentation/amdgpu: Modify pp_dpm_*clk detailsLijo Lazar1-1/+9
pp_dpm_*clk nodes also could show the frequencies when a clock is in 'sleep' state. Add documentation related to that. Signed-off-by: Lijo Lazar <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd: Enable seamless boot by default on newer ASICsMario Limonciello1-11/+4
Seamless boot can technically be supported as far back as DCN1 but to avoid regressions on older hardware, enable it for DCN3 and later. If users report using the module parameter that it works on older ASICs as well, this can be adjusted. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd: Add a module parameter for seamless bootMario Limonciello3-3/+26
The module parameter can be used to test more easily enabling seamless boot support on additional ASICs. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd: Add HDP flush during jpeg initTimmy Tsai1-0/+3
During jpeg init, CPU writes to frame buffer which can be cached by HDP, occasionally causing invalid header to be sent to MMSCH. Perform HDP flush after writing to frame buffer before continuing with jpeg init sequence. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Timmy Tsai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd: Move seamless boot check out of displayMario Limonciello4-24/+23
This will allow base driver to dictate whether seamless should be enabled. No intended functional changes. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd: Drop special case for yellow carp without discoveryMario Limonciello1-6/+0
`amdgpu_gmc_get_vbios_allocations` has a special case for how to bring up yellow carp when amdgpu discovery is turned off. As this ASIC ships with discovery turned on, it's generally dead code and worse it causes `adev->mman.keep_stolen_vga_memory` to not be initialized for yellow carp. Remove it. Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/pm:Fix GFX deep sleep clock reportingLijo Lazar1-1/+9
For SMU v13.0.6, keep GFX deep sleep clock reporting style consistent with that of other clocks. Sample format below. S: 78Mhz * 0: 600Mhz 1: 800Mhz Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amd/pm: Fix clock reporting for SMUv13.0.6Lijo Lazar1-97/+62
On SMU v13.0.6, effective clocks are reported by FW which won't exactly match with DPM level. Report the current clock based on the values matching closest to the effective clock. Also, when deep sleep is applied to a clock, report it with a special level "S:" as in sample clock levels below S: 19Mhz * 0: 615Mhz 1: 800Mhz 2: 888Mhz 3: 1000Mhz Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-20drm/amdgpu: Use function for IP version checkLijo Lazar94-593/+714
Use an inline function for version check. Gives more flexibility to handle any format changes. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-12drm/amdgpu: add remap_hdp_registers callback for nbio 7.11Alex Deucher1-0/+9
Implement support for remapping the HDP aperture registers for NBIO 7.11. Reviewed-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-12drm/amdgpu: add vcn_doorbell_range callback for nbio 7.11Alex Deucher1-0/+22
Implement support for setting up the VCN doorbell range for NBIO 7.11. Reviewed-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-12drm/amdkfd: Insert missing TLB flush on GFX10 and laterHarish Kasiviswanathan1-2/+1
Heavy-weight TLB flush is required after unmap on all GPUs for correctness and security. Signed-off-by: Harish Kasiviswanathan <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: Handle null atom context in VBIOS info ioctlDavid Francis1-6/+11
On some APU systems, there is no atom context and so the atom_context struct is null. Add a check to the VBIOS_INFO branch of amdgpu_info_ioctl to handle this case, returning all zeroes. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: David Francis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: Create an option to disable soft recoveryAndré Almeida3-1/+13
Create a module option to disable soft recoveries on amdgpu, making every recovery go through the device reset path. This option makes easier to force device resets for testing and debugging purposes. Signed-off-by: André Almeida <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: Merge debug module parametersAndré Almeida7-25/+45
Merge all developer debug options available as separated module parameters in one, making it obvious that are for developers. Drop the obsolete module options in favor of the new ones. Signed-off-by: André Almeida <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: fix replay_mode kernel-doc warningRandy Dunlap1-1/+1
Fix the typo in the kernel-doc for @replay_mode to prevent kernel-doc warnings: drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:623: warning: Incorrect use of kernel-doc format: * @replay mode: Replay supported drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:626: warning: Function parameter or member 'replay_mode' not described in 'amdgpu_hdmi_vsdb_info' Fixes: ec8e59cb4e0c ("drm/amd/display: Get replay info from VSDB") Signed-off-by: Randy Dunlap <[email protected]> Reported-by: kernel test robot <[email protected]> Cc: Bhawanpreet Lakha <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Leo Li <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: clean up some inconsistent indentingJiapeng Chong1-3/+2
No functional modification involved. drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c:2476 link_set_dpms_on() warn: if statement not indented. Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6502 Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: add skip_implict_edp_power_control flag for dcn32Ian Chen1-2/+4
Add flag skip_implict_edp_power_control check in function dcn32_disable_link_output to fix DCN35 issue. Reviewed-by: Robin Chen <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Ian Chen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: minior logging improvementsWenjing Liu2-6/+11
[how] - Add minimial transition log with reason and base state. - Do not log set dpms interfaces for virtual signal in stream. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: do not skip ODM minimal transition based on new stateWenjing Liu1-3/+3
[why] During 8k video plane resizing we could transition from MPC combine mode back to ODM combine 2:1 + 8k video plane. In this transition minimal transition state is based on new state with ODM combine enabled. We are skipping this and it causes corruption because we have to reassign a current DPP pipe to a different MPC blending tree which is not supported seamlessly. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: move odm power optimization decision after subvp optimizationWenjing Liu1-4/+5
[why] ODM power optimization excludes subvp power optimization but subvp optimization can override ODM power optimization even if subvp optimization configuration is not found. This happens with 4k144hz + 1 5k desktop plane. We could have applied ODM power optimization however this is overridden by subvp but subvp ends up deciding not apply its optimization. [how] Move ODM power optimization decision after subvp so it will try ODM power optimization after subvp optimization is not possible. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: add seamless pipe topology transition checkWenjing Liu5-0/+68
[why] We have a few cases where we need to perform update topology update in dc update interface. However some of the updates are not seamless This could cause user noticible glitches. To enforce seamless transition we are adding a checking condition and error logging so the corruption as result of non seamless transition can be easily spotted. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: 3.2.250Aric Cyr1-1/+1
Acked-by: Stylon Wang <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Fix MST recognizes connected displays as oneMuhammad Ahmed3-20/+20
[What] MST now recognizes both connected displays Reviewed-by: Charlene Liu <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Muhammad Ahmed <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: fix some non-initialized register mask and settingCharlene Liu4-18/+65
[why] fix some non-initialized register mask and update golden setting Reviewed-by: Duncan Ma <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Add check for vrr_active_fixedAustin Zheng3-5/+5
Why: vrr_active_fixed should also be checked when determining if DRR is in use How: Add check for vrr_active_fixed when allow_freesync and vrr_active_variable are also checked Reviewed-by: Alvin Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Austin Zheng <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: dc cleanup for testsSridevi Arvindekar1-1/+1
[WHY&HOW] Code cleanup found in internal tests Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Sridevi Arvindekar <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amdgpu: add type conversion for gc infoYifan Zhang1-3/+3
gc info usage misses type conversion. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: Drop unused registersQingqing Zhuo1-2/+0
[Why & How] Some registers are never used in the driver but defined. Remove them. Reviewed-by: Roman Li <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: add dp dto programming function to dccgDillon Varone2-0/+11
[WHY&HOW] Add support for programming dp dto via dccg. Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-11drm/amd/display: only allow ODM power optimization if surface is within ↵Wenjing Liu2-0/+63
guaranteed viewport size [why] Current dc update design has limitation to support transition from ODM combine to minimum transition to MPC combine state seamlessly at the capability boundary when MPO plane is resizing. This will require dc update high level refactor in order to remove the design limitation. The decision is to block such use case for existing products by limiting ODM power optimization support for only those surfaces within guaranteed viewport size. This will prevent us from transitioning to MPC combine state when ODM power optimization is enabled. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Stylon Wang <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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