diff options
| author | Duncan Ma <[email protected]> | 2023-08-01 17:59:05 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2023-09-20 16:24:07 -0400 |
| commit | f1eb045639a38ae9ee80c466f81f2e18204f6d25 (patch) | |
| tree | 1573ab464b3f1767f269e469e197461e3dbeac6c | |
| parent | 1101185bc50f5e45b8b89300914d9aa35a0c8cbe (diff) | |
drm/amd/display: Fix dig register undefined
[Why]
Some of the stream encoder registers have register offset address 0. It
is causing no display in some scenarios due to DIG_FE was not setup
correctly and was not enabled.
[How]
Fix stream encoder register define list.
Tested-by: Daniel Wheeler <[email protected]>
Reviewed-by: Charlene Liu <[email protected]>
Acked-by: Qingqing Zhuo <[email protected]>
Signed-off-by: Duncan Ma <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c index 957f39e1381b..aa0c27e76e4e 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c @@ -308,7 +308,7 @@ static const struct dcn31_apg_mask apg_mask = { }; #define stream_enc_regs_init(id)\ - SE_DCN32_REG_LIST_RI(id) + SE_DCN35_REG_LIST_RI(id) static struct dcn10_stream_enc_registers stream_enc_regs[5]; |