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2021-05-19drm/i915/adl_p: Program DP/HDMI link rate to DDI_BUF_CTLImre Deak2-3/+34
On ADL_P besides programming the PLL accordingly the DP/HDMI link rate should be also programmed to the DDI_BUF_CTL register, do that. Cc: José Roberto de Souza <[email protected]> Signed-off-by: Imre Deak <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: Add PLL SupportAnusha Srivatsa2-17/+60
The clocks in ALD_P is similar to that of TGL. The combo PLLs use the same DPLL0, DPLL1 and TBT_PLL. This patch adds the helper function intel_mg_pll_enable_reg() which is similar to intel_combo_pll_enable_reg() for being lookup place for PLL_ENABLE register in combo phy cases. Bspec: 55409,55316 Cc: Matt Roper <[email protected]> Cc: Clinton Taylor <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: José Roberto de Souza <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: Define and use ADL-P specific DP translation tablesMika Kahola3-1/+63
Define and use DP voltage swing and pre-emphasis translation tables for ADL-P. v2: - Update according to recent bspec updates; there are now separate tables for RBR/HBR and HBR2/HBR3. (Anusha) BSpec: 54956 Cc: Imre Deak <[email protected]> Signed-off-by: Mika Kahola <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Clint Taylor <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/display: Add PSR interrupt error check functionGwan-gyeong Mun1-18/+29
In order to reuse code of PSR interrupt error check on other PSR functions, it adds psr_interrupt_error_check() function. Cc: José Roberto de Souza <[email protected]> Signed-off-by: Gwan-gyeong Mun <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: José Roberto de Souza <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/display: Replace dc3co_enabled with dc3co_exitline on intel_psr structGwan-gyeong Mun2-6/+6
It replaces dc3co_enabled with dc3co_exitline on intel_psr struct. And it saves dc3co_exitline, not dc3co_enabled, so we can use dc3co_exitline without intel_crtc_state on other psr internal function like as intel_psr_enable_source(). Cc: Ville Syrjälä <[email protected]> Cc: José Roberto de Souza <[email protected]> Cc: Anshuman Gupta <[email protected]> Signed-off-by: Gwan-gyeong Mun <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Anshuman Gupta <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: Tx escape clock with DSIMika Kahola2-2/+25
Today when the DSI controller is paired with the Combo-PHY it uses the high-speed (HS) Word clock for its low power (LP) transmit PPI communication to the DPHY. The interface signaling only changes state at an Escape clock frequency (i.e. its effectively running on a virtual Tx Escape clock that is controlled by counters w/in the controller), but all the interface flops are running off the HS clock. This has the following drawbacks: * It is a deviation from the PPI spec which assumes signaling is running on a physical Escape clock * The PV timings are over constrained (HS timed to 312.5MHz vs. an Escape clock of 20MHz max) This feature is proposing to change the LP Tx communication between the controller and the DPHY from a virtual Tx Escape clock to a physical clock. To do this we need to program two "M" divisors. One for the usual DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV register and one for MIPIO_DWORD8. For DSI_ESC_CLK_DIV and DPHY_ESC_CLK_DIV registers the "M" is calculated as following Nt = ceil(f_link/160) (theoretical word clock) Nact = max[3, Nt + (Nt + 1)%2] (actual word clock) M = Nact * 8 For MIPIO_DWORD8 register, the divisor "M" is calculated as following M = (Nact - 1)/2 BSpec: 55171 Cc: Vandita Kulkarni <[email protected]> Signed-off-by: Mika Kahola <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Vandita Kulkarni <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: MBUS programmingVandita Kulkarni6-9/+120
Update MBUS_CTL register if the 2 mbus can be joined as per the current DDB allocation and active pipes, also update hashing mode and pipe select bits as per the sequence mentioned in the bspec. Cc: Stanislav Lisovskiy <[email protected]> Cc: José Roberto de Souza <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915: Introduce MBUS relative dbuf offsetsVille Syrjälä1-6/+34
The dbuf slices are going to be split across several MBUS units. The actual dbuf programming will use offsets relative to the MBUS unit. To accommodate that we shall store the MBUS relative offsets into the dbuf_state->ddb[] and crtc_state->plane_ddb*[]. For crtc_state->wm.skl.ddb however we want to stick to global offsets as we use this to sanity check that the ddb allocations don't overlap between pipes. Cc: Clint Taylor <[email protected]> Signed-off-by: Ville Syrjälä <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: Add ddb allocation supportVandita Kulkarni2-5/+138
On adlp the two mbuses have two display pipes and two DBUFS, Pipe A and D on Mbus1 and Pipe B and C on Mbus2. The Mbus can be joined and all the DBUFS can be used on Pipe A or B. Bspec: 49255 Cc: Anusha Srivatsa <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: Don't config MBUS and DBUF during display initializationJosé Roberto de Souza1-0/+6
Alderlake-P don't have programing sequences for MBUS or DBUF during display initializaiton, instead it requires programing to those registers during modeset because it to depend on the pipes left enabled. Bspec: 49213 Cc: Matt Roper <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: Implement TC sequencesJosé Roberto de Souza3-11/+137
ADL-P have basically the same TC connection and disconnection sequences as ICL and TGL, the major difference is the new registers. So here adding functions without the icl prefix in the name and making the new functions call the platform specific function to access the correct register. v2: - Retain DDI TC PHY ownership flag during modesetting. BSpec: 55480 Cc: Imre Deak <[email protected]> Signed-off-by: José Roberto de Souza <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: Setup ports/physAnusha Srivatsa1-2/+11
The SoC has 6 DDI ports(DDI A,DDI B and DDI TC1-4. The first two are connected to combo phys while the rest are connected to TC phys. Cc: Matt Roper <[email protected]> Cc: Clinton Taylor <[email protected]> Cc: Lucas De Marchi <[email protected]> Cc: Swathi Dhanavanthri <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Imre Deak <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/adl_p: Add dedicated SAGV watermarksMatt Roper4-21/+126
XE_LPD reduces the number of regular watermark latency levels from 8 to 6 on non-dgfx platforms. However the hardware also adds a special purpose SAGV wateramrk (and an accompanying transition watermark) that will be used by the hardware in place of the level 0 values during SAGV transitions. Bspec: 49325, 49326, 50419 Cc: Matt Atwood <[email protected]> Signed-off-by: Matt Roper <[email protected]> Signed-off-by: Clinton Taylor <[email protected]> Reviewed-by: Stanislav Lisovskiy <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/xelpd: Add rc_qp_table for rcparams calculationVandita Kulkarni4-1/+333
Add the qp table for 444 formats, for 8bpc, 10bpc and 12bpc, as given by the VESA C model for DSC 1.1 v2: - Add include guard to header (Jani) - Move the big tables to a .c file (Chris, Jani, Lucas) v3: - Make tables 'static const' and add lookup functions to index into them. (Jani) v3.1: - Include missing .h file. Cc: Manasi Navare <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/xelpd: Calculate VDSC RC parametersVandita Kulkarni1-10/+87
Add methods to calculate rc parameters for all bpps, against the fixed arrays that we already have for 8,10,12 valid o/p bpps, to cover RGB 444 formats. Our hw doesn't support YUV compression yet. The calculations used here are from VESA C model for DSC 1.1 v2: - Checkpatch fixes Cc: Manasi Navare <[email protected]> Cc: Juha-Pekka Heikkil <[email protected]> Signed-off-by: Vandita Kulkarni <[email protected]> Signed-off-by: Mohammed Khajapasha <[email protected]> Signed-off-by: Matt Roper <[email protected]> Reviewed-by: Manasi Navare <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-20Merge tag 'drm-misc-next-2021-05-17' of ↵Dave Airlie17-32/+108
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.14: UAPI Changes: Cross-subsystem Changes: Core Changes: * aperture: Fix unlocking on errors * legacy: Fix some doc comments Driver Changes: * drm/amdgpu: Free resource on fence usage query; Fix fence calculation; * drm/bridge: Lt9611: Add missing MODULE_DEVICE_TABLE * drm/i915: Print formats with %p4cc * drm/ingenic: IPU planes are now always of type OVERLAY * drm/nouveau: Remove left-over reference to struct drm_device.pdev * drm/panfrost: Disable devfreq if num_supplies > 1; Add Mediatek MT8183 + DT bindings; Cleanups * drm/simpledrm: Print resources with %pr; Fix use-after-free errors; Fix NULL deref; Fix MAINTAINERS entry * drm/vmwgfx: Fix memory allocation and leak in FIFO allocation; Fix return value in PCI resource setup Signed-off-by: Dave Airlie <[email protected]> From: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/amdgpu: stop touching sched.ready in the backendChristian König4-16/+1
This unfortunately comes up in regular intervals and breaks GPU reset for the engine in question. The sched.ready flag controls if an engine can't get working during hw_init, but should never be set to false during hw_fini. v2: squash in unused variable fix (Alex) Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: fix a potential deadlock in gpu resetLang Yu1-1/+0
When amdgpu_ib_ring_tests failed, the reset logic called amdgpu_device_ip_suspend twice, then deadlock occurred. Deadlock log: [ 805.655192] amdgpu 0000:04:00.0: amdgpu: ib ring test failed (-110). [ 806.290952] [drm] free PSP TMR buffer [ 806.319406] ============================================ [ 806.320315] WARNING: possible recursive locking detected [ 806.321225] 5.11.0-custom #1 Tainted: G W OEL [ 806.322135] -------------------------------------------- [ 806.323043] cat/2593 is trying to acquire lock: [ 806.323825] ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.325668] but task is already holding lock: [ 806.326664] ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.328430] other info that might help us debug this: [ 806.329539] Possible unsafe locking scenario: [ 806.330549] CPU0 [ 806.330983] ---- [ 806.331416] lock(&adev->dm.dc_lock); [ 806.332086] lock(&adev->dm.dc_lock); [ 806.332738] *** DEADLOCK *** [ 806.333747] May be due to missing lock nesting notation [ 806.334899] 3 locks held by cat/2593: [ 806.335537] #0: ffff888100d3f1b8 (&attr->mutex){+.+.}-{3:3}, at: simple_attr_read+0x4e/0x110 [ 806.337009] #1: ffff888136b1fd78 (&adev->reset_sem){++++}-{3:3}, at: amdgpu_device_lock_adev+0x42/0x94 [amdgpu] [ 806.339018] #2: ffff888136b1cdc8 (&adev->dm.dc_lock){+.+.}-{3:3}, at: dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.340869] stack backtrace: [ 806.341621] CPU: 6 PID: 2593 Comm: cat Tainted: G W OEL 5.11.0-custom #1 [ 806.342921] Hardware name: AMD Celadon-CZN/Celadon-CZN, BIOS WLD0C23N_Weekly_20_12_2 12/23/2020 [ 806.344413] Call Trace: [ 806.344849] dump_stack+0x93/0xbd [ 806.345435] __lock_acquire.cold+0x18a/0x2cf [ 806.346179] lock_acquire+0xca/0x390 [ 806.346807] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.347813] __mutex_lock+0x9b/0x930 [ 806.348454] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.349434] ? amdgpu_device_indirect_rreg+0x58/0x70 [amdgpu] [ 806.350581] ? _raw_spin_unlock_irqrestore+0x47/0x50 [ 806.351437] ? dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.352437] ? rcu_read_lock_sched_held+0x4f/0x80 [ 806.353252] ? rcu_read_lock_sched_held+0x4f/0x80 [ 806.354064] mutex_lock_nested+0x1b/0x20 [ 806.354747] ? mutex_lock_nested+0x1b/0x20 [ 806.355457] dm_suspend+0xb8/0x1d0 [amdgpu] [ 806.356427] ? soc15_common_set_clockgating_state+0x17d/0x19 [amdgpu] [ 806.357736] amdgpu_device_ip_suspend_phase1+0x78/0xd0 [amdgpu] [ 806.360394] amdgpu_device_ip_suspend+0x21/0x70 [amdgpu] [ 806.362926] amdgpu_device_pre_asic_reset+0xb3/0x270 [amdgpu] [ 806.365560] amdgpu_device_gpu_recover.cold+0x679/0x8eb [amdgpu] Signed-off-by: Lang Yu <[email protected]> Acked-by: Christian KÃnig <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: modify system reference clock source for navi+ (V2)Aaron Liu1-0/+15
Starting from Navi+, the rlc reference clock is used for system clock from vbios gfx_info table. It is incorrect to use core_refclk_10khz of vbios smu_info table as system clock. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: update sdma golden setting for Navi12Guchun Chen1-0/+4
Current golden setting is out of date. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: update gc golden setting for Navi12Guchun Chen1-2/+4
Current golden setting is out of date. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Fix a use-after-freexinhui pan1-0/+1
looks like we forget to set ttm->sg to NULL. Hit panic below [ 1235.844104] general protection fault, probably for non-canonical address 0x6b6b6b6b6b6b7b4b: 0000 [#1] SMP DEBUG_PAGEALLOC NOPTI [ 1235.989074] Call Trace: [ 1235.991751] sg_free_table+0x17/0x20 [ 1235.995667] amdgpu_ttm_backend_unbind.cold+0x4d/0xf7 [amdgpu] [ 1236.002288] amdgpu_ttm_backend_destroy+0x29/0x130 [amdgpu] [ 1236.008464] ttm_tt_destroy+0x1e/0x30 [ttm] [ 1236.013066] ttm_bo_cleanup_memtype_use+0x51/0xa0 [ttm] [ 1236.018783] ttm_bo_release+0x262/0xa50 [ttm] [ 1236.023547] ttm_bo_put+0x82/0xd0 [ttm] [ 1236.027766] amdgpu_bo_unref+0x26/0x50 [amdgpu] [ 1236.032809] amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu+0x7aa/0xd90 [amdgpu] [ 1236.040400] kfd_ioctl_alloc_memory_of_gpu+0xe2/0x330 [amdgpu] [ 1236.046912] kfd_ioctl+0x463/0x690 [amdgpu] Signed-off-by: xinhui pan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu/display: restore the backlight on modeset (v2)Alex Deucher1-0/+6
To stay consistent with the user's setting. v2: rebase on multi-eDP support Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1337 Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu/display: add helper functions to get/set backlight (v2)Alex Deucher2-11/+38
And cache the value. These can be used by the backlight callbacks and modesetting functions. v2: rebase on latest backlight changes. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1337 Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Query correct register for DF hashing on AldebaranMukul Joshi2-4/+8
For Aldebaran, driver needs to query DramMegaBaseAddress to check if DF hashing is enabled. Signed-off-by: Mukul Joshi <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add video_codecs query support for aldebaranJames Zhu1-0/+1
Add video_codecs query support for aldebaran. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: fix a resource leakage issueDennis Li1-0/+2
The function kfd_lookup_process_by_pasid will increase the reference count of kfd_process object, its caller should call kfd_unref_process to decrease the reference count. Otherwise resource leakage will happen. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Move dmabuf attach/detach to backend_(un)bindFelix Kuehling2-29/+25
The dmabuf attachment should be updated by moving the SG BO to DOMAIN_CPU and back to DOMAIN_GTT. This does not necessarily invoke the populate/unpopulate callbacks. Do this in backend_bind/unbind instead. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Oak Zeng <[email protected]> Acked-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Add DMA mapping of GTT BOsFelix Kuehling2-1/+77
Use DMABufs with dynamic attachment to DMA-map GTT BOs on other GPUs. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Oak Zeng <[email protected]> Acked-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Move kfd_mem_attach outside reservationFelix Kuehling1-31/+44
This is needed to avoid deadlocks with DMA buf import in the next patch. Also move PT/PD validation out of kfd_mem_attach, that way the caller can bo this unconditionally. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Oak Zeng <[email protected]> Acked-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: DMA map/unmap when updating GPU mappingsFelix Kuehling1-27/+29
DMA map kfd_mem_attachments in update_gpuvm_pte. This function is called with the BO and page tables reserved, so we can safely update the DMA mapping. DMA unmap when a BO is unmapped from a GPU and before updating mappings in restore workers. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Oak Zeng <[email protected]> Acked-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Add multi-GPU DMA mapping helpersFelix Kuehling2-9/+148
Add BO-type specific helpers functions to DMA-map and unmap kfd_mem_attachments. Implement this functionality for userptrs by creating one SG BO per GPU and filling it with a DMA mapping of the pages from the original mem->bo. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Oak Zeng <[email protected]> Acked-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Simplify AQL queue mappingFelix Kuehling1-55/+48
Do AQL queue double-mapping with a single attach call. That will make it easier to create per-GPU BOs later, to be shared between the two BO VA mappings on the same GPU. Freeing the attachments is not necessary if map_to_gpu fails. These will be cleaned up when the kdg_mem object is destroyed in amdgpu_amdkfd_gpuvm_free_memory_of_gpu. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Oak Zeng <[email protected]> Acked-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Keep a bo-reference per-attachmentFelix Kuehling1-5/+17
For now they all reference the same BO. For correct DMA mappings they will refer to different BOs per-GPU. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Oak Zeng <[email protected]> Acked-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Rename kfd_bo_va_list to kfd_mem_attachmentFelix Kuehling2-113/+104
This name is more fitting, especially for the changes coming next to support multi-GPU systems with proper DMA mappings. Cleaned up the code and renamed some related functions and variables to improve readability. Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Oak Zeng <[email protected]> Acked-by: Ramesh Errabolu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: fix refcount leakJingwen Chen1-0/+3
[Why] the gem object rfb->base.obj[0] is get according to num_planes in amdgpufb_create, but is not put according to num_planes [How] put rfb->base.obj[0] in amdgpu_fbdev_destroy according to num_planes Signed-off-by: Jingwen Chen <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: psp program IH_RB_CTRL on sienna_cichlidYuBiao Wang2-5/+27
[Why] IH_RB_CNTL is blocked by PSP so we need to ask psp to help config it. [How] Move psp ip block before ih, and use psp to program IH_RB_CNTL under sriov. Reviewed-by: Chen, Horace <[email protected]> Signed-off-by: YuBiao Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Fix typo of format termination newlineJoe Perches3-3/+3
/n should be \n Signed-off-by: Joe Perches <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: enable idle optimizations for beige gobyAurabindo Pillai1-0/+1
[Why&How] MALL requires idle optimizations to be enabled. This enables MALL feature on dcn303 Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Enable HDCP for Beige GobyAurabindo Pillai1-0/+4
[Why&How] Add beige_goby_ta.bin to module firmware table and call psp init for TA Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Update DCN303 SR Exit LatencyJoshua Aberback1-1/+1
[Why] This update was made for DCN30, but it is needed for DCN303 as well Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add callback for update_soc_for_wm_a for dcn303Aurabindo Pillai1-0/+1
[Why&How] Absense of this callback causes null pointer dereference. Add the corresponding callback in dcn303 resources. Fixes: 443dfba0248387 ("drm/amd/display: fix dcn3+ bw validation soc param update sequence") Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: Enable DCN IP init for Beige GobyAurabindo Pillai2-0/+5
[Why&How] Adds DCN IP block initialization for Beige Goby Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add DM support for Beige GobyAurabindo Pillai1-0/+14
[Why&How] Adds the firmware definition and missing cases statement hooks for Beige Goby support in AMDGPU DM. Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Edit license info for beige goby DC filesAurabindo Pillai16-263/+42
[How] * Add MIT license to all new files as SPDX tag. * Fix copyright year Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Initial DC support for Beige GobyAurabindo Pillai27-1/+2651
[Why&How] Add Beige Goby (DCN303) resource, irq service, & dmub loader. v2: fix nbio include (Alex) Signed-off-by: Chris Park <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add register definitions for Beige GobyAurabindo Pillai4-0/+45172
[Why&How] Adds registers definitions required for Beige Goby initial support. Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Chris Park <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: fix GCR_GENERAL_CNTL offset for beige_gobyJiansong Chen1-1/+1
beige_goby has similar gc_10_3 ip with sienna_cichlid, so follow its registers offset setting. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Jack Gui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: Enable gfxoff for beige_gobyChengming Gui2-0/+2
Enable gfxoff in driver side based on SMC#73.3 v2: fix typo 'Eanble' --> 'Enable' Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Use the PPTable from VBIOS for beige_gobyChengming Gui1-2/+1
Switch from softPPTable to VBIOS PPTable. v2: drop extra parens (Alex) Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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