diff options
| author | Ville Syrjälä <[email protected]> | 2021-06-08 11:54:15 +0300 |
|---|---|---|
| committer | José Roberto de Souza <[email protected]> | 2021-06-08 10:22:55 -0700 |
| commit | 17c1a4b7ac6ffcebcc97442b9af4a34a95d4a1f8 (patch) | |
| tree | d37318ab07aa3b22713b41ede079ed9578a69cfa | |
| parent | 234b40282efba8c6a8824dee2c580f3c3964be34 (diff) | |
drm/i915: Disable PSR around cdclk changes
AUX logic is often clocked from cdclk. Disable PSR to make sure
there are no hw initiated AUX transactions in flight while we
change the cdclk frequency.
Cc: Mika Kahola <[email protected]>
Signed-off-by: Ville Syrjälä <[email protected]>
Signed-off-by: Gwan-gyeong Mun <[email protected]>
Reviewed-by: Mika Kahola <[email protected]>
Signed-off-by: José Roberto de Souza <[email protected]>
Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
| -rw-r--r-- | drivers/gpu/drm/i915/display/intel_cdclk.c | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4656a6edc3be..618a9e1e2b0c 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -28,6 +28,7 @@ #include "intel_cdclk.h" #include "intel_de.h" #include "intel_display_types.h" +#include "intel_psr.h" #include "intel_sideband.h" /** @@ -1908,6 +1909,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, intel_dump_cdclk_config(cdclk_config, "Changing CDCLK to"); + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + intel_psr_pause(intel_dp); + } + /* * Lock aux/gmbus while we change cdclk in case those * functions use cdclk. Not all platforms/ports do, @@ -1930,6 +1937,12 @@ static void intel_set_cdclk(struct drm_i915_private *dev_priv, } mutex_unlock(&dev_priv->gmbus_mutex); + for_each_intel_encoder_with_psr(&dev_priv->drm, encoder) { + struct intel_dp *intel_dp = enc_to_intel_dp(encoder); + + intel_psr_resume(intel_dp); + } + if (drm_WARN(&dev_priv->drm, intel_cdclk_changed(&dev_priv->cdclk.hw, cdclk_config), "cdclk state doesn't match!\n")) { |