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2021-05-19drm/amd/display: Document set RECOUT operationRodrigo Siqueira2-16/+39
During the investigation on how to add visual confirmation on top of the planes used by DCN, it becomes evident that the lack of information in the code makes this work unnecessarily complicated. This commit introduces a set of documentation related to the RECOUT operation in order to make it easy for developers to navigate this set of functions. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add kernel-doc to some hubp functionsRodrigo Siqueira1-0/+13
Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Remove legacy commentsRodrigo Siqueira1-160/+0
To improve the code readability, this commit removes a set of commented and not used functions for a long time. Notice that now we have the amdgpu_dm_dtn_log, which prints all the relevant information that we need. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add documentation for power gate planeRodrigo Siqueira1-2/+36
This commit introduces kernel documentation to some essential functions related to power gate control over planes. It also adds a macro to make one part of the code easy to understand. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add get_current_time interface to dmub_srvWyatt Wood5-2/+13
[Why] Need to get current DMUB time. [How] Add get_current_time interface to dmub_srv. v2: drop whitespace changes (Alex) Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: treat memory as a single-channel for asymmetric memory V3Hugo Hu2-2/+48
Previous patch caused crash and had been reverted. This patch addresses the issue without regression. [Why] 1. Driver use umachannelnumber to calculate watermarks for stutter. In asymmetric memory config, the actual bandwidth is less than dual-channel. The bandwidth should be the same as single-channel. 2. We found single rank dimm need additional delay time for stutter. [How] Get information from each DIMM. Treat memory config as a single-channel for asymmetric memory in bandwidth calculating. Add additional delay time for single rank dimm. Signed-off-by: Hugo Hu <[email protected]> Reviewed-by: Sung Lee <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Reset max GFX clock after disabling determinismLijo Lazar1-3/+8
When determinism mode is disabled on aldebaran, max GFX clock will be reset to default max frequency value. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Fix showing incorrect frequencies on aldebaranLijo Lazar2-25/+55
v1: Use the current and custom pstate frequencies to track the current and user-set min/max values in manual and determinism mode. Previously, only actual_* value was used to track the currrent and user requested value. The value will get reassigned whenever user requests a new value with pp_od_clk_voltage node. Hence it will show incorrect values when user requests an invalid value or tries a partial request without committing the values. Separating out to custom and current variable fixes such issues. v2: Remove redundant if-else check Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Add custom/current freq to pstatesLijo Lazar1-0/+8
Add custom member for user requested custom frequency, level mask or min/max frequencies. Add curr member to keep track of the current active values. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Conditionally reset RAS counters on bootJohn Clements4-14/+14
Only clear RAS error counters if perestent EDC harvesting is not supported Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: disable 3DCGCG on picasso/raven1 to avoid compute hangChangfeng2-5/+7
There is problem with 3DCGCG firmware and it will cause compute test hang on picasso/raven1. It needs to disable 3DCGCG in driver to avoid compute hang. Signed-off-by: Changfeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Refine the error report when flush tlb.Peng Ju Zhou1-1/+1
there are 2 hubs to flush in the gmc, to make it easier to debug when hub flush failed, refine the logs. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Skip the program of GRBM_CAM* in SRIOVPeng Ju Zhou1-0/+3
KMD should not the program these registers, so skip them in the SRIOV environment. Signed-off-by: Peng Ju Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Fix GPU TLB update error when PAGE_SIZE > AMDGPU_PAGE_SIZEYi Li1-1/+1
When PAGE_SIZE is larger than AMDGPU_PAGE_SIZE, the number of GPU TLB entries which need to update in amdgpu_map_buffer() should be multiplied by AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_PAGE_SIZE). Reviewed-by: Christian König <[email protected]> Signed-off-by: Yi Li <[email protected]> Signed-off-by: Huacai Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: heavy-weight flush TLB after unmapPhilip Yang4-6/+13
Need do a heavy-weight TLB flush to make sure we have no more dirty data in the cache for the unmapped pages. Define enum TLB_FLUSH_TYPE, add flush_type parameter to amdgpu_amdkfd_flush_gpu_tlb_pasid. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19Revert "drm/amdkfd: flush TLB after updating GPU page table"Philip Yang1-3/+0
This reverts commit 1704ac8e439e3dcf97431e268bd64fde1874d807. After "drm/amdgpu: flush TLB if valid PDE turns into PTE" is checked in, this workaround is not needed. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Fill adev->unique_id with data from PF2VF msgJiawei Gu2-1/+4
Initialize unique_id from PF2VF under virtualization. V2: skip smu_get_unique_id() under virtualization Signed-off-by: Jiawei Gu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: flush TLB if valid PDE turns into PTEPhilip Yang3-7/+27
Mapping huge page, 2MB aligned address with 2MB size, uses PDE0 as PTE. If previously valid PDE0, PDE0.V=1 and PDE0.P=0 turns into PTE, this requires TLB flush, otherwise page table walker will not read updated PDE0. Change page table update mapping to return table_freed flag to indicate the previously valid PDE may have turned into a PTE if page table is freed. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/radeon: use the dummy page for GART if neededChristian König1-1/+2
Imported BOs don't have a pagelist any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Fixes: 0575ff3d33cd ("drm/radeon: stop using pages with drm_prime_sg_to_page_addr_arrays v2")
2021-05-19drm/amdgpu: move struct amdgpu_vram_reservation into vram mgrChristian König2-5/+5
Not used outside of that file. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: check contiguous flags instead of mm_nodeChristian König1-7/+4
Drop the last user of drm_mm_node. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: set the contiguous flag if possibleChristian König1-2/+3
This avoids reallocating scanout BOs on first pin in a lot of cases. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: use cursor functions in amdgpu_bo_in_cpu_visible_vramChristian König1-6/+9
One of the last remaining uses of drm_mm_node. Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: re-apply "use the new cursor in the VM code" v2Christian König3-40/+20
Now that we found the underlying problem we can re-apply this patch. This reverts commit 6b44b667e24cf89603ebdaa31b939c034d425162. v2: rebase on KFD changes Signed-off-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Tested-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: query boot config cap before issue psp cmdHawking Zhang1-4/+6
Only send boot_config cmd to ASICs that support dynamic boot config. Otherwise, the boot_config cmd will fail. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add helper function to query dynamic boot config capHawking Zhang3-0/+18
Check firmware flags to determine whether dynmaic boot config is supported or not. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: switch to cached fw flags for mem training capHawking Zhang3-62/+11
Check cached firmware_flags to determin whether two stage mem training is supported or not. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: switch to cached fw flags for sram ecc capHawking Zhang1-21/+7
Check cached firmware_flags to determine whether sram ecc is supported or not. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: switch to cached fw flags for gpu virt capHawking Zhang3-16/+13
Check cached firmware_flags to determine if gpu virtualization is supported in vbios Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add atomfirmware helper function to query fw capHawking Zhang4-12/+44
Fimware capability was changed from 16 bits to 32 bits for atomfirmware. add helper funciton to query firmware capability and cache the value at early stage. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Complete multimedia bandwidth interfaceBokun Zhang4-7/+225
- Update SRIOV PF2VF header with latest revision - Extend existing function in amdgpu_virt.c to read MM bandwidth config from PF2VF message - Add SRIOV Sienna Cichlid codec array and update the bandwidth with PF2VF message v2: squash in removal of unused variable (Alex) Signed-off-by: Bokun Zhang <[email protected]> Reviewed-by: Monk liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Albebaran: MTYPE_NC for coarse-grain remote memoryFelix Kuehling2-2/+4
MTYPE UC was used for a specific use case that ended up not being implemented. Use NC for better performance for coarse-grained memory where cache coherence during shader execution is not required. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Arcturus: MTYPE_NC for coarse-grain remote memoryFelix Kuehling2-2/+4
MTYPE UC was used for a specific use case that ended up not being implemented. Use NC for better performance for coarse-grained memory where cache coherence during shader execution is not required. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oak Zeng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Add compile flag for securedisplayJinzhou Su1-0/+4
Add compile flag CONFIG_DEBUG_FS to clear the warning: unused variable 'amdgpu_securedisplay_debugfs_ops' Signed-off-by: Jinzhou Su <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Huang Rui <[email protected]> Reported-by: kernel test robot <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: refine the poison data consumption handlingDennis Li3-1/+42
The user applications maybe register the KFD_EVENT_TYPE_HW_EXCEPTION and KFD_EVENT_TYPE_MEMORY events, driver could notify them when poison data consumed. Beside that, some applications maybe register SIGBUS signal hander. These applications will handle poison data by themselves, exit or re-create context to re-dispatch works. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/radeon/dpm: Disable sclk switching on Oland when two 4K 60Hz monitors ↵Kai-Heng Feng3-0/+12
are connected Screen flickers rapidly when two 4K 60Hz monitors are in use. This issue doesn't happen when one monitor is 4K 60Hz (pixelclock 594MHz) and another one is 4K 30Hz (pixelclock 297MHz). The issue is gone after setting "power_dpm_force_performance_level" to "high". Following the indication, we found that the issue occurs when sclk is too low. So resolve the issue by disabling sclk switching when there are two monitors requires high pixelclock (> 297MHz). v2: - Only apply the fix to Oland. Signed-off-by: Kai-Heng Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdkfd: new range accessible by all GPUsPhilip Yang1-4/+8
If xnack is on, new range is created to recover retry vm fault or created by SVM API calls, set all GPUs have access to the range. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: Update aldebaran pmfw interfaceLijo Lazar2-3/+6
Update aldebaran driver-PMFW interface to version 0x07 Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: Cancel the hrtimer in sw_finiRoy Sun1-7/+5
Move the process of cancelling hrtimer to sw_fini Signed-off-by: Roy Sun <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/pm: enable ASPM by defaultKenneth Feng4-4/+4
Since ASPM function has been stable, we don't need to add the modprobe parameter and we can enable ASPM by default. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: update the method for harvest IP for specific SKULikun Gao1-14/+16
Update the method of disabling VCN IP for specific SKU for navi1x ASIC, it will judge whether should add the related IP at the function of amdgpu_device_ip_block_add(). Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add judgement when add ip blocks (v2)Likun GAO6-2/+57
Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add synchronization among waves in the same threadgroupDennis Li1-134/+142
It is possible that the previous waves have exited before others are created, so the other waves maybe reuse pyhsical resouces left by previous ones. Therefore add barrier instruction to synchronize waves within the same threadgroup. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu/display: fix dal_allocation documentationAlex Deucher1-0/+4
Add missing structure elements. Fixes: 0dd79532340568 ("drm/amdgpu/display: Implement functions to let DC allocate GPU memory") Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/i915/dmc: s/intel_csr.c/intel_dmc.c and s/intel_csr.h/intel_dmc.hAnusha Srivatsa9-17/+17
Finally, rename the header and source file from csr to dmc. v2: Add file rename in Documentation. - Place headers in orders. (Jani) Cc: Jani Nikula <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/dmc: Rename functions names having "csr"Anusha Srivatsa5-54/+54
No functional change. Cc: Jani Nikula <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/dmc: Rename macro names containing csrAnusha Srivatsa6-118/+117
Rename all occurences of CSR_* with DMC_* Cc: Jani Nikula <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/dmc: s/HAS_CSR/HAS_DMCAnusha Srivatsa7-13/+13
No functional change. Cc: Jani Nikula <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/i915/dmc: s/intel_csr/intel_dmcAnusha Srivatsa6-125/+125
No functional change. v2: Chchpatch fixes. Cc: Jani Nikula <[email protected]> Signed-off-by: Anusha Srivatsa <[email protected]> Reviewed-by: Lucas De Marchi <[email protected]> Signed-off-by: Lucas De Marchi <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-20Merge tag 'imx-drm-next-2021-05-12' of ↵Dave Airlie8-24/+167
git://git.pengutronix.de/git/pza/linux into drm-next drm/imx: fixes, dma-fence annotation, and color encoding/range plane properties - Annotate dma-fence critical section in atomic_commit_tail - Fix PRG modifiers after drmm resource conversion to regain tiled scanout capability - Add 8 pixel alignment fix to support 1366x768 resolution - Stop advertising YUV formats on planes that don't support them - Add COLOR_ENCODING and COLOR_RANGE plane properties on planes that support them - Remove unnecessarily exported symbols Signed-off-by: Dave Airlie <[email protected]> From: Philipp Zabel <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
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