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2020-10-05drm/amd/display: Hardcode 45W Bounding Box for DCN2.1 DiagsSung Lee1-83/+36
[WHY] Currently construction of clock limits gets skipped for diags. This logic would be useful to get tested in diags. [HOW] Copy existing states to clk_table such that update_bw_bounding_box logic gets used to fill the table. Signed-off-by: Sung Lee <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: FreeSync not active near lower bound of non-LFC monitor rangeAric Cyr1-4/+6
[Why] On narrow range monitors without LFC, a margin prevents good utilization of the available range. [How] Decrease the margin for exiting fixed mode and fix the frame counter to reset if a non-consecutive render is found. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Fix OPTC_DATA_FORMAT programmingDmytro Laktyushkin3-16/+11
This should be programmed with timing rather than with odm. Signed-off-by: Dmytro Laktyushkin <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Add i2c speed arbitration for dc_i2c and hdcp_i2cCharlene Liu11-3/+20
[why] HDCP 1.4 failed on SL8800 SW w/a test driver use. [how] Slow down the HW i2c speed when used by HW i2c. This request: each acquired_i2c_engine setup the i2c speed needed and sets the I2c engine for HDCP use at release_engine. This covers SW using HW i2c engine and HDCP using HW i2c engine. for dmcu using HW i2c engine, needs add similar logic in dmcu fw. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Block ABM in case of eDP ODMYongqiang Sun6-0/+24
[Why] enable ODM on eDP panel with ABM will result in color difference on the panel due to only one ABM module to set one pipe. [How] Block ABM in case of ODM enabled on eDP. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Copy WM values from set A to other sets in hw_initJoshua Aberback3-0/+47
[Why] When we transfer the WM range table to SMU, they can perform a watermark switch right away. This can be a problem if we're in not in accelerated mode during hw_init as SMU may initiate a dummy p-state change before the rest of the watermarks are programmed. Watermark set A is defined to be sufficient for all cases, so we can copy the values from set A to all other sets, avoiding any issues from SMU doing WM switches. [How] - new hubbub func init_watermarks - copy register values from set A to all other sets - call init_watermarks before calling notify_wm_ranges Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Force enable pstate on driver unloadJoshua Aberback7-6/+29
[Why] During driver unload, it is expected that p-state switching is supported. If it's not supported, PMFW will hang due to a forced p-state switch. Even if the current timing does not support p-state normally, we still want to force allow because the worst that can happen is underflow. This will match Navi10 behaviour. [How] - new hubbub func to control the force pstate register - force allow when releasing display ownership - registers are inaccessible after due to m_cgs.hwNotAvailable - explicitly disable force signal during hw_init - if driver is disabled and re-enabled, register not cleared otherwise Also, remove DCN3 part of dcn10_init_hw, we will not be going back to it. Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Fixed comments (uniform style)Felipe1-22/+23
[WHY] This change was implemented because the comment style was not uniform across the file. In some lines comments were initiated with // and in others they were in between /* ... */. Additionally, the style for multi-line comments was also not uniform and some comment lines were missing the space between the opening /* and the first word of the comment. [HOW] All comments are now in between /*.../*, multi line comments also use /*...*/ and for every comment there is now a space between the opening /* and the first word of the comment. Signed-off-by: Felipe <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Check for flip pending before locking pipesAric Cyr4-83/+88
[Why] When running games or benchmarking with v-sync disabled, disabling a plane (which is v-sync) can cause underflow. This is caused by flips pending before pipe locking being applied after locks are released and pipes could have been re-arranged or disconnected. This could potentially apply a flip on incorrect pipe. Also, previous logic of always locking pipes was unnecessary. [How] Only lock the pipes when there is a pipe being disabled to increase efficiency. Before the pipes are locked, check that any pending flips are cleared to ensure the flips are applied to the correct pipe. Signed-off-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Don't allow pstate if no support in blankAlvin Lee1-1/+1
[Why] We will hang if we report switch in VACTIVE but not in VBLANK and DPG_EN = 1 [How] Block switch in ACTIVE if not supported in BLANK Signed-off-by: Alvin Lee <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: 3.2.105Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add van gogh pci idHuang Rui1-0/+3
Add Van Gogh PCI id support. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Add dcn3.01 support to DMRoman Li1-0/+26
Update dm for vangogh support. Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/display: Add dcn3.01 support to DC (v2)Roman Li48-33/+5232
Update dc for vangogh support. v2: fix compilation without DCN 301 set. Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: enable gfx clock gating and power gating for vangoghHuang Rui1-2/+5
This patch is to enable the gfx cg and pg for vangogh. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add gfx power gating for gfx10Huang Rui1-0/+24
This patch adds power gating handler for gfx10. v2: simplify function Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/mmhub2.3: print client id string for mmhubAlex Deucher1-6/+43
Print the name of the client rather than the number. This makes it easier to debug what block is causing the fault. Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: IP discovery table is not ready yet for VGAlex Deucher1-0/+4
Fallback to legacy path for now. Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: disable gfxoff on vangogh for the moment (v2)Huang Rui1-0/+1
GFXOFF will be enabled once it's verified on real asic. v2: move check into gfx10 module. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: enable psp support for vangoghHuang Rui4-2/+9
This patch is to enable psp support for vangogh Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add TOC firmware support for apu (v3)Huang Rui4-10/+77
APU needs load toc firmware for gfx10 series on psp front door loading. v2: rebase against latest code v3: clarify error message Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add TOC firmware definitionHuang Rui1-0/+2
This patch is to add TOC firmware definition on uapi. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add smu ip block for vangoghHuang Rui1-0/+1
This patch is to add ip block for vangogh. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/powerplay: add vangogh ppt into swSMUHuang Rui2-0/+5
This patch is to add vangogh ppt funcions into swSMU block. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/powerplay: partially enable swsmu for vangoghHuang Rui1-0/+6
This patch is to partially enable swSMU for vangogh for the moment. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v4)Xiaojian Du2-0/+384
This patch is to add smu initialize functions for vangogh. v2: squash in updates v3: drop duplicate table entries v4: rebase fixes Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2)Xiaojian Du2-0/+4
This patch is to add vangogh asic name in smu v11. v2: drop smu firmware name (N/A for VG) Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu v11.5 smc header for vangoghXiaojian Du1-0/+86
This patch is to add smu v11.5 smc header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2)Xiaojian Du1-0/+120
This patch is to add smu v11.5 firmware header for vangogh v2: squash in updates Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/admgpu/powerplay: add smu v11.5 driver interface header for vangoghXiaojian Du1-0/+239
This patch is to add smu v11.5 driver interface header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add new smu messages and feature masks for vangogh (v2)Xiaojian Du1-6/+47
This patch is to add new smu messages and feature masks for vangogh. v2: squash in updates and typo fixes Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add nbio v7.2 for vangogh (v2)Huang Rui4-3/+383
VanGogh uses nbio v7.2, and a couple of offsets are changed since nbio v2.3 for navi series, so add new nbio v7.2 block. v2: squash in fix for sdma and vcn instances Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add pcie port indirect read and write on nvHuang Rui2-0/+34
This patch is to add pcie port indirect read/write callback for nv series. They will be used for new asic. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: enable vcn3.0 for van goghThong Thai2-0/+10
Same as other VCN 3.0 asics. Signed-off-by: Thong Thai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add mmhub v2.3 for vangogh (v4)Huang Rui4-2/+590
There are too many register offset mismatch between mmhub v2.0 and v2.3. E.X: mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3) mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3) mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32: 0x072b(v2.0) 0x0940(v2.3) mmMMVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32: 0x072c(v2.0) 0x0941(v2.3) mmMMVM_INVALIDATE_ENG0_REQ: 0x06e3(v2.0) 0x0a01(v2.3) mmMMVM_INVALIDATE_ENG0_ACK: 0x06f5(v2.0) 0x0a02(v2.3) mmMMVM_CONTEXT0_CNTL: 0x06c0(v2.0) 0x0740(v2.3) mmMMVM_L2_PROTECTION_FAULT_STATUS: 0x068c(v2.0) 0x070c(v2.3) mmMMVM_L2_PROTECTION_FAULT_CNTL: 0x0688(v2.0) 0x0708(v2.3) mmMM_ATC_L2_MISC_CG: 0x064a(v2.0) 0x06cd(v2.3) mmDAGB0_CNTL_MISC2: 0x0071(v2.0) 0x0096(v2.3) ... Continuing using the same file mmhub v2.0 is not good choice, it will introduce a lot of checking with ASIC types. And also easy to introduce the issues that offset not align, this kind of issues are really hard to find. Van Gogh's mmhub vm invalidation is actually caused by the offset mismatch as well. So it would like to create a new file rather than stick to re-use orignal mmhub v2.0 here. v2: add missed translate_further programming. v3: sync with latest code v4: add missing callbacks Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdkfd: add Van Gogh KFD supportHuang Rui6-0/+29
This patch is to add GFX10 based APU Van Gogh KFD support. We will treat Van Gogh as "dgpu" (bypass IOMMU v2). Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: set ip blocks for van goghHuang Rui1-0/+9
Enable ip blocks for van gogh. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add sdma support for van goghHuang Rui1-0/+10
This patch adds the sdma v5.2 support for van gogh. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/gfx10: add updated register offsets for VGHAlex Deucher1-2/+16
Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add gfx golden settings for vangogh (v3)Huang Rui1-1/+35
This patch is to add gfx golden settings for vangogh post si. v2: squash in updates v3: fix SPI register offset Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add gfx support for van gogh (v3)Huang Rui1-1/+28
Add van gogh checks to gfx10 code. v2: squash in fixes v3: fix mode Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: set fw load type for van goghHuang Rui1-0/+2
This patch sets fw load type as direct for van gogh for the moment. Will switch to psp when psp is ready. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add gmc v10 supports for van gogh (v4)Huang Rui1-1/+15
Add gfx memory controller support for van gogh. v2: don't use dynamic invalidate eng allocation for van gogh. v3: squash in other fixes v4: rebase Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: get the correct vram type for van goghHuang Rui2-0/+5
This patch is to get the correct vram type from atombios for van gogh. Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/atomfirmware: Add edp and integrated info v2.1 tablesRoman Li1-1/+61
Required for vangogh. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: update new memory types in atomfirmware headerHuang Rui1-0/+5
Add new nemory types in atomfirmware header. Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add uapi to define van gogh memory typeHuang Rui1-0/+1
This patch adds van gogh memory type as DDR5. Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: use gpu virtual address for interrupt packet write space for vangoghHuang Rui1-2/+5
The interrupts are not stable while uses guest physical address (GPA) for interrupt packet write space even on direct loading case. v2: make condition more readable Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: add van gogh support for ih blockHuang Rui1-0/+1
This patch adds the support for van gogh ih block. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu: skip sdma1 in nv_allowed_read_registers list for van gogh (v2)Huang Rui1-1/+2
Van gogh only has one sdma. v2: use num_instances rather than APU flag Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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