diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json index f75084309041..53d7f76325a3 100644 --- a/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "DTLB load misses", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.ANY", "SampleAfterValue": "200000", @@ -8,6 +9,7 @@ }, { "BriefDescription": "DTLB load miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -15,6 +17,7 @@ }, { "BriefDescription": "DTLB load miss caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -22,6 +25,7 @@ }, { "BriefDescription": "DTLB second level hit", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "SampleAfterValue": "2000000", @@ -29,6 +33,7 @@ }, { "BriefDescription": "DTLB load miss page walks complete", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -36,6 +41,7 @@ }, { "BriefDescription": "DTLB load miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x8", "EventName": "DTLB_LOAD_MISSES.WALK_CYCLES", "SampleAfterValue": "200000", @@ -43,6 +49,7 @@ }, { "BriefDescription": "DTLB misses", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -50,6 +57,7 @@ }, { "BriefDescription": "DTLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -57,6 +65,7 @@ }, { "BriefDescription": "DTLB misses caused by low part of address", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.PDE_MISS", "SampleAfterValue": "200000", @@ -64,6 +73,7 @@ }, { "BriefDescription": "DTLB first level misses but second level hit", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.STLB_HIT", "SampleAfterValue": "200000", @@ -71,6 +81,7 @@ }, { "BriefDescription": "DTLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -78,6 +89,7 @@ }, { "BriefDescription": "DTLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -85,6 +97,7 @@ }, { "BriefDescription": "Extended Page Table walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x4F", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -92,6 +105,7 @@ }, { "BriefDescription": "ITLB flushes", + "Counter": "0,1,2,3", "EventCode": "0xAE", "EventName": "ITLB_FLUSH", "SampleAfterValue": "2000000", @@ -99,6 +113,7 @@ }, { "BriefDescription": "ITLB miss", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.ANY", "SampleAfterValue": "200000", @@ -106,6 +121,7 @@ }, { "BriefDescription": "ITLB miss large page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED", "SampleAfterValue": "200000", @@ -113,6 +129,7 @@ }, { "BriefDescription": "ITLB miss page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "SampleAfterValue": "200000", @@ -120,6 +137,7 @@ }, { "BriefDescription": "ITLB miss page walk cycles", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_CYCLES", "SampleAfterValue": "2000000", @@ -127,6 +145,7 @@ }, { "BriefDescription": "Retired instructions that missed the ITLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC8", "EventName": "ITLB_MISS_RETIRED", "PEBS": "1", @@ -135,6 +154,7 @@ }, { "BriefDescription": "Retired loads that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xCB", "EventName": "MEM_LOAD_RETIRED.DTLB_MISS", "PEBS": "1", @@ -143,6 +163,7 @@ }, { "BriefDescription": "Retired stores that miss the DTLB (Precise Event)", + "Counter": "0,1,2,3", "EventCode": "0xC", "EventName": "MEM_STORE_RETIRED.DTLB_MISS", "PEBS": "1", |