diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/sandybridge/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/sandybridge/other.json | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/sandybridge/other.json b/tools/perf/pmu-events/arch/x86/sandybridge/other.json index 9f96121baef8..42692fa24b6c 100644 --- a/tools/perf/pmu-events/arch/x86/sandybridge/other.json +++ b/tools/perf/pmu-events/arch/x86/sandybridge/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Unhalted core cycles when the thread is in ring 0.", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING0", "SampleAfterValue": "2000003", @@ -8,6 +9,7 @@ }, { "BriefDescription": "Number of intervals between processor halts while thread is in ring 0.", + "Counter": "0,1,2,3", "CounterMask": "1", "EdgeDetect": "1", "EventCode": "0x5C", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3.", + "Counter": "0,1,2,3", "EventCode": "0x5C", "EventName": "CPL_CYCLES.RING123", "SampleAfterValue": "2000003", @@ -24,6 +27,7 @@ }, { "BriefDescription": "Hardware Prefetch requests that miss the L1D cache. This accounts for both L1 streamer and IP-based (IPP) HW prefetchers. A request is being counted each time it access the cache & miss it, including if a block is applicable or if hit the Fill Buffer for .", + "Counter": "0,1,2,3", "EventCode": "0x4E", "EventName": "HW_PRE_REQ.DL1_MISS", "SampleAfterValue": "2000003", @@ -31,6 +35,7 @@ }, { "BriefDescription": "Valid instructions written to IQ per cycle.", + "Counter": "0,1,2,3", "EventCode": "0x17", "EventName": "INSTS_WRITTEN_TO_IQ.INSTS", "SampleAfterValue": "2000003", @@ -38,6 +43,7 @@ }, { "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock.", + "Counter": "0,1,2,3", "EventCode": "0x63", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "SampleAfterValue": "2000003", |