diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/rocketlake/other.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/rocketlake/other.json | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/rocketlake/other.json b/tools/perf/pmu-events/arch/x86/rocketlake/other.json index 4fdc87339555..a96b2a989d3f 100644 --- a/tools/perf/pmu-events/arch/x86/rocketlake/other.json +++ b/tools/perf/pmu-events/arch/x86/rocketlake/other.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the Non-AVX turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL0_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was running with power-delivery for baseline license level 0. This includes non-AVX codes, SSE, AVX 128-bit, and low-current AVX 256-bit codes.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX2 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL1_TURBO_LICENSE", "PublicDescription": "Counts Core cycles where the core was running with power-delivery for license level 1. This includes high current AVX 256-bit instructions as well as low current AVX 512-bit instructions.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Core cycles where the core was running in a manner where Turbo may be clipped to the AVX512 turbo schedule.", + "Counter": "0,1,2,3", "EventCode": "0x28", "EventName": "CORE_POWER.LVL2_TURBO_LICENSE", "PublicDescription": "Core cycles where the core was running with power-delivery for license level 2 (introduced in Skylake Server microarchitecture). This includes high current AVX 512-bit instructions.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -34,6 +38,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -43,6 +48,7 @@ }, { "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -52,6 +58,7 @@ }, { "BriefDescription": "Counts demand data reads that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -61,6 +68,7 @@ }, { "BriefDescription": "Counts demand data reads that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -70,6 +78,7 @@ }, { "BriefDescription": "Counts demand data reads that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -79,6 +88,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -88,6 +98,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -97,6 +108,7 @@ }, { "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -106,6 +118,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -115,6 +128,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -124,6 +138,7 @@ }, { "BriefDescription": "Counts L1 data cache prefetch requests and software prefetches (except PREFETCHW) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L1D_AND_SWPF.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -133,6 +148,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -142,6 +158,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -151,6 +168,7 @@ }, { "BriefDescription": "Counts hardware prefetch data reads (which bring data to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -160,6 +178,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -169,6 +188,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -178,6 +198,7 @@ }, { "BriefDescription": "Counts hardware prefetch RFOs (which bring data to L2) that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -187,6 +208,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -196,6 +218,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -205,6 +228,7 @@ }, { "BriefDescription": "Counts miscellaneous requests, such as I/O and un-cacheable accesses that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.OTHER.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -214,6 +238,7 @@ }, { "BriefDescription": "Counts streaming stores that have any type of response.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.ANY_RESPONSE", "MSRIndex": "0x1a6,0x1a7", @@ -223,6 +248,7 @@ }, { "BriefDescription": "Counts streaming stores that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.DRAM", "MSRIndex": "0x1a6,0x1a7", @@ -232,6 +258,7 @@ }, { "BriefDescription": "Counts streaming stores that DRAM supplied the request.", + "Counter": "0,1,2,3", "EventCode": "0xB7, 0xBB", "EventName": "OCR.STREAMING_WR.LOCAL_DRAM", "MSRIndex": "0x1a6,0x1a7", |