diff options
Diffstat (limited to 'tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json')
| -rw-r--r-- | tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json | 49 |
1 files changed, 49 insertions, 0 deletions
diff --git a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json index 87a4ec1ee7d7..7cf00ae0e993 100644 --- a/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json +++ b/tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json @@ -1,6 +1,7 @@ [ { "BriefDescription": "Load misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in all TLB levels that cause a page walk of any page size.", @@ -9,6 +10,7 @@ }, { "BriefDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.PDE_CACHE_MISS", "PublicDescription": "DTLB demand load misses with low part of linear-to-physical address translation missed.", @@ -17,6 +19,7 @@ }, { "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT", "PublicDescription": "Number of cache load STLB hits. No page walk.", @@ -25,6 +28,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "PublicDescription": "This event counts load operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", @@ -33,6 +37,7 @@ }, { "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "PublicDescription": "This event counts load operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", @@ -41,6 +46,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks in any TLB of any page size due to demand load misses.", @@ -49,6 +55,7 @@ }, { "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "2000003", @@ -56,6 +63,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to demand load misses that caused 2M/4M page walks in any TLB levels.", @@ -64,6 +72,7 @@ }, { "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to demand load misses that caused 4K page walks in any TLB levels.", @@ -72,6 +81,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x08", "EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.", @@ -80,6 +90,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Miss in all TLB levels causes a page walk of any page size (4K/2M/4M/1G).", @@ -88,6 +99,7 @@ }, { "BriefDescription": "DTLB store misses with low part of linear-to-physical address translation missed", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.PDE_CACHE_MISS", "PublicDescription": "DTLB store misses with low part of linear-to-physical address translation missed.", @@ -96,6 +108,7 @@ }, { "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT", "PublicDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.", @@ -104,6 +117,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "PublicDescription": "This event counts store operations from a 2M page that miss the first DTLB level but hit the second and do not cause page walks.", @@ -112,6 +126,7 @@ }, { "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "PublicDescription": "This event counts store operations from a 4K page that miss the first DTLB level but hit the second and do not cause page walks.", @@ -120,6 +135,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause completed page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks due to store miss in any TLB levels of any page size (4K/2M/4M/1G).", @@ -128,6 +144,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause completed page walks. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", @@ -135,6 +152,7 @@ }, { "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 2M/4M page structure.", @@ -143,6 +161,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to store misses in one or more TLB levels of 4K page structure.", @@ -151,6 +170,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x49", "EventName": "DTLB_STORE_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB store misses.", @@ -159,6 +179,7 @@ }, { "BriefDescription": "Cycle count for an Extended Page table walk.", + "Counter": "0,1,2,3", "EventCode": "0x4f", "EventName": "EPT.WALK_CYCLES", "SampleAfterValue": "2000003", @@ -166,6 +187,7 @@ }, { "BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.", + "Counter": "0,1,2,3", "EventCode": "0xae", "EventName": "ITLB.ITLB_FLUSH", "PublicDescription": "Counts the number of ITLB flushes, includes 4k/2M/4M pages.", @@ -174,6 +196,7 @@ }, { "BriefDescription": "Misses at all ITLB levels that cause page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "PublicDescription": "Misses in ITLB that causes a page walk of any page size.", @@ -182,6 +205,7 @@ }, { "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT", "PublicDescription": "ITLB misses that hit STLB. No page walk.", @@ -190,6 +214,7 @@ }, { "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_2M", "PublicDescription": "ITLB misses that hit STLB (2M).", @@ -198,6 +223,7 @@ }, { "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.STLB_HIT_4K", "PublicDescription": "ITLB misses that hit STLB (4K).", @@ -206,6 +232,7 @@ }, { "BriefDescription": "Misses in all ITLB levels that cause completed page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED", "PublicDescription": "Completed page walks in ITLB of any page size.", @@ -214,6 +241,7 @@ }, { "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "SampleAfterValue": "100003", @@ -221,6 +249,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "PublicDescription": "Completed page walks due to misses in ITLB 2M/4M page entries.", @@ -229,6 +258,7 @@ }, { "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "PublicDescription": "Completed page walks due to misses in ITLB 4K page entries.", @@ -237,6 +267,7 @@ }, { "BriefDescription": "Cycles when PMH is busy with page walks", + "Counter": "0,1,2,3", "EventCode": "0x85", "EventName": "ITLB_MISSES.WALK_DURATION", "PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by ITLB misses.", @@ -245,6 +276,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L1", "PublicDescription": "Number of DTLB page walker loads that hit in the L1+FB.", @@ -253,6 +285,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L2", "PublicDescription": "Number of DTLB page walker loads that hit in the L2.", @@ -261,6 +294,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_L3", @@ -270,6 +304,7 @@ }, { "BriefDescription": "Number of DTLB page walker hits in Memory", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", @@ -279,6 +314,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L1", "SampleAfterValue": "2000003", @@ -286,6 +322,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L2", "SampleAfterValue": "2000003", @@ -293,6 +330,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in the L3.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_L3", "SampleAfterValue": "2000003", @@ -300,6 +338,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walks from the DTLB that hit in memory.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_DTLB_MEMORY", "SampleAfterValue": "2000003", @@ -307,6 +346,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L1 and FB.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L1", "SampleAfterValue": "2000003", @@ -314,6 +354,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L2", "SampleAfterValue": "2000003", @@ -321,6 +362,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in the L2.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_L3", "SampleAfterValue": "2000003", @@ -328,6 +370,7 @@ }, { "BriefDescription": "Counts the number of Extended Page Table walks from the ITLB that hit in memory.", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.EPT_ITLB_MEMORY", "SampleAfterValue": "2000003", @@ -335,6 +378,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L1+FB", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L1", "PublicDescription": "Number of ITLB page walker loads that hit in the L1+FB.", @@ -343,6 +387,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L2", + "Counter": "0,1,2,3", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L2", "PublicDescription": "Number of ITLB page walker loads that hit in the L2.", @@ -351,6 +396,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_L3", @@ -360,6 +406,7 @@ }, { "BriefDescription": "Number of ITLB page walker hits in Memory", + "Counter": "0,1,2,3", "Errata": "HSD25", "EventCode": "0xBC", "EventName": "PAGE_WALKER_LOADS.ITLB_MEMORY", @@ -369,6 +416,7 @@ }, { "BriefDescription": "DTLB flush attempts of the thread-specific entries", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.DTLB_THREAD", "PublicDescription": "DTLB flush attempts of the thread-specific entries.", @@ -377,6 +425,7 @@ }, { "BriefDescription": "STLB flush attempts", + "Counter": "0,1,2,3", "EventCode": "0xBD", "EventName": "TLB_FLUSH.STLB_ANY", "PublicDescription": "Count number of STLB flush attempts.", |