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Diffstat (limited to 'sound/soc/loongson/loongson_i2s.h')
-rw-r--r--sound/soc/loongson/loongson_i2s.h24
1 files changed, 12 insertions, 12 deletions
diff --git a/sound/soc/loongson/loongson_i2s.h b/sound/soc/loongson/loongson_i2s.h
index 89492eebf834..c8052a762c1b 100644
--- a/sound/soc/loongson/loongson_i2s.h
+++ b/sound/soc/loongson/loongson_i2s.h
@@ -27,18 +27,18 @@
#define LS_I2S_RX_ORDER 0x110 /* RX DMA Order */
/* Loongson I2S Control Register */
-#define I2S_CTRL_MCLK_READY (1 << 16) /* MCLK ready */
-#define I2S_CTRL_MASTER (1 << 15) /* Master mode */
-#define I2S_CTRL_MSB (1 << 14) /* MSB bit order */
-#define I2S_CTRL_RX_EN (1 << 13) /* RX enable */
-#define I2S_CTRL_TX_EN (1 << 12) /* TX enable */
-#define I2S_CTRL_RX_DMA_EN (1 << 11) /* DMA RX enable */
-#define I2S_CTRL_CLK_READY (1 << 8) /* BCLK ready */
-#define I2S_CTRL_TX_DMA_EN (1 << 7) /* DMA TX enable */
-#define I2S_CTRL_RESET (1 << 4) /* Controller soft reset */
-#define I2S_CTRL_MCLK_EN (1 << 3) /* Enable MCLK */
-#define I2S_CTRL_RX_INT_EN (1 << 1) /* RX interrupt enable */
-#define I2S_CTRL_TX_INT_EN (1 << 0) /* TX interrupt enable */
+#define I2S_CTRL_MCLK_READY BIT(16) /* MCLK ready */
+#define I2S_CTRL_MASTER BIT(15) /* Master mode */
+#define I2S_CTRL_MSB BIT(14) /* MSB bit order */
+#define I2S_CTRL_RX_EN BIT(13) /* RX enable */
+#define I2S_CTRL_TX_EN BIT(12) /* TX enable */
+#define I2S_CTRL_RX_DMA_EN BIT(11) /* DMA RX enable */
+#define I2S_CTRL_CLK_READY BIT(8) /* BCLK ready */
+#define I2S_CTRL_TX_DMA_EN BIT(7) /* DMA TX enable */
+#define I2S_CTRL_RESET BIT(4) /* Controller soft reset */
+#define I2S_CTRL_MCLK_EN BIT(3) /* Enable MCLK */
+#define I2S_CTRL_RX_INT_EN BIT(1) /* RX interrupt enable */
+#define I2S_CTRL_TX_INT_EN BIT(0) /* TX interrupt enable */
#define LS_I2S_DRVNAME "loongson-i2s"