diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h | 483 |
1 files changed, 465 insertions, 18 deletions
diff --git a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h index e85fd3ac52c7..4db4c5ad5169 100644 --- a/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h +++ b/drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h @@ -81,6 +81,16 @@ */ #define NUM_BL_CURVE_SEGS 16 +/** + * Maximum number of segments in ABM ACE curve. + */ +#define ABM_MAX_NUM_OF_ACE_SEGMENTS 64 + +/** + * Maximum number of bins in ABM histogram. + */ +#define ABM_MAX_NUM_OF_HG_BINS 64 + /* Maximum number of SubVP streams */ #define DMUB_MAX_SUBVP_STREAMS 2 @@ -150,10 +160,6 @@ #define dmub_memset(dest, val, bytes) memset((dest), (val), (bytes)) #endif -#if defined(__cplusplus) -extern "C" { -#endif - /** * OS/FW agnostic udelay */ @@ -487,10 +493,6 @@ struct dmub_visual_confirm_color { uint16_t panel_inst; }; -#if defined(__cplusplus) -} -#endif - //============================================================================== //</DMUB_TYPES>================================================================= //============================================================================== @@ -505,6 +507,17 @@ struct dmub_visual_confirm_color { #define DMUB_FW_META_OFFSET 0x24 /** + * union dmub_fw_meta_feature_bits - Static feature bits for pre-initialization + */ +union dmub_fw_meta_feature_bits { + struct { + uint32_t shared_state_link_detection : 1; /**< 1 supports link detection via shared state */ + uint32_t reserved : 31; + } bits; /**< status bits */ + uint32_t all; /**< 32-bit access to status bits */ +}; + +/** * struct dmub_fw_meta_info - metadata associated with fw binary * * NOTE: This should be considered a stable API. Fields should @@ -529,6 +542,7 @@ struct dmub_fw_meta_info { uint32_t shared_state_size; /**< size of the shared state region in bytes */ uint16_t shared_state_features; /**< number of shared state features */ uint16_t reserved2; /**< padding bytes */ + union dmub_fw_meta_feature_bits feature_bits; /**< static feature bits */ }; /** @@ -663,7 +677,7 @@ union dmub_fw_boot_options { uint32_t ips_pg_disable: 1; /* 1 to disable ONO domains power gating*/ uint32_t ips_disable: 3; /* options to disable ips support*/ uint32_t ips_sequential_ono: 1; /**< 1 to enable sequential ONO IPS sequence */ - uint32_t reserved : 9; /**< reserved */ + uint32_t reserved : 8; /**< reserved */ } bits; /**< boot bits */ uint32_t all; /**< 32-bit access to bits */ }; @@ -706,7 +720,8 @@ union dmub_shared_state_ips_fw_signals { uint32_t ips1_commit : 1; /**< 1 if in IPS1 */ uint32_t ips2_commit : 1; /**< 1 if in IPS2 */ uint32_t in_idle : 1; /**< 1 if DMCUB is in idle */ - uint32_t reserved_bits : 29; /**< Reversed */ + uint32_t detection_required : 1; /**< 1 if detection is required */ + uint32_t reserved_bits : 28; /**< Reversed */ } bits; uint32_t all; }; @@ -938,6 +953,37 @@ enum dmub_gpint_command { DMUB_GPINT__REPLAY_RESIDENCY = 14, /** + * DESC: Copy bounding box to the host. + * ARGS: Version of bounding box to copy + * RETURN: Result of copying bounding box + */ + DMUB_GPINT__BB_COPY = 96, + + /** + * DESC: Updates the host addresses bit48~bit63 for bounding box. + * ARGS: The word3 for the 64 bit address + */ + DMUB_GPINT__SET_BB_ADDR_WORD3 = 97, + + /** + * DESC: Updates the host addresses bit32~bit47 for bounding box. + * ARGS: The word2 for the 64 bit address + */ + DMUB_GPINT__SET_BB_ADDR_WORD2 = 98, + + /** + * DESC: Updates the host addresses bit16~bit31 for bounding box. + * ARGS: The word1 for the 64 bit address + */ + DMUB_GPINT__SET_BB_ADDR_WORD1 = 99, + + /** + * DESC: Updates the host addresses bit0~bit15 for bounding box. + * ARGS: The word0 for the 64 bit address + */ + DMUB_GPINT__SET_BB_ADDR_WORD0 = 100, + + /** * DESC: Updates the trace buffer lower 32-bit mask. * ARGS: The new mask * RETURN: Lower 32-bit mask. @@ -1582,6 +1628,223 @@ struct dmub_rb_cmd_fw_assisted_mclk_switch_v2 { struct dmub_cmd_fw_assisted_mclk_switch_config_v2 config_data; }; +struct dmub_flip_addr_info { + uint32_t surf_addr_lo; + uint32_t surf_addr_c_lo; + uint32_t meta_addr_lo; + uint32_t meta_addr_c_lo; + uint16_t surf_addr_hi; + uint16_t surf_addr_c_hi; + uint16_t meta_addr_hi; + uint16_t meta_addr_c_hi; +}; + +struct dmub_fams2_flip_info { + union { + struct { + uint8_t is_immediate: 1; + } bits; + uint8_t all; + } config; + uint8_t otg_inst; + uint8_t pipe_mask; + uint8_t pad; + struct dmub_flip_addr_info addr_info; +}; + +struct dmub_rb_cmd_fams2_flip { + struct dmub_cmd_header header; + struct dmub_fams2_flip_info flip_info; +}; + +struct dmub_optc_state_v2 { + uint32_t v_total_min; + uint32_t v_total_max; + uint32_t v_total_mid; + uint32_t v_total_mid_frame_num; + uint8_t program_manual_trigger; + uint8_t tg_inst; + uint8_t pad[2]; +}; + +struct dmub_optc_position { + uint32_t vpos; + uint32_t hpos; + uint32_t frame; +}; + +struct dmub_rb_cmd_fams2_drr_update { + struct dmub_cmd_header header; + struct dmub_optc_state_v2 dmub_optc_state_req; +}; + +/* HW and FW global configuration data for FAMS2 */ +/* FAMS2 types and structs */ +enum fams2_stream_type { + FAMS2_STREAM_TYPE_NONE = 0, + FAMS2_STREAM_TYPE_VBLANK = 1, + FAMS2_STREAM_TYPE_VACTIVE = 2, + FAMS2_STREAM_TYPE_DRR = 3, + FAMS2_STREAM_TYPE_SUBVP = 4, +}; + +/* dynamic stream state */ +struct dmub_fams2_legacy_stream_dynamic_state { + uint8_t force_allow_at_vblank; + uint8_t pad[3]; +}; + +struct dmub_fams2_subvp_stream_dynamic_state { + uint16_t viewport_start_hubp_vline; + uint16_t viewport_height_hubp_vlines; + uint16_t viewport_start_c_hubp_vline; + uint16_t viewport_height_c_hubp_vlines; + uint16_t phantom_viewport_height_hubp_vlines; + uint16_t phantom_viewport_height_c_hubp_vlines; + uint16_t microschedule_start_otg_vline; + uint16_t mall_start_otg_vline; + uint16_t mall_start_hubp_vline; + uint16_t mall_start_c_hubp_vline; + uint8_t force_allow_at_vblank_only; + uint8_t pad[3]; +}; + +struct dmub_fams2_drr_stream_dynamic_state { + uint16_t stretched_vtotal; + uint8_t use_cur_vtotal; + uint8_t pad; +}; + +struct dmub_fams2_stream_dynamic_state { + uint64_t ref_tick; + uint32_t cur_vtotal; + uint16_t adjusted_allow_end_otg_vline; + uint8_t pad[2]; + struct dmub_optc_position ref_otg_pos; + struct dmub_optc_position target_otg_pos; + union { + struct dmub_fams2_legacy_stream_dynamic_state legacy; + struct dmub_fams2_subvp_stream_dynamic_state subvp; + struct dmub_fams2_drr_stream_dynamic_state drr; + } sub_state; +}; + +/* static stream state */ +struct dmub_fams2_legacy_stream_static_state { + uint8_t vactive_det_fill_delay_otg_vlines; + uint8_t programming_delay_otg_vlines; +}; + +struct dmub_fams2_subvp_stream_static_state { + uint16_t vratio_numerator; + uint16_t vratio_denominator; + uint16_t phantom_vtotal; + uint16_t phantom_vactive; + union { + struct { + uint8_t is_multi_planar : 1; + uint8_t is_yuv420 : 1; + } bits; + uint8_t all; + } config; + uint8_t programming_delay_otg_vlines; + uint8_t prefetch_to_mall_otg_vlines; + uint8_t phantom_otg_inst; + uint8_t phantom_pipe_mask; + uint8_t phantom_plane_pipe_masks[DMUB_MAX_PHANTOM_PLANES]; // phantom pipe mask per plane (for flip passthrough) +}; + +struct dmub_fams2_drr_stream_static_state { + uint16_t nom_stretched_vtotal; + uint8_t programming_delay_otg_vlines; + uint8_t only_stretch_if_required; + uint8_t pad[2]; +}; + +struct dmub_fams2_stream_static_state { + enum fams2_stream_type type; + uint32_t otg_vline_time_ns; + uint32_t otg_vline_time_ticks; + uint16_t htotal; + uint16_t vtotal; // nominal vtotal + uint16_t vblank_start; + uint16_t vblank_end; + uint16_t max_vtotal; + uint16_t allow_start_otg_vline; + uint16_t allow_end_otg_vline; + uint16_t drr_keepout_otg_vline; // after this vline, vtotal cannot be changed + uint8_t scheduling_delay_otg_vlines; // min time to budget for ready to microschedule start + uint8_t contention_delay_otg_vlines; // time to budget for contention on execution + uint8_t vline_int_ack_delay_otg_vlines; // min time to budget for vertical interrupt firing + uint8_t allow_to_target_delay_otg_vlines; // time from allow vline to target vline + union { + struct { + uint8_t is_drr: 1; // stream is DRR enabled + uint8_t clamp_vtotal_min: 1; // clamp vtotal to min instead of nominal + uint8_t min_ttu_vblank_usable: 1; // if min ttu vblank is above wm, no force pstate is needed in blank + } bits; + uint8_t all; + } config; + uint8_t otg_inst; + uint8_t pipe_mask; // pipe mask for the whole config + uint8_t num_planes; + uint8_t plane_pipe_masks[DMUB_MAX_PLANES]; // pipe mask per plane (for flip passthrough) + uint8_t pad[DMUB_MAX_PLANES % 4]; + union { + struct dmub_fams2_legacy_stream_static_state legacy; + struct dmub_fams2_subvp_stream_static_state subvp; + struct dmub_fams2_drr_stream_static_state drr; + } sub_state; +}; + +/** + * enum dmub_fams2_allow_delay_check_mode - macroscheduler mode for breaking on excessive + * p-state request to allow latency + */ +enum dmub_fams2_allow_delay_check_mode { + /* No check for request to allow delay */ + FAMS2_ALLOW_DELAY_CHECK_NONE = 0, + /* Check for request to allow delay */ + FAMS2_ALLOW_DELAY_CHECK_FROM_START = 1, + /* Check for prepare to allow delay */ + FAMS2_ALLOW_DELAY_CHECK_FROM_PREPARE = 2, +}; + +union dmub_fams2_global_feature_config { + struct { + uint32_t enable: 1; + uint32_t enable_ppt_check: 1; + uint32_t enable_stall_recovery: 1; + uint32_t enable_debug: 1; + uint32_t enable_offload_flip: 1; + uint32_t enable_visual_confirm: 1; + uint32_t allow_delay_check_mode: 2; + uint32_t reserved: 24; + } bits; + uint32_t all; +}; + +struct dmub_cmd_fams2_global_config { + uint32_t max_allow_delay_us; // max delay to assert allow from uclk change begin + uint32_t lock_wait_time_us; // time to forecast acquisition of lock + uint32_t num_streams; + union dmub_fams2_global_feature_config features; + uint8_t pad[3]; +}; + +union dmub_cmd_fams2_config { + struct dmub_cmd_fams2_global_config global; + struct dmub_fams2_stream_static_state stream; +}; + +/** + * DMUB rb command definition for FAMS2 (merged SubVP, FPO, Legacy) + */ +struct dmub_rb_cmd_fams2 { + struct dmub_cmd_header header; + union dmub_cmd_fams2_config config; +}; + /** * enum dmub_cmd_idle_opt_type - Idle optimization command type. */ @@ -2263,6 +2526,9 @@ enum dmub_cmd_fams_type { * on (for any SubVP cases that use a DRR display) */ DMUB_CMD__FAMS_SET_MANUAL_TRIGGER = 3, + DMUB_CMD__FAMS2_CONFIG = 4, + DMUB_CMD__FAMS2_DRR_UPDATE = 5, + DMUB_CMD__FAMS2_FLIP = 6, }; /** @@ -3547,6 +3813,7 @@ enum hw_lock_client { * Replay is the client of HW Lock Manager. */ HW_LOCK_CLIENT_REPLAY = 4, + HW_LOCK_CLIENT_FAMS2 = 5, /** * Invalid client. */ @@ -3639,6 +3906,87 @@ enum dmub_cmd_abm_type { * on restore we update state with passed in data. */ DMUB_CMD__ABM_SAVE_RESTORE = 7, + + /** + * Query ABM caps. + */ + DMUB_CMD__ABM_QUERY_CAPS = 8, + + /** + * Set ABM Events + */ + DMUB_CMD__ABM_SET_EVENT = 9, +}; + +struct abm_ace_curve { + /** + * @offsets: ACE curve offsets. + */ + uint32_t offsets[ABM_MAX_NUM_OF_ACE_SEGMENTS]; + + /** + * @thresholds: ACE curve thresholds. + */ + uint32_t thresholds[ABM_MAX_NUM_OF_ACE_SEGMENTS]; + + /** + * @slopes: ACE curve slopes. + */ + uint32_t slopes[ABM_MAX_NUM_OF_ACE_SEGMENTS]; +}; + +struct fixed_pt_format { + /** + * @sign_bit: Indicates whether one bit is reserved for the sign. + */ + bool sign_bit; + + /** + * @num_int_bits: Number of bits used for integer part. + */ + uint8_t num_int_bits; + + /** + * @num_frac_bits: Number of bits used for fractional part. + */ + uint8_t num_frac_bits; + + /** + * @pad: Explicit padding to 4 byte boundary. + */ + uint8_t pad; +}; + +struct abm_caps { + /** + * @num_hg_bins: Number of histogram bins. + */ + uint8_t num_hg_bins; + + /** + * @num_ace_segments: Number of ACE curve segments. + */ + uint8_t num_ace_segments; + + /** + * @pad: Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; + + /** + * @ace_thresholds_format: Format of the ACE thresholds. If not programmable, it is set to 0. + */ + struct fixed_pt_format ace_thresholds_format; + + /** + * @ace_offsets_format: Format of the ACE offsets. If not programmable, it is set to 0. + */ + struct fixed_pt_format ace_offsets_format; + + /** + * @ace_slopes_format: Format of the ACE slopes. + */ + struct fixed_pt_format ace_slopes_format; }; /** @@ -4049,6 +4397,54 @@ struct dmub_rb_cmd_abm_pause { }; /** + * Data passed from driver to FW in a DMUB_CMD__ABM_QUERY_CAPS command. + */ +struct dmub_cmd_abm_query_caps_in { + /** + * Panel instance. + */ + uint8_t panel_inst; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[3]; +}; + +/** + * Data passed from FW to driver in a DMUB_CMD__ABM_QUERY_CAPS command. + */ +struct dmub_cmd_abm_query_caps_out { + /** + * SW Algorithm caps. + */ + struct abm_caps sw_caps; + + /** + * ABM HW caps. + */ + struct abm_caps hw_caps; +}; + +/** + * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. + */ +struct dmub_rb_cmd_abm_query_caps { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed between FW and driver in a DMUB_CMD__ABM_QUERY_CAPS command. + */ + union { + struct dmub_cmd_abm_query_caps_in abm_query_caps_in; + struct dmub_cmd_abm_query_caps_out abm_query_caps_out; + } data; +}; + +/** * Definition of a DMUB_CMD__ABM_SAVE_RESTORE command. */ struct dmub_rb_cmd_abm_save_restore { @@ -4079,6 +4475,51 @@ struct dmub_rb_cmd_abm_save_restore { }; /** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. + */ +struct dmub_cmd_abm_set_event_data { + + /** + * VB Scaling Init. Strength Mapping + * Byte 0: 0~255 for VB level 0 + * Byte 1: 0~255 for VB level 1 + * Byte 2: 0~255 for VB level 2 + * Byte 3: 0~255 for VB level 3 + */ + uint32_t vb_scaling_strength_mapping; + /** + * VariBright Scaling Enable + */ + uint8_t vb_scaling_enable; + /** + * Panel Control HW instance mask. + * Bit 0 is Panel Control HW instance 0. + * Bit 1 is Panel Control HW instance 1. + */ + uint8_t panel_mask; + + /** + * Explicit padding to 4 byte boundary. + */ + uint8_t pad[2]; +}; + +/** + * Definition of a DMUB_CMD__ABM_SET_EVENT command. + */ +struct dmub_rb_cmd_abm_set_event { + /** + * Command header. + */ + struct dmub_cmd_header header; + + /** + * Data passed from driver to FW in a DMUB_CMD__ABM_SET_EVENT command. + */ + struct dmub_cmd_abm_set_event_data abm_set_event_data; +}; + +/** * Data passed from driver to FW in a DMUB_CMD__QUERY_FEATURE_CAPS command. */ struct dmub_cmd_query_feature_caps_data { @@ -4613,6 +5054,16 @@ union dmub_rb_cmd { struct dmub_rb_cmd_abm_save_restore abm_save_restore; /** + * Definition of a DMUB_CMD__ABM_QUERY_CAPS command. + */ + struct dmub_rb_cmd_abm_query_caps abm_query_caps; + + /** + * Definition of a DMUB_CMD__ABM_SET_EVENT command. + */ + struct dmub_rb_cmd_abm_set_event abm_set_event; + + /** * Definition of a DMUB_CMD__DP_AUX_ACCESS command. */ struct dmub_rb_cmd_dp_aux_access dp_aux_access; @@ -4722,7 +5173,11 @@ union dmub_rb_cmd { * Definition of a DMUB_CMD__PSP_ASSR_ENABLE command. */ struct dmub_rb_cmd_assr_enable assr_enable; + struct dmub_rb_cmd_fams2 fams2_config; + + struct dmub_rb_cmd_fams2_drr_update fams2_drr_update; + struct dmub_rb_cmd_fams2_flip fams2_flip; }; /** @@ -4759,10 +5214,6 @@ union dmub_rb_out_cmd { //< DMUB_RB>==================================================================== //============================================================================== -#if defined(__cplusplus) -extern "C" { -#endif - /** * struct dmub_rb_init_params - Initialization params for DMUB ringbuffer */ @@ -5039,10 +5490,6 @@ static inline void dmub_rb_get_return_data(struct dmub_rb *rb, dmub_memcpy(cmd, rd_ptr, DMUB_RB_CMD_SIZE); } -#if defined(__cplusplus) -} -#endif - //============================================================================== //</DMUB_RB>==================================================================== //============================================================================== |