diff options
Diffstat (limited to 'drivers/gpu/drm/amd/display/dc/inc')
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/clock_source.h | 1 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/core_types.h | 27 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h | 6 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h | 55 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h | 8 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h | 24 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h | 56 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h | 9 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h | 726 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/opp.h | 7 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/optc.h | 4 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/hw/transform.h | 28 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/inc/resource.h | 18 |
16 files changed, 805 insertions, 174 deletions
diff --git a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h index 8f8ac8e29ed0..ed2f8005d85e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/clock_source.h +++ b/drivers/gpu/drm/amd/display/dc/inc/clock_source.h @@ -96,6 +96,7 @@ struct pixel_clk_params { /*> de-spread info, relevant only for on-the-fly tune-up pixel rate*/ enum dc_pixel_encoding pixel_encoding; struct pixel_clk_flags flags; + uint32_t dio_se_pix_per_cycle; }; /** diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 028b2f971e36..f58c27ad8b3e 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -39,6 +39,7 @@ #include "panel_cntl.h" #include "dmub/inc/dmub_cmd.h" #include "pg_cntl.h" +#include "spl/dc_spl.h" #define MAX_CLOCK_SOURCES 7 #define MAX_SVP_PHANTOM_STREAMS 2 @@ -60,6 +61,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state, #include "transform.h" #include "dpp.h" +#include "dml2/dml21/inc/dml_top_dchub_registers.h" +#include "dml2/dml21/inc/dml_top_types.h" + struct resource_pool; struct dc_state; struct resource_context; @@ -159,6 +163,7 @@ struct resource_funcs { struct dc *dc, struct dc_state *new_ctx, struct dc_stream_state *stream); + enum dc_status (*patch_unknown_plane_state)( struct dc_plane_state *plane_state); @@ -166,6 +171,7 @@ struct resource_funcs { struct resource_context *res_ctx, const struct resource_pool *pool, struct dc_stream_state *stream); + void (*populate_dml_writeback_from_context)( struct dc *dc, struct resource_context *res_ctx, @@ -176,6 +182,7 @@ struct resource_funcs { struct dc_state *context, display_e2e_pipe_params_st *pipes, int pipe_cnt); + void (*update_bw_bounding_box)( struct dc *dc, struct clk_bw_params *bw_params); @@ -292,7 +299,6 @@ struct resource_pool { struct abm *abm; struct dmcu *dmcu; struct dmub_psr *psr; - struct dmub_replay *replay; struct abm *multiple_abms[MAX_PIPES]; @@ -342,6 +348,13 @@ struct plane_resource { /* scl_data is scratch space required to program a plane */ struct scaler_data scl_data; /* Below pointers to hw objects are required to enable the plane */ + /* spl_in and spl_out are the input and output structures for SPL + * which are required when using Scaler Programming Library + * these are scratch spaces needed when programming a plane + */ + struct spl_in spl_in; + struct spl_out spl_out; + /* Below pointers to hw objects are required to enable the plane */ struct hubp *hubp; struct mem_input *mi; struct input_pixel_processor *ipp; @@ -386,6 +399,11 @@ union pipe_update_flags { uint32_t raw; }; +struct pixel_rate_divider { + uint32_t div_factor1; + uint32_t div_factor2; +}; + enum p_state_switch_method { P_STATE_UNKNOWN = 0, P_STATE_V_BLANK = 1, @@ -440,6 +458,8 @@ struct pipe_ctx { int det_buffer_size_kb; bool unbounded_req; unsigned int surface_size_in_mall_bytes; + struct dml2_dchub_per_pipe_register_set hubp_regs; + struct dml2_hubp_pipe_mcache_regs mcache_regs; struct dwbc *dwbc; struct mcif_wb *mcif_wb; @@ -449,6 +469,7 @@ struct pipe_ctx { bool has_vactive_margin; /* subvp_index: only valid if the pipe is a SUBVP_MAIN*/ uint8_t subvp_index; + struct pixel_rate_divider pixel_rate_divider; }; /* Data used for dynamic link encoder assignment. @@ -509,6 +530,10 @@ struct dcn_bw_output { unsigned int mall_subvp_size_bytes; unsigned int legacy_svp_drr_stream_index; bool legacy_svp_drr_stream_index_valid; + struct dml2_mcache_surface_allocation mcache_allocations[DML2_MAX_PLANES]; + struct dmub_fams2_stream_static_state fams2_stream_params[DML2_MAX_PLANES]; + unsigned fams2_stream_count; + struct dml2_display_arb_regs arb_regs; }; union bw_output { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h index 4f7480f60c85..d5fefce3e74b 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr.h @@ -39,6 +39,8 @@ #define WM_C 2 #define WM_D 3 #define WM_SET_COUNT 4 +#define WM_1A 2 +#define WM_1B 3 #define DCN_MINIMUM_DISPCLK_Khz 100000 #define DCN_MINIMUM_DPPCLK_Khz 100000 @@ -242,14 +244,14 @@ struct wm_table { struct dummy_pstate_entry { unsigned int dram_speed_mts; - double dummy_pstate_latency_us; + unsigned int dummy_pstate_latency_us; }; struct clk_bw_params { unsigned int vram_type; unsigned int num_channels; unsigned int dram_channel_width_bytes; - unsigned int dispclk_vco_khz; + unsigned int dispclk_vco_khz; unsigned int dc_mode_softmax_memclk; unsigned int max_memclk_mhz; struct clk_limit_table clk_table; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h index 4ba18ea57aad..12282f96dfe1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/clk_mgr_internal.h @@ -97,11 +97,6 @@ enum dentist_divider_range { #define CLK_COMMON_REG_LIST_DCN_BASE() \ SR(DENTIST_DISPCLK_CNTL) -#define VBIOS_SMU_MSG_BOX_REG_LIST_RV() \ - .MP1_SMN_C2PMSG_91 = mmMP1_SMN_C2PMSG_91, \ - .MP1_SMN_C2PMSG_83 = mmMP1_SMN_C2PMSG_83, \ - .MP1_SMN_C2PMSG_67 = mmMP1_SMN_C2PMSG_67 - #define CLK_COMMON_REG_LIST_DCN_201() \ SR(DENTIST_DISPCLK_CNTL), \ CLK_SRI(CLK4_CLK_PLL_REQ, CLK4, 0), \ @@ -113,7 +108,7 @@ enum dentist_divider_range { CLK_SRI(CLK3_CLK2_DFS_CNTL, CLK3, 0) #define CLK_REG_LIST_DCN3() \ - CLK_COMMON_REG_LIST_DCN_BASE(), \ + SR(DENTIST_DISPCLK_CNTL), \ CLK_SRI(CLK0_CLK_PLL_REQ, CLK02, 0), \ CLK_SRI(CLK0_CLK2_DFS_CNTL, CLK02, 0) @@ -190,41 +185,39 @@ enum dentist_divider_range { CLK_SF(CLK0_CLK_PLL_REQ, FbMult_int, mask_sh),\ CLK_SF(CLK0_CLK_PLL_REQ, FbMult_frac, mask_sh) +#define CLK_REG_LIST_DCN401() \ + CLK_SR_DCN401(CLK0_CLK_PLL_REQ, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK0_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK1_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK2_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK3_DFS_CNTL, CLK01, 0), \ + CLK_SR_DCN401(CLK0_CLK4_DFS_CNTL, CLK01, 0) + +#define CLK_COMMON_MASK_SH_LIST_DCN401(mask_sh) \ + CLK_COMMON_MASK_SH_LIST_DCN321(mask_sh) + #define CLK_REG_FIELD_LIST(type) \ type DPREFCLK_SRC_SEL; \ type DENTIST_DPREFCLK_WDIVIDER; \ type DENTIST_DISPCLK_WDIVIDER; \ type DENTIST_DISPCLK_CHG_DONE; -/* - *************************************************************************************** - ****************** Clock Manager Private Structures *********************************** - *************************************************************************************** - */ #define CLK20_REG_FIELD_LIST(type) \ type DENTIST_DPPCLK_WDIVIDER; \ type DENTIST_DPPCLK_CHG_DONE; \ type FbMult_int; \ type FbMult_frac; -#define VBIOS_SMU_REG_FIELD_LIST(type) \ - type CONTENT; - -struct clk_mgr_shift { - CLK_REG_FIELD_LIST(uint8_t) - CLK20_REG_FIELD_LIST(uint8_t) - VBIOS_SMU_REG_FIELD_LIST(uint32_t) -}; - -struct clk_mgr_mask { - CLK_REG_FIELD_LIST(uint32_t) - CLK20_REG_FIELD_LIST(uint32_t) - VBIOS_SMU_REG_FIELD_LIST(uint32_t) -}; +/* + *************************************************************************************** + ****************** Clock Manager Private Structures *********************************** + *************************************************************************************** + */ struct clk_mgr_registers { uint32_t DPREFCLK_CNTL; uint32_t DENTIST_DISPCLK_CNTL; + uint32_t CLK4_CLK2_CURRENT_CNT; uint32_t CLK4_CLK_PLL_REQ; @@ -253,10 +246,16 @@ struct clk_mgr_registers { uint32_t CLK0_CLK1_DFS_CNTL; uint32_t CLK0_CLK3_DFS_CNTL; uint32_t CLK0_CLK4_DFS_CNTL; +}; - uint32_t MP1_SMN_C2PMSG_67; - uint32_t MP1_SMN_C2PMSG_83; - uint32_t MP1_SMN_C2PMSG_91; +struct clk_mgr_shift { + CLK_REG_FIELD_LIST(uint8_t) + CLK20_REG_FIELD_LIST(uint8_t) +}; + +struct clk_mgr_mask { + CLK_REG_FIELD_LIST(uint32_t) + CLK20_REG_FIELD_LIST(uint32_t) }; enum clock_type { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h index d4c7885fc916..4fb1aacee894 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h @@ -176,6 +176,11 @@ struct dccg_funcs { enum pixel_rate_div k1, enum pixel_rate_div k2); + void (*get_pixel_rate_div)(struct dccg *dccg, + uint32_t otg_inst, + uint32_t *div_factor1, + uint32_t *div_factor2); + void (*set_valid_pixel_rate)( struct dccg *dccg, int ref_dtbclk_khz, @@ -208,7 +213,8 @@ struct dccg_funcs { uint32_t otg_inst); void (*set_dto_dscclk)( struct dccg *dccg, - uint32_t dsc_inst); + uint32_t dsc_inst, + bool enable); void (*set_ref_dscclk)(struct dccg *dccg, uint32_t dsc_inst); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h index 305fdc127bfc..a73cb8f731b3 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dchubbub.h @@ -33,6 +33,8 @@ * blocks for the Data Fabric Interface that are not clock/power gated. */ +#include "dc/dc_hw_types.h" + enum dcc_control { dcc_control__256_256_xxx, dcc_control__128_128_xxx, @@ -72,8 +74,15 @@ enum dcn_hubbub_page_table_depth { enum dcn_hubbub_page_table_block_size { DCN_PAGE_TABLE_BLOCK_SIZE_4KB = 0, + DCN_PAGE_TABLE_BLOCK_SIZE_8KB = 1, + DCN_PAGE_TABLE_BLOCK_SIZE_16KB = 2, + DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3, DCN_PAGE_TABLE_BLOCK_SIZE_64KB = 4, - DCN_PAGE_TABLE_BLOCK_SIZE_32KB = 3 + DCN_PAGE_TABLE_BLOCK_SIZE_128KB = 5, + DCN_PAGE_TABLE_BLOCK_SIZE_256KB = 6, + DCN_PAGE_TABLE_BLOCK_SIZE_512KB = 7, + DCN_PAGE_TABLE_BLOCK_SIZE_1024KB = 8, + DCN_PAGE_TABLE_BLOCK_SIZE_2048KB = 9 }; struct dcn_hubbub_phys_addr_config { @@ -147,6 +156,17 @@ struct hubbub_funcs { enum segment_order *segment_order_horz, enum segment_order *segment_order_vert); + bool (*dcc_support_swizzle_addr3)( + enum swizzle_mode_addr3_values swizzle, + unsigned int plane_pitch, + unsigned int bytes_per_element, + enum segment_order *segment_order_horz, + enum segment_order *segment_order_vert); + + bool (*dcc_support_pixel_format_plane0_plane1)( + enum surface_pixel_format format, + unsigned int *plane0_bpe, + unsigned int *plane1_bpe); bool (*dcc_support_pixel_format)( enum surface_pixel_format format, unsigned int *bytes_per_element); @@ -201,6 +221,8 @@ struct hubbub_funcs { void (*set_request_limit)(struct hubbub *hubbub, int memory_channel_count, int words_per_channel); void (*dchubbub_init)(struct hubbub *hubbub); void (*get_mall_en)(struct hubbub *hubbub, unsigned int *mall_in_use); + void (*program_det_segments)(struct hubbub *hubbub, int hubp_inst, unsigned det_buffer_size_seg); + void (*program_compbuf_segments)(struct hubbub *hubbub, unsigned compbuf_size_seg, bool safe_to_increase); }; struct hubbub { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h index ca8de345d039..9ac7fc717a92 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/dpp.h @@ -329,6 +329,10 @@ struct dpp_funcs { void (*dpp_get_gamut_remap)(struct dpp *dpp_base, struct dpp_grph_csc_adjustment *adjust); + void (*set_cursor_matrix)( + struct dpp *dpp_base, + enum dc_color_space color_space, + struct dc_csc_transform cursor_csc_color_matrix); }; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h index 72610cd7eae0..bcd7b22a1627 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/hubp.h @@ -41,6 +41,8 @@ #include "mem_input.h" #include "cursor_reg_cache.h" +#include "dml2/dml21/inc/dml_top_dchub_registers.h" + #define OPP_ID_INVALID 0xf #define MAX_TTU 0xffffff @@ -65,6 +67,37 @@ enum hubp_ind_block_size { hubp_ind_block_64b_no_128bcl, }; +enum hubp_3dlut_fl_mode { + hubp_3dlut_fl_mode_disable = 0, + hubp_3dlut_fl_mode_native_1 = 1, + hubp_3dlut_fl_mode_native_2 = 2, + hubp_3dlut_fl_mode_transform = 3 +}; + +enum hubp_3dlut_fl_format { + hubp_3dlut_fl_format_unorm_12msb_bitslice = 0, + hubp_3dlut_fl_format_unorm_12lsb_bitslice = 1, + hubp_3dlut_fl_format_float_fp1_5_10 = 2 +}; + +enum hubp_3dlut_fl_addressing_mode { + hubp_3dlut_fl_addressing_mode_sw_linear = 0, + hubp_3dlut_fl_addressing_mode_simple_linear = 1 +}; + +enum hubp_3dlut_fl_width { + hubp_3dlut_fl_width_17 = 17, + hubp_3dlut_fl_width_33 = 33, + hubp_3dlut_fl_width_transformed = 4916 +}; + +enum hubp_3dlut_fl_crossbar_bit_slice { + hubp_3dlut_fl_crossbar_bit_slice_0_15 = 0, + hubp_3dlut_fl_crossbar_bit_slice_16_31 = 1, + hubp_3dlut_fl_crossbar_bit_slice_32_47 = 2, + hubp_3dlut_fl_crossbar_bit_slice_48_63 = 3 +}; + struct hubp { const struct hubp_funcs *funcs; struct dc_context *ctx; @@ -211,17 +244,36 @@ struct hubp_funcs { bool (*hubp_in_blank)(struct hubp *hubp); void (*hubp_soft_reset)(struct hubp *hubp, bool reset); + void (*hubp_set_flip_int)(struct hubp *hubp); + void (*hubp_update_force_pstate_disallow)(struct hubp *hubp, bool allow); void (*hubp_update_force_cursor_pstate_disallow)(struct hubp *hubp, bool allow); void (*hubp_update_mall_sel)(struct hubp *hubp, uint32_t mall_sel, bool c_cursor); void (*hubp_prepare_subvp_buffering)(struct hubp *hubp, bool enable); - - void (*hubp_set_flip_int)(struct hubp *hubp); + void (*hubp_surface_update_lock)(struct hubp *hubp, + bool lock); void (*program_extended_blank)(struct hubp *hubp, unsigned int min_dst_y_next_start_optimized); void (*hubp_wait_pipe_read_start)(struct hubp *hubp); + void (*hubp_update_3dlut_fl_bias_scale)(struct hubp *hubp, uint16_t bias, uint16_t scale); + void (*hubp_program_3dlut_fl_mode)(struct hubp *hubp, + enum hubp_3dlut_fl_mode mode); + void (*hubp_program_3dlut_fl_format)(struct hubp *hubp, + enum hubp_3dlut_fl_format format); + void (*hubp_program_3dlut_fl_addr)(struct hubp *hubp, + const struct dc_plane_address address); + void (*hubp_program_3dlut_fl_dlg_param)(struct hubp *hubp, int refcyc_per_3dlut_group); + void (*hubp_enable_3dlut_fl)(struct hubp *hubp, bool enable); + void (*hubp_program_3dlut_fl_addressing_mode)(struct hubp *hubp, enum hubp_3dlut_fl_addressing_mode addr_mode); + void (*hubp_program_3dlut_fl_width)(struct hubp *hubp, enum hubp_3dlut_fl_width width); + void (*hubp_program_3dlut_fl_tmz_protected)(struct hubp *hubp, bool protection_enabled); + void (*hubp_program_3dlut_fl_crossbar)(struct hubp *hubp, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_y_g, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cb_b, + enum hubp_3dlut_fl_crossbar_bit_slice bit_slice_cr_r); + int (*hubp_get_3dlut_fl_done)(struct hubp *hubp); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h index 86c12cd6f47d..5f6c7daa14d9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mem_input.h @@ -29,6 +29,7 @@ #include "include/grph_object_id.h" #include "dml/display_mode_structs.h" +#include "dml2/dml21/inc/dml_top_dchub_registers.h" struct dchub_init_data; struct cstate_pstate_watermarks_st { @@ -45,7 +46,7 @@ struct dcn_watermarks { uint32_t urgent_ns; uint32_t frac_urg_bw_nom; uint32_t frac_urg_bw_flip; - int32_t urgent_latency_ns; + uint32_t urgent_latency_ns; struct cstate_pstate_watermarks_st cstate_pstate; uint32_t usr_retraining_ns; }; @@ -57,6 +58,12 @@ union dcn_watermark_set { struct dcn_watermarks c; struct dcn_watermarks d; }; // legacy + struct { + struct dml2_dchub_watermark_regs a; + struct dml2_dchub_watermark_regs b; + struct dml2_dchub_watermark_regs c; + struct dml2_dchub_watermark_regs d; + } dcn4; //dcn4+ }; struct dce_watermarks { diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h index 34a398f23fc6..40a9b3471208 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/mpc.h @@ -1,4 +1,5 @@ -/* Copyright 2012-15 Advanced Micro Devices, Inc. +/* + * Copyright 2012-15 Advanced Micro Devices, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), @@ -96,6 +97,29 @@ enum mpcc_alpha_blend_mode { MPCC_ALPHA_BLEND_MODE_GLOBAL_ALPHA }; +enum mpcc_movable_cm_location { + MPCC_MOVABLE_CM_LOCATION_BEFORE, + MPCC_MOVABLE_CM_LOCATION_AFTER, +}; + +enum MCM_LUT_XABLE { + MCM_LUT_DISABLE, + MCM_LUT_DISABLED = MCM_LUT_DISABLE, + MCM_LUT_ENABLE, + MCM_LUT_ENABLED = MCM_LUT_ENABLE, +}; + +enum MCM_LUT_ID { + MCM_LUT_3DLUT, + MCM_LUT_1DLUT, + MCM_LUT_SHAPER +}; + +union mcm_lut_params { + const struct pwl_params *pwl; + const struct tetrahedral_params *lut3d; +}; + /** * struct mpcc_blnd_cfg - MPCC blending configuration */ @@ -163,6 +187,7 @@ struct mpcc_blnd_cfg { struct mpc_grph_gamut_adjustment { struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE]; enum graphics_gamut_adjust_type gamut_adjust_type; + enum mpcc_gamut_remap_id mpcc_gamut_remap_block_id; }; struct mpcc_sm_cfg { @@ -282,33 +307,48 @@ struct mpcc_state { * struct mpc_funcs - funcs */ struct mpc_funcs { + /** + * @read_mpcc_state: + * + * Read register content from given MPCC physical instance. + * + * Parameters: + * + * - [in/out] mpc - MPC context + * - [in] mpcc_instance - MPC context instance + * - [in] mpcc_state - MPC context state + * + * Return: + * + * void + */ void (*read_mpcc_state)( struct mpc *mpc, int mpcc_inst, struct mpcc_state *s); /** - * @insert_plane: - * - * Insert DPP into MPC tree based on specified blending position. - * Only used for planes that are part of blending chain for OPP output - * - * Parameters: - * - * - [in/out] mpc - MPC context. - * - [in/out] tree - MPC tree structure that plane will be added to. - * - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - * - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. - * stereo mix must disable for the very bottom layer of the tree config. - * - [in] insert_above_mpcc - Insert new plane above this MPCC. - * If NULL, insert as bottom plane. - * - [in] dpp_id - DPP instance for the plane to be added. - * - [in] mpcc_id - The MPCC physical instance to use for blending. - * - * Return: - * - * struct mpcc* - MPCC that was added. - */ + * @insert_plane: + * + * Insert DPP into MPC tree based on specified blending position. + * Only used for planes that are part of blending chain for OPP output + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in/out] tree - MPC tree structure that plane will be added to. + * - [in] blnd_cfg - MPCC blending configuration for the new blending layer. + * - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. + * stereo mix must disable for the very bottom layer of the tree config. + * - [in] insert_above_mpcc - Insert new plane above this MPCC. + * If NULL, insert as bottom plane. + * - [in] dpp_id - DPP instance for the plane to be added. + * - [in] mpcc_id - The MPCC physical instance to use for blending. + * + * Return: + * + * struct mpcc* - MPCC that was added. + */ struct mpcc* (*insert_plane)( struct mpc *mpc, struct mpc_tree *tree, @@ -319,107 +359,117 @@ struct mpc_funcs { int mpcc_id); /** - * @remove_mpcc: - * - * Remove a specified MPCC from the MPC tree. - * - * Parameters: - * - * - [in/out] mpc - MPC context. - * - [in/out] tree - MPC tree structure that plane will be removed from. - * - [in/out] mpcc - MPCC to be removed from tree. - * - * Return: - * - * void - */ + * @remove_mpcc: + * + * Remove a specified MPCC from the MPC tree. + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in/out] tree - MPC tree structure that plane will be removed from. + * - [in/out] mpcc - MPCC to be removed from tree. + * + * Return: + * + * void + */ void (*remove_mpcc)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc *mpcc); /** - * @mpc_init: - * - * Reset the MPCC HW status by disconnecting all muxes. - * - * Parameters: - * - * - [in/out] mpc - MPC context. - * - * Return: - * - * void - */ + * @mpc_init: + * + * Reset the MPCC HW status by disconnecting all muxes. + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * + * Return: + * + * void + */ void (*mpc_init)(struct mpc *mpc); + + /** + * @mpc_init_single_inst: + * + * Initialize given MPCC physical instance. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id - The MPCC physical instance to be initialized. + */ void (*mpc_init_single_inst)( struct mpc *mpc, unsigned int mpcc_id); /** - * @update_blending: - * - * Update the blending configuration for a specified MPCC. - * - * Parameters: - * - * - [in/out] mpc - MPC context. - * - [in] blnd_cfg - MPCC blending configuration. - * - [in] mpcc_id - The MPCC physical instance. - * - * Return: - * - * void - */ + * @update_blending: + * + * Update the blending configuration for a specified MPCC. + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in] blnd_cfg - MPCC blending configuration. + * - [in] mpcc_id - The MPCC physical instance. + * + * Return: + * + * void + */ void (*update_blending)( struct mpc *mpc, struct mpcc_blnd_cfg *blnd_cfg, int mpcc_id); /** - * @cursor_lock: - * - * Lock cursor updates for the specified OPP. OPP defines the set of - * MPCC that are locked together for cursor. - * - * Parameters: - * - * - [in] mpc - MPC context. - * - [in] opp_id - The OPP to lock cursor updates on - * - [in] lock - lock/unlock the OPP - * - * Return: - * - * void - */ + * @cursor_lock: + * + * Lock cursor updates for the specified OPP. OPP defines the set of + * MPCC that are locked together for cursor. + * + * Parameters: + * + * - [in] mpc - MPC context. + * - [in] opp_id - The OPP to lock cursor updates on + * - [in] lock - lock/unlock the OPP + * + * Return: + * + * void + */ void (*cursor_lock)( struct mpc *mpc, int opp_id, bool lock); /** - * @insert_plane_to_secondary: - * - * Add DPP into secondary MPC tree based on specified blending - * position. Only used for planes that are part of blending chain for - * DWB output - * - * Parameters: - * - * - [in/out] mpc - MPC context. - * - [in/out] tree - MPC tree structure that plane will be added to. - * - [in] blnd_cfg - MPCC blending configuration for the new blending layer. - * - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. - * stereo mix must disable for the very bottom layer of the tree config. - * - [in] insert_above_mpcc - Insert new plane above this MPCC. If - * NULL, insert as bottom plane. - * - [in] dpp_id - DPP instance for the plane to be added. - * - [in] mpcc_id - The MPCC physical instance to use for blending. - * - * Return: - * - * struct mpcc* - MPCC that was added. - */ + * @insert_plane_to_secondary: + * + * Add DPP into secondary MPC tree based on specified blending + * position. Only used for planes that are part of blending chain for + * DWB output + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in/out] tree - MPC tree structure that plane will be added to. + * - [in] blnd_cfg - MPCC blending configuration for the new blending layer. + * - [in] sm_cfg - MPCC stereo mix configuration for the new blending layer. + * stereo mix must disable for the very bottom layer of the tree config. + * - [in] insert_above_mpcc - Insert new plane above this MPCC. If + * NULL, insert as bottom plane. + * - [in] dpp_id - DPP instance for the plane to be added. + * - [in] mpcc_id - The MPCC physical instance to use for blending. + * + * Return: + * + * struct mpcc* - MPCC that was added. + */ struct mpcc* (*insert_plane_to_secondary)( struct mpc *mpc, struct mpc_tree *tree, @@ -430,81 +480,301 @@ struct mpc_funcs { int mpcc_id); /** - * @remove_mpcc_from_secondary: - * - * Remove a specified DPP from the 'secondary' MPC tree. - * - * Parameters: - * - * - [in/out] mpc - MPC context. - * - [in/out] tree - MPC tree structure that plane will be removed from. - * - [in] mpcc - MPCC to be removed from tree. - * - * Return: - * - * void - */ + * @remove_mpcc_from_secondary: + * + * Remove a specified DPP from the 'secondary' MPC tree. + * + * Parameters: + * + * - [in/out] mpc - MPC context. + * - [in/out] tree - MPC tree structure that plane will be removed from. + * - [in] mpcc - MPCC to be removed from tree. + * + * Return: + * + * void + */ void (*remove_mpcc_from_secondary)( struct mpc *mpc, struct mpc_tree *tree, struct mpcc *mpcc); + /** + * @get_mpcc_for_dpp_from_secondary: + * + * Find, if it exists, a MPCC from a given 'secondary' MPC tree that + * is associated with specified plane. + * + * Parameters: + * - [in/out] tree - MPC tree structure to search for plane. + * - [in] dpp_id - DPP to be searched. + * + * Return: + * + * struct mpcc* - pointer to plane or NULL if no plane found. + */ struct mpcc* (*get_mpcc_for_dpp_from_secondary)( struct mpc_tree *tree, int dpp_id); + /** + * @get_mpcc_for_dpp: + * + * Find, if it exists, a MPCC from a given MPC tree that + * is associated with specified plane. + * + * Parameters: + * - [in/out] tree - MPC tree structure to search for plane. + * - [in] dpp_id - DPP to be searched. + * + * Return: + * + * struct mpcc* - pointer to plane or NULL if no plane found. + */ struct mpcc* (*get_mpcc_for_dpp)( struct mpc_tree *tree, int dpp_id); + /** + * @wait_for_idle: + * + * Wait for a MPCC in MPC context to enter idle state. + * + * Parameters: + * - [in/out] mpc - MPC Context. + * - [in] id - MPCC to wait for idle state. + * + * Return: + * + * void + */ void (*wait_for_idle)(struct mpc *mpc, int id); + /** + * @assert_mpcc_idle_before_connect: + * + * Assert if MPCC in MPC context is in idle state. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id - MPCC to assert idle state. + * + * Return: + * + * void + */ void (*assert_mpcc_idle_before_connect)(struct mpc *mpc, int mpcc_id); + /** + * @init_mpcc_list_from_hw: + * + * Iterate through the MPCC array from a given MPC context struct + * and configure each MPCC according to its registers' values. + * + * Parameters: + * - [in/out] mpc - MPC context to initialize MPCC array. + * - [in/out] tree - MPC tree structure containing MPCC contexts to initialize. + * + * Return: + * + * void + */ void (*init_mpcc_list_from_hw)( struct mpc *mpc, struct mpc_tree *tree); + /** + * @set_denorm: + * + * Set corresponding OPP DENORM_CONTROL register value to specific denorm_mode + * based on given color depth. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - Corresponding OPP to update register. + * - [in] output_depth - Arbitrary color depth to set denorm_mode. + * + * Return: + * + * void + */ void (*set_denorm)(struct mpc *mpc, int opp_id, enum dc_color_depth output_depth); + /** + * @set_denorm_clamp: + * + * Set denorm clamp values on corresponding OPP DENORM CONTROL register. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - Corresponding OPP to update register. + * - [in] denorm_clamp - Arbitrary denorm clamp to be set. + * + * Return: + * + * void + */ void (*set_denorm_clamp)( struct mpc *mpc, int opp_id, struct mpc_denorm_clamp denorm_clamp); + /** + * @set_output_csc: + * + * Set the Output Color Space Conversion matrix + * with given values and mode. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - Corresponding OPP to update register. + * - [in] regval - Values to set in CSC matrix. + * - [in] ocsc_mode - Mode to set CSC. + * + * Return: + * + * void + */ void (*set_output_csc)(struct mpc *mpc, int opp_id, const uint16_t *regval, enum mpc_output_csc_mode ocsc_mode); + /** + * @set_ocsc_default: + * + * Set the Output Color Space Conversion matrix + * to default values according to color space. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - Corresponding OPP to update register. + * - [in] color_space - OCSC color space. + * - [in] ocsc_mode - Mode to set CSC. + * + * Return: + * + * void + * + */ void (*set_ocsc_default)(struct mpc *mpc, int opp_id, enum dc_color_space color_space, enum mpc_output_csc_mode ocsc_mode); + /** + * @set_output_gamma: + * + * Set Output Gamma with given curve parameters. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id - Corresponding MPC to update registers. + * - [in] params - Parameters. + * + * Return: + * + * void + * + */ void (*set_output_gamma)( struct mpc *mpc, int mpcc_id, const struct pwl_params *params); + /** + * @power_on_mpc_mem_pwr: + * + * Power on/off memory LUT for given MPCC. + * Powering on enables LUT to be updated. + * Powering off allows entering low power mode. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id - MPCC to power on. + * - [in] power_on + * + * Return: + * + * void + */ void (*power_on_mpc_mem_pwr)( struct mpc *mpc, int mpcc_id, bool power_on); + /** + * @set_dwb_mux: + * + * Set corresponding Display Writeback mux + * MPC register field to given MPCC id. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] dwb_id - DWB to be set. + * - [in] mpcc_id - MPCC id to be stored in DWB mux register. + * + * Return: + * + * void + */ void (*set_dwb_mux)( struct mpc *mpc, int dwb_id, int mpcc_id); + /** + * @disable_dwb_mux: + * + * Reset corresponding Display Writeback mux + * MPC register field. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] dwb_id - DWB to be set. + * + * Return: + * + * void + */ void (*disable_dwb_mux)( struct mpc *mpc, int dwb_id); + /** + * @is_dwb_idle: + * + * Check DWB status on MPC_DWB0_MUX_STATUS register field. + * Return if it is null. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] dwb_id - DWB to be checked. + * + * Return: + * + * bool - wheter DWB is idle or not + */ bool (*is_dwb_idle)( struct mpc *mpc, int dwb_id); + /** + * @set_out_rate_control: + * + * Set display output rate control. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] opp_id - OPP to be set. + * - [in] enable + * - [in] rate_2x_mode + * - [in] flow_control + * + * Return: + * + * void + */ void (*set_out_rate_control)( struct mpc *mpc, int opp_id, @@ -512,38 +782,264 @@ struct mpc_funcs { bool rate_2x_mode, struct mpc_dwb_flow_control *flow_control); + /** + * @set_gamut_remap: + * + * Set post-blending CTM for given MPCC. + * + * Parameters: + * - [in] mpc - MPC context. + * - [in] mpcc_id - MPCC to set gamut map. + * - [in] adjust + * + * Return: + * + * void + */ void (*set_gamut_remap)( struct mpc *mpc, int mpcc_id, const struct mpc_grph_gamut_adjustment *adjust); + /** + * @program_1dlut: + * + * Set 1 dimensional Lookup Table. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] params - curve parameters for the LUT configuration + * - [in] rmu_idx + * + * bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). + */ bool (*program_1dlut)( struct mpc *mpc, const struct pwl_params *params, uint32_t rmu_idx); + /** + * @program_shaper: + * + * Set shaper. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] params - curve parameters to be set + * - [in] rmu_idx + * + * Return: + * + * bool - wheter shaper was set (set with given parameters) or not (params is NULL and LUT is disabled). + */ bool (*program_shaper)( struct mpc *mpc, const struct pwl_params *params, uint32_t rmu_idx); + /** + * @acquire_rmu: + * + * Set given MPCC to be multiplexed to given RMU unit. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] mpcc_id - MPCC + * - [in] rmu_idx - Given RMU unit to set MPCC to be multiplexed to. + * + * Return: + * + * unit32_t - rmu_idx if operation was successful, -1 else. + */ uint32_t (*acquire_rmu)(struct mpc *mpc, int mpcc_id, int rmu_idx); + /** + * @program_3dlut: + * + * Set 3 dimensional Lookup Table. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] params - tetrahedral parameters for the LUT configuration + * - [in] rmu_idx + * + * bool - wheter LUT was set (set with given parameters) or not (params is NULL and LUT is disabled). + */ bool (*program_3dlut)( struct mpc *mpc, const struct tetrahedral_params *params, int rmu_idx); + /** + * @release_rmu: + * + * For a given MPCC, release the RMU unit it muliplexes to. + * + * Parameters: + * - [in/out] mpc - MPC context + * - [in] mpcc_id - MPCC + * + * Return: + * + * int - a valid rmu_idx representing released RMU unit or -1 if there was no RMU unit to release. + */ int (*release_rmu)(struct mpc *mpc, int mpcc_id); + /** + * @get_mpc_out_mux: + * + * Return MPC out mux. + * + * Parameters: + * - [in] mpc - MPC context. + * - [in] opp_id - OPP + * + * Return: + * + * unsigned int - Out Mux + */ unsigned int (*get_mpc_out_mux)( - struct mpc *mpc, - int opp_id); + struct mpc *mpc, + int opp_id); + /** + * @set_bg_color: + * + * Find corresponding bottommost MPCC and + * set its bg color. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] bg_color - background color to be set. + * - [in] mpcc_id + * + * Return: + * + * void + */ void (*set_bg_color)(struct mpc *mpc, struct tg_color *bg_color, int mpcc_id); + + /** + * @set_mpc_mem_lp_mode: + * + * Set mpc_mem_lp_mode. + * + * Parameters: + * - [in/out] mpc - MPC context. + * + * Return: + * + * void + */ + void (*set_mpc_mem_lp_mode)(struct mpc *mpc); + /** + * @set_movable_cm_location: + * + * Set Movable CM Location. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] location + * - [in] mpcc_id + * + * Return: + * + * void + */ + + void (*set_movable_cm_location)(struct mpc *mpc, enum mpcc_movable_cm_location location, int mpcc_id); + /** + * @update_3dlut_fast_load_select: + * + * Update 3D LUT fast load select. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id + * - [in] hubp_idx + * + * Return: + * + * void + */ + + void (*update_3dlut_fast_load_select)(struct mpc *mpc, int mpcc_id, int hubp_idx); + /** + * @get_3dlut_fast_load_status: + * + * Get 3D LUT fast load status and reference them with done, soft_underflow and hard_underflow pointers. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] mpcc_id + * - [in/out] done + * - [in/out] soft_underflow + * - [in/out] hard_underflow + * + * Return: + * + * void + */ + void (*get_3dlut_fast_load_status)(struct mpc *mpc, int mpcc_id, uint32_t *done, uint32_t *soft_underflow, uint32_t *hard_underflow); + + /** + * @populate_lut: + * + * Populate LUT with given tetrahedral parameters. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id + * - [in] params + * - [in] lut_bank_a + * - [in] mpcc_id + * + * Return: + * + * void + */ + void (*populate_lut)(struct mpc *mpc, const enum MCM_LUT_ID id, const union mcm_lut_params params, + bool lut_bank_a, int mpcc_id); + + /** + * @program_lut_read_write_control: + * + * Program LUT RW control. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id + * - [in] lut_bank_a + * - [in] mpcc_id + * + * Return: + * + * void + */ + void (*program_lut_read_write_control)(struct mpc *mpc, const enum MCM_LUT_ID id, bool lut_bank_a, int mpcc_id); + + /** + * @program_lut_mode: + * + * Program LUT mode. + * + * Parameters: + * - [in/out] mpc - MPC context. + * - [in] id + * - [in] xable + * - [in] lut_bank_a + * - [in] mpcc_id + * + * Return: + * + * void + */ + void (*program_lut_mode)(struct mpc *mpc, const enum MCM_LUT_ID id, const enum MCM_LUT_XABLE xable, + bool lut_bank_a, int mpcc_id); + void (*program_3dlut_size)(struct mpc *mpc, bool is_17x17x17, int mpcc_id); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h index d89c92370d5b..127fb1a51654 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/opp.h @@ -346,8 +346,13 @@ struct opp_funcs { void (*opp_program_left_edge_extra_pixel)( struct output_pixel_processor *opp, - bool count); + enum dc_pixel_encoding pixel_encoding, + bool is_primary); + uint32_t (*opp_get_left_edge_extra_pixel_count)( + struct output_pixel_processor *opp, + enum dc_pixel_encoding pixel_encoding, + bool is_primary); }; #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h index 8d32e525f05a..287bf8a90ff6 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/optc.h @@ -212,10 +212,10 @@ bool optc1_get_crc(struct timing_generator *optc, uint32_t *g_y, uint32_t *b_cb); -bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); - void optc1_set_vtg_params(struct timing_generator *optc, const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); +bool optc1_is_two_pixels_per_container(const struct dc_crtc_timing *timing); + #endif diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h index 75b9ec21f297..e5e11c84e9e2 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/stream_encoder.h @@ -99,6 +99,7 @@ struct encoder_unblank_param { struct dc_link_settings link_settings; struct dc_crtc_timing timing; int opp_cnt; + uint32_t pix_per_cycle; }; struct encoder_set_dp_phy_pattern_param { @@ -222,7 +223,7 @@ struct stream_encoder_funcs { struct stream_encoder *enc, int tg_inst); - void (*dig_stream_enable)( + void (*enable_stream)( struct stream_encoder *enc, enum signal_type signal, bool enable); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h index cd68ecc242c1..cd4826f329c1 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/timing_generator.h @@ -276,6 +276,7 @@ struct timing_generator_funcs { uint32_t *num_of_input_segments, uint32_t *seg0_src_sel, uint32_t *seg1_src_sel); + bool (*is_two_pixels_per_container)(const struct dc_crtc_timing *timing); /** * Configure CRCs for the given timing generator. Return false if TG is @@ -312,7 +313,7 @@ struct timing_generator_funcs { * OPP(s) and turn on/off ODM memory. */ void (*set_odm_combine)(struct timing_generator *optc, int *opp_id, int opp_cnt, - struct dc_crtc_timing *timing); + int segment_width, int last_segment_width); void (*get_odm_combine_segments)(struct timing_generator *tg, int *odm_segments); void (*set_h_timing_div_manual_mode)(struct timing_generator *optc, bool manual_mode); void (*set_gsl)(struct timing_generator *optc, const struct gsl_params *params); diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h index 9ac9d5e8df8b..28da1dddf0a0 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h +++ b/drivers/gpu/drm/amd/display/dc/inc/hw/transform.h @@ -29,6 +29,7 @@ #include "hw_shared.h" #include "dc_hw_types.h" #include "fixed31_32.h" +#include "spl/dc_spl_types.h" #define CSC_TEMPERATURE_MATRIX_SIZE 12 @@ -110,22 +111,6 @@ enum graphics_gamut_adjust_type { GRAPHICS_GAMUT_ADJUST_TYPE_SW /* use adjustments */ }; -enum lb_memory_config { - /* Enable all 3 pieces of memory */ - LB_MEMORY_CONFIG_0 = 0, - - /* Enable only the first piece of memory */ - LB_MEMORY_CONFIG_1 = 1, - - /* Enable only the second piece of memory */ - LB_MEMORY_CONFIG_2 = 2, - - /* Only applicable in 4:2:0 mode, enable all 3 pieces of memory and the - * last piece of chroma memory used for the luma storage - */ - LB_MEMORY_CONFIG_3 = 3 -}; - struct xfm_grph_csc_adjustment { struct fixed31_32 temperature_matrix[CSC_TEMPERATURE_MATRIX_SIZE]; enum graphics_gamut_adjust_type gamut_adjust_type; @@ -177,6 +162,8 @@ struct scaler_data { struct sharpness_adj sharpness; enum pixel_format format; struct line_buffer_params lb_params; + // Below struct holds the scaler values to program hw registers + struct dscl_prog_data dscl_prog_data; }; struct transform_funcs { @@ -259,6 +246,15 @@ struct transform_funcs { struct transform *xfm_base, const struct dc_cursor_attributes *attr); + bool (*transform_program_blnd_lut)( + struct transform *xfm, + const struct pwl_params *params); + bool (*transform_program_shaper_lut)( + struct transform *xfm, + const struct pwl_params *params); + bool (*transform_program_3dlut)( + struct transform *xfm, + struct tetrahedral_params *params); }; const uint16_t *get_filter_2tap_16p(void); diff --git a/drivers/gpu/drm/amd/display/dc/inc/resource.h b/drivers/gpu/drm/amd/display/dc/inc/resource.h index 361ad6b16b96..96d40d33a1f9 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/resource.h +++ b/drivers/gpu/drm/amd/display/dc/inc/resource.h @@ -29,6 +29,7 @@ #include "core_status.h" #include "dal_asic_id.h" #include "dm_pp_smu.h" +#include "spl/dc_spl.h" #define MEMORY_TYPE_MULTIPLIER_CZ 4 #define MEMORY_TYPE_HBM 2 @@ -77,11 +78,9 @@ struct resource_create_funcs { struct hpo_dp_stream_encoder *(*create_hpo_dp_stream_encoder)( enum engine_id eng_id, struct dc_context *ctx); - struct hpo_dp_link_encoder *(*create_hpo_dp_link_encoder)( uint8_t inst, struct dc_context *ctx); - struct dce_hwseq *(*create_hwseq)( struct dc_context *ctx); }; @@ -443,6 +442,16 @@ int resource_get_odm_slice_count(const struct pipe_ctx *pipe); /* Get the ODM slice index counting from 0 from left most slice */ int resource_get_odm_slice_index(const struct pipe_ctx *opp_head); +/* Get ODM slice source rect in timing active as input to OPP block */ +struct rect resource_get_odm_slice_src_rect(struct pipe_ctx *pipe_ctx); + +/* Get ODM slice destination rect in timing active as output from OPP block */ +struct rect resource_get_odm_slice_dst_rect(struct pipe_ctx *pipe_ctx); + +/* Get ODM slice destination width in timing active as output from OPP block */ +int resource_get_odm_slice_dst_width(struct pipe_ctx *otg_master, + bool is_last_segment); + /* determine if pipe topology is changed between state a and state b */ bool resource_is_pipe_topology_changed(const struct dc_state *state_a, const struct dc_state *state_b); @@ -620,6 +629,11 @@ enum dc_status update_dp_encoder_resources_for_test_harness(const struct dc *dc, bool check_subvp_sw_cursor_fallback_req(const struct dc *dc, struct dc_stream_state *stream); +/* Get hw programming parameters container from pipe context + * @pipe_ctx: pipe context + * @dscl_prog_data: struct to hold programmable hw reg values + */ +struct dscl_prog_data *resource_get_dscl_prog_data(struct pipe_ctx *pipe_ctx); /* Setup dc callbacks for dml2 * @dc: the display core structure * @dml2_options: struct to hold callbacks |