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path: root/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
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Diffstat (limited to 'drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h')
-rw-r--r--drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h25
1 files changed, 23 insertions, 2 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
index a8a0e8cb1a11..0b31779a0485 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h
@@ -336,6 +336,13 @@ struct amdgpu_display_manager {
*/
const struct gpu_info_soc_bounding_box_v1_0 *soc_bounding_box;
+#ifdef CONFIG_DEBUG_FS
+ /* set the crc calculation window*/
+ struct drm_property *crc_win_x_start_property;
+ struct drm_property *crc_win_y_start_property;
+ struct drm_property *crc_win_x_end_property;
+ struct drm_property *crc_win_y_end_property;
+#endif
/**
* @mst_encoders:
*
@@ -420,10 +427,17 @@ struct dc_plane_state;
struct dm_plane_state {
struct drm_plane_state base;
struct dc_plane_state *dc_state;
- uint64_t tiling_flags;
- bool tmz_surface;
};
+#ifdef CONFIG_DEBUG_FS
+struct crc_rec {
+ uint16_t x_start;
+ uint16_t y_start;
+ uint16_t x_end;
+ uint16_t y_end;
+ };
+#endif
+
struct dm_crtc_state {
struct drm_crtc_state base;
struct dc_stream_state *stream;
@@ -440,11 +454,15 @@ struct dm_crtc_state {
bool freesync_timing_changed;
bool freesync_vrr_info_changed;
+ bool dsc_force_changed;
bool vrr_supported;
struct mod_freesync_config freesync_config;
struct dc_info_packet vrr_infopacket;
int abm_level;
+#ifdef CONFIG_DEBUG_FS
+ struct crc_rec crc_window;
+#endif
};
#define to_dm_crtc_state(x) container_of(x, struct dm_crtc_state, base)
@@ -465,6 +483,9 @@ struct dm_connector_state {
uint8_t underscan_hborder;
bool underscan_enable;
bool freesync_capable;
+#ifdef CONFIG_DRM_AMD_DC_HDCP
+ bool update_hdcp;
+#endif
uint8_t abm_level;
int vcpi_slots;
uint64_t pbn;