diff options
Diffstat (limited to 'drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c')
| -rw-r--r-- | drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c | 22 | 
1 files changed, 16 insertions, 6 deletions
| diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c index f92c158d89a1..0e0daf0021b6 100644 --- a/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c @@ -4273,7 +4273,7 @@ static int gfx_v10_0_update_gfx_clock_gating(struct amdgpu_device *adev,  		/* ===  CGCG /CGLS for GFX 3D Only === */  		gfx_v10_0_update_3d_clock_gating(adev, enable);  		/* ===  MGCG + MGLS === */ -		/* gfx_v10_0_update_medium_grain_clock_gating(adev, enable); */ +		gfx_v10_0_update_medium_grain_clock_gating(adev, enable);  	}  	if (adev->cg_flags & @@ -4353,11 +4353,7 @@ static int gfx_v10_0_set_powergating_state(void *handle,  	switch (adev->asic_type) {  	case CHIP_NAVI10:  	case CHIP_NAVI14: -		if (!enable) { -			amdgpu_gfx_off_ctrl(adev, false); -			cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work); -		} else -			amdgpu_gfx_off_ctrl(adev, true); +		amdgpu_gfx_off_ctrl(adev, enable);  		break;  	default:  		break; @@ -4918,6 +4914,19 @@ static void gfx_v10_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,  							   ref, mask);  } +static void gfx_v10_0_ring_soft_recovery(struct amdgpu_ring *ring, +					 unsigned vmid) +{ +	struct amdgpu_device *adev = ring->adev; +	uint32_t value = 0; + +	value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03); +	value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01); +	value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1); +	value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid); +	WREG32_SOC15(GC, 0, mmSQ_CMD, value); +} +  static void  gfx_v10_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,  				      uint32_t me, uint32_t pipe, @@ -5309,6 +5318,7 @@ static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_gfx = {  	.emit_wreg = gfx_v10_0_ring_emit_wreg,  	.emit_reg_wait = gfx_v10_0_ring_emit_reg_wait,  	.emit_reg_write_reg_wait = gfx_v10_0_ring_emit_reg_write_reg_wait, +	.soft_recovery = gfx_v10_0_ring_soft_recovery,  };  static const struct amdgpu_ring_funcs gfx_v10_0_ring_funcs_compute = { |