diff options
Diffstat (limited to 'arch/arm64/boot/dts/qcom/sc8280xp.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 187 |
1 files changed, 182 insertions, 5 deletions
diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi index d0f82e12289e..0549ba1fbeea 100644 --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi @@ -50,7 +50,8 @@ reg = <0x0 0x0>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_0>; power-domains = <&CPU_PD0>; power-domain-names = "psci"; @@ -77,7 +78,8 @@ reg = <0x0 0x100>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_100>; power-domains = <&CPU_PD1>; power-domain-names = "psci"; @@ -99,7 +101,8 @@ reg = <0x0 0x200>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_200>; power-domains = <&CPU_PD2>; power-domain-names = "psci"; @@ -121,7 +124,8 @@ reg = <0x0 0x300>; clocks = <&cpufreq_hw 0>; enable-method = "psci"; - capacity-dmips-mhz = <602>; + capacity-dmips-mhz = <981>; + dynamic-power-coefficient = <549>; next-level-cache = <&L2_300>; power-domains = <&CPU_PD3>; power-domain-names = "psci"; @@ -144,6 +148,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_400>; power-domains = <&CPU_PD4>; power-domain-names = "psci"; @@ -166,6 +171,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_500>; power-domains = <&CPU_PD5>; power-domain-names = "psci"; @@ -188,6 +194,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_600>; power-domains = <&CPU_PD6>; power-domain-names = "psci"; @@ -210,6 +217,7 @@ clocks = <&cpufreq_hw 1>; enable-method = "psci"; capacity-dmips-mhz = <1024>; + dynamic-power-coefficient = <590>; next-level-cache = <&L2_700>; power-domains = <&CPU_PD7>; power-domain-names = "psci"; @@ -300,6 +308,7 @@ scm: scm { compatible = "qcom,scm-sc8280xp", "qcom,scm"; interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; + qcom,dload-mode = <&tcsr 0x13000>; }; }; @@ -862,6 +871,18 @@ #mbox-cells = <2>; }; + qfprom: efuse@784000 { + compatible = "qcom,sc8280xp-qfprom", "qcom,qfprom"; + reg = <0 0x00784000 0 0x3000>; + #address-cells = <1>; + #size-cells = <1>; + + gpu_speed_bin: gpu-speed-bin@18b { + reg = <0x18b 0x1>; + bits = <5 3>; + }; + }; + qup2: geniqup@8c0000 { compatible = "qcom,geni-se-qup"; reg = <0 0x008c0000 0 0x2000>; @@ -1731,6 +1752,8 @@ linux,pci-domain = <6>; num-lanes = <1>; + msi-map = <0x0 &its 0xe0000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, @@ -1780,6 +1803,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie4_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie4_phy: phy@1c06000 { @@ -1832,6 +1865,8 @@ linux,pci-domain = <5>; num-lanes = <2>; + msi-map = <0x0 &its 0xd0000 0x10000>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, @@ -1879,6 +1914,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie3b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3b_phy: phy@1c0e000 { @@ -1931,6 +1976,8 @@ linux,pci-domain = <4>; num-lanes = <4>; + msi-map = <0x0 &its 0xc0000 0x10000>; + interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, @@ -1978,6 +2025,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie3a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie3a_phy: phy@1c14000 { @@ -2033,6 +2090,8 @@ linux,pci-domain = <3>; num-lanes = <2>; + msi-map = <0x0 &its 0xb0000 0x10000>; + interrupts = <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, @@ -2080,6 +2139,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie2b_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2b_phy: phy@1c1e000 { @@ -2132,6 +2201,8 @@ linux,pci-domain = <2>; num-lanes = <4>; + msi-map = <0x0 &its 0xa0000 0x10000>; + interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, @@ -2179,6 +2250,16 @@ phy-names = "pciephy"; status = "disabled"; + + pcie2a_port0: pcie@0 { + device_type = "pci"; + reg = <0x0 0x0 0x0 0x0 0x0>; + bus-range = <0x01 0xff>; + + #address-cells = <3>; + #size-cells = <2>; + ranges; + }; }; pcie2a_phy: phy@1c24000 { @@ -3342,6 +3423,88 @@ interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; }; + usb_2: usb@a4f8800 { + compatible = "qcom,sc8280xp-dwc3-mp", "qcom,dwc3"; + reg = <0 0x0a4f8800 0 0x400>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + clocks = <&gcc GCC_CFG_NOC_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_MP_AXI_CLK>, + <&gcc GCC_USB30_MP_SLEEP_CLK>, + <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_NORTH_AXI_CLK>, + <&gcc GCC_AGGRE_USB_NOC_SOUTH_AXI_CLK>, + <&gcc GCC_SYS_NOC_USB_AXI_CLK>; + clock-names = "cfg_noc", "core", "iface", "sleep", "mock_utmi", + "noc_aggr", "noc_aggr_north", "noc_aggr_south", "noc_sys"; + + assigned-clocks = <&gcc GCC_USB30_MP_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_MP_MASTER_CLK>; + assigned-clock-rates = <19200000>, <200000000>; + + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 127 IRQ_TYPE_EDGE_BOTH>, + <&pdc 126 IRQ_TYPE_EDGE_BOTH>, + <&pdc 129 IRQ_TYPE_EDGE_BOTH>, + <&pdc 128 IRQ_TYPE_EDGE_BOTH>, + <&pdc 131 IRQ_TYPE_EDGE_BOTH>, + <&pdc 130 IRQ_TYPE_EDGE_BOTH>, + <&pdc 133 IRQ_TYPE_EDGE_BOTH>, + <&pdc 132 IRQ_TYPE_EDGE_BOTH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; + + interrupt-names = "pwr_event_1", "pwr_event_2", + "pwr_event_3", "pwr_event_4", + "hs_phy_1", "hs_phy_2", + "hs_phy_3", "hs_phy_4", + "dp_hs_phy_1", "dm_hs_phy_1", + "dp_hs_phy_2", "dm_hs_phy_2", + "dp_hs_phy_3", "dm_hs_phy_3", + "dp_hs_phy_4", "dm_hs_phy_4", + "ss_phy_1", "ss_phy_2"; + + power-domains = <&gcc USB30_MP_GDSC>; + required-opps = <&rpmhpd_opp_nom>; + + resets = <&gcc GCC_USB30_MP_BCR>; + + interconnects = <&aggre1_noc MASTER_USB3_MP 0 &mc_virt SLAVE_EBI1 0>, + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_USB3_MP 0>; + interconnect-names = "usb-ddr", "apps-usb"; + + wakeup-source; + + status = "disabled"; + + usb_2_dwc3: usb@a400000 { + compatible = "snps,dwc3"; + reg = <0 0x0a400000 0 0xcd00>; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x800 0x0>; + phys = <&usb_2_hsphy0>, <&usb_2_qmpphy0>, + <&usb_2_hsphy1>, <&usb_2_qmpphy1>, + <&usb_2_hsphy2>, + <&usb_2_hsphy3>; + phy-names = "usb2-0", "usb3-0", + "usb2-1", "usb3-1", + "usb2-2", + "usb2-3"; + dr_mode = "host"; + }; + }; + usb_0: usb@a6f8800 { compatible = "qcom,sc8280xp-dwc3", "qcom,dwc3"; reg = <0 0x0a6f8800 0 0x400>; @@ -3366,10 +3529,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 804 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 805 IRQ_TYPE_LEVEL_HIGH>, <&pdc 14 IRQ_TYPE_EDGE_BOTH>, <&pdc 15 IRQ_TYPE_EDGE_BOTH>, <&pdc 138 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -3426,10 +3591,12 @@ assigned-clock-rates = <19200000>, <200000000>; interrupts-extended = <&intc GIC_SPI 811 IRQ_TYPE_LEVEL_HIGH>, + <&intc GIC_SPI 790 IRQ_TYPE_LEVEL_HIGH>, <&pdc 12 IRQ_TYPE_EDGE_BOTH>, <&pdc 13 IRQ_TYPE_EDGE_BOTH>, <&pdc 136 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "pwr_event", + "hs_phy_irq", "dp_hs_phy_irq", "dm_hs_phy_irq", "ss_phy_irq"; @@ -4453,6 +4620,11 @@ #thermal-sensor-cells = <1>; }; + restart@c264000 { + compatible = "qcom,pshold"; + reg = <0 0x0c264000 0 0x4>; + }; + tsens1: thermal-sensor@c265000 { compatible = "qcom,sc8280xp-tsens", "qcom,tsens-v2"; reg = <0 0x0c265000 0 0x1ff>, /* TM */ @@ -4804,7 +4976,7 @@ #size-cells = <2>; ranges; - msi-controller@17a40000 { + its: msi-controller@17a40000 { compatible = "arm,gic-v3-its"; reg = <0 0x17a40000 0 0x20000>; msi-controller; @@ -4971,6 +5143,11 @@ <0 0x18592000 0 0x1000>; reg-names = "freq-domain0", "freq-domain1"; + interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "dcvsh-irq-0", + "dcvsh-irq-1"; + clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; clock-names = "xo", "alternate"; |