diff options
Diffstat (limited to 'arch/arm64/boot/dts/freescale')
132 files changed, 7648 insertions, 854 deletions
diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile index c6872b7e9471..2e027675d7bb 100644 --- a/arch/arm64/boot/dts/freescale/Makefile +++ b/arch/arm64/boot/dts/freescale/Makefile @@ -15,12 +15,15 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1043a-tqmls1043a-mbls10xxa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-frwy.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1046a-tqmls1046a-mbls10xxa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-ten64.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1088a-tqmls1088a-mbls10xxa.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2080a-rdb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls2081a-rdb.dtb @@ -33,6 +36,7 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-clearfog-cx.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-honeycomb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-qds.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-rdb.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-clearfog.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2162a-qds.dtb fsl-ls1028a-qds-13bb-dtbs := fsl-ls1028a-qds.dtb fsl-ls1028a-qds-13bb.dtbo @@ -49,6 +53,32 @@ dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-85bb.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-899b.dtb dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-ls1028a-qds-9999.dtb +fsl-lx2160a-tqmlx2160a-mblx2160a-12-11-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \ + fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtbo \ + fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtbo +fsl-lx2160a-tqmlx2160a-mblx2160a-12-7-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \ + fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtbo \ + fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtbo +fsl-lx2160a-tqmlx2160a-mblx2160a-12-8-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \ + fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtbo \ + fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtbo +fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \ + fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtbo \ + fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtbo +fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \ + fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtbo \ + fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtbo +fsl-lx2160a-tqmlx2160a-mblx2160a-14-11-x-dtbs := fsl-lx2160a-tqmlx2160a-mblx2160a.dtb \ + fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtbo \ + fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtbo + +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-12-11-x.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-12-8-x.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-12-7-x.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-11-x.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-8-x.dtb +dtb-$(CONFIG_ARCH_LAYERSCAPE) += fsl-lx2160a-tqmlx2160a-mblx2160a-14-7-x.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8dxl-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-data-modul-edm-sbc.dtb @@ -66,6 +96,8 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-mx8menlo.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-nitrogen-r2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phg.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-phyboard-polis-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-phygate-tauri-l.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-prt8mm.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb @@ -78,19 +110,31 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7904.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw7905-0x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-verdin-wifi-yavia.dtb + +imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33-dtbs += imx8mm-tqma8mqml-mba8mx.dtb imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mn-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-bsh-smm-s2pro.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-dimonoff-gateway-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr3l-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mn-rve-gateway.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mn-venice-gw7902.dtb + +imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33-dtbs += imx8mn-tqma8mqnl-mba8mx.dtb imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8mp-beacon-kit.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-data-modul-edm-sbc.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-debix-model-a.dtb @@ -101,6 +145,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-icore-mx8mp-edimm2.2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-msc-sm2s-ep1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-phyboard-pollux-rdk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-hdmi.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-lt6.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-skov-revb-mi1010ait-1cp1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw71xx-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw72xx-2x.dtb @@ -109,13 +156,17 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw7905-2x.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-nonwifi-yavia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dahlia.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-dev.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-mallow.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-verdin-wifi-yavia.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds.dtbo +imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01-dtbs += imx8mp-tqma8mpql-mba8mpxl.dtb imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-hummingboard-pulse.dtb @@ -132,6 +183,10 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mq-pico-pi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-thor96.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-rmb3.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mq-zii-ultra-zest.dtb + +imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33-dtbs += imx8mq-tqma8mq-mba8mx.dtb imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtbo +dtb-$(CONFIG_ARCH_MXC) += imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtb + dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-eval.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-ixora-v1.1.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qm-apalis-v1.1-eval.dtb @@ -146,6 +201,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8qxp-colibri-iris-v2.dtb dtb-$(CONFIG_ARCH_MXC) += imx8qxp-mek.dtb dtb-$(CONFIG_ARCH_MXC) += imx8ulp-evk.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-11x11-evk.dtb +dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxca.dtb dtb-$(CONFIG_ARCH_MXC) += imx93-tqma9352-mba93xxla.dtb imx8mm-venice-gw72xx-0x-imx219-dtbs := imx8mm-venice-gw72xx-0x.dtb imx8mm-venice-gw72xx-0x-imx219.dtbo @@ -158,6 +214,7 @@ imx8mm-venice-gw73xx-0x-rpidsi-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice imx8mm-venice-gw73xx-0x-rs232-rts-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs232-rts.dtbo imx8mm-venice-gw73xx-0x-rs422-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs422.dtbo imx8mm-venice-gw73xx-0x-rs485-dtbs := imx8mm-venice-gw73xx-0x.dtb imx8mm-venice-gw73xx-0x-rs485.dtbo +imx8mp-venice-gw74xx-imx219-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-imx219.dtbo imx8mp-venice-gw74xx-rpidsi-dtbs := imx8mp-venice-gw74xx.dtb imx8mp-venice-gw74xx-rpidsi.dtbo dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x-imx219.dtb @@ -170,6 +227,7 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rpidsi.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs232-rts.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs422.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x-rs485.dtb +dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-imx219.dtb dtb-$(CONFIG_ARCH_MXC) += imx8mp-venice-gw74xx-rpidsi.dtb dtb-$(CONFIG_ARCH_S32) += s32g274a-evb.dtb diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi index a863022529ac..1e3fe3897b52 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi @@ -307,46 +307,46 @@ reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x60062>; - fsl,tmu-calibration = <0x00000000 0x00000025 - 0x00000001 0x0000002c - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004c - 0x00000007 0x00000053 - 0x00000008 0x00000059 - 0x00000009 0x0000005f - 0x0000000a 0x00000066 - 0x0000000b 0x0000006c - - 0x00010000 0x00000026 - 0x00010001 0x0000002d - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004d - 0x00010006 0x00000055 - 0x00010007 0x0000005d - 0x00010008 0x00000065 - 0x00010009 0x0000006d - - 0x00020000 0x00000026 - 0x00020001 0x00000030 - 0x00020002 0x0000003a - 0x00020003 0x00000044 - 0x00020004 0x0000004e - 0x00020005 0x00000059 - 0x00020006 0x00000063 - - 0x00030000 0x00000014 - 0x00030001 0x00000021 - 0x00030002 0x0000002e - 0x00030003 0x0000003a - 0x00030004 0x00000047 - 0x00030005 0x00000053 - 0x00030006 0x00000060>; - big-endian; + fsl,tmu-calibration = + <0x00000000 0x00000025>, + <0x00000001 0x0000002c>, + <0x00000002 0x00000032>, + <0x00000003 0x00000039>, + <0x00000004 0x0000003f>, + <0x00000005 0x00000046>, + <0x00000006 0x0000004c>, + <0x00000007 0x00000053>, + <0x00000008 0x00000059>, + <0x00000009 0x0000005f>, + <0x0000000a 0x00000066>, + <0x0000000b 0x0000006c>, + + <0x00010000 0x00000026>, + <0x00010001 0x0000002d>, + <0x00010002 0x00000035>, + <0x00010003 0x0000003d>, + <0x00010004 0x00000045>, + <0x00010005 0x0000004d>, + <0x00010006 0x00000055>, + <0x00010007 0x0000005d>, + <0x00010008 0x00000065>, + <0x00010009 0x0000006d>, + + <0x00020000 0x00000026>, + <0x00020001 0x00000030>, + <0x00020002 0x0000003a>, + <0x00020003 0x00000044>, + <0x00020004 0x0000004e>, + <0x00020005 0x00000059>, + <0x00020006 0x00000063>, + + <0x00030000 0x00000014>, + <0x00030001 0x00000021>, + <0x00030002 0x0000002e>, + <0x00030003 0x0000003a>, + <0x00030004 0x00000047>, + <0x00030005 0x00000053>, + <0x00030006 0x00000060>; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi index eefe3577d94e..ae534c23b970 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi @@ -1026,49 +1026,50 @@ reg = <0x0 0x1f80000 0x0 0x10000>; interrupts = <0 23 0x4>; fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; - fsl,tmu-calibration = <0x00000000 0x00000024 - 0x00000001 0x0000002b - 0x00000002 0x00000031 - 0x00000003 0x00000038 - 0x00000004 0x0000003f - 0x00000005 0x00000045 - 0x00000006 0x0000004c - 0x00000007 0x00000053 - 0x00000008 0x00000059 - 0x00000009 0x00000060 - 0x0000000a 0x00000066 - 0x0000000b 0x0000006d - - 0x00010000 0x0000001c - 0x00010001 0x00000024 - 0x00010002 0x0000002c - 0x00010003 0x00000035 - 0x00010004 0x0000003d - 0x00010005 0x00000045 - 0x00010006 0x0000004d - 0x00010007 0x00000055 - 0x00010008 0x0000005e - 0x00010009 0x00000066 - 0x0001000a 0x0000006e - - 0x00020000 0x00000018 - 0x00020001 0x00000022 - 0x00020002 0x0000002d - 0x00020003 0x00000038 - 0x00020004 0x00000043 - 0x00020005 0x0000004d - 0x00020006 0x00000058 - 0x00020007 0x00000063 - 0x00020008 0x0000006e - - 0x00030000 0x00000010 - 0x00030001 0x0000001c - 0x00030002 0x00000029 - 0x00030003 0x00000036 - 0x00030004 0x00000042 - 0x00030005 0x0000004f - 0x00030006 0x0000005b - 0x00030007 0x00000068>; + fsl,tmu-calibration = + <0x00000000 0x00000024>, + <0x00000001 0x0000002b>, + <0x00000002 0x00000031>, + <0x00000003 0x00000038>, + <0x00000004 0x0000003f>, + <0x00000005 0x00000045>, + <0x00000006 0x0000004c>, + <0x00000007 0x00000053>, + <0x00000008 0x00000059>, + <0x00000009 0x00000060>, + <0x0000000a 0x00000066>, + <0x0000000b 0x0000006d>, + + <0x00010000 0x0000001c>, + <0x00010001 0x00000024>, + <0x00010002 0x0000002c>, + <0x00010003 0x00000035>, + <0x00010004 0x0000003d>, + <0x00010005 0x00000045>, + <0x00010006 0x0000004d>, + <0x00010007 0x00000055>, + <0x00010008 0x0000005e>, + <0x00010009 0x00000066>, + <0x0001000a 0x0000006e>, + + <0x00020000 0x00000018>, + <0x00020001 0x00000022>, + <0x00020002 0x0000002d>, + <0x00020003 0x00000038>, + <0x00020004 0x00000043>, + <0x00020005 0x0000004d>, + <0x00020006 0x00000058>, + <0x00020007 0x00000063>, + <0x00020008 0x0000006e>, + + <0x00030000 0x00000010>, + <0x00030001 0x0000001c>, + <0x00030002 0x00000029>, + <0x00030003 0x00000036>, + <0x00030004 0x00000042>, + <0x00030005 0x0000004f>, + <0x00030006 0x0000005b>, + <0x00030007 0x00000068>; little-endian; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts new file mode 100644 index 000000000000..03748a7f657b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a-mbls10xxa.dts @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> + +#include "fsl-ls1043a-tqmls1043a.dtsi" +#include "tqmls10xxa-mbls10xxa.dtsi" + +/ { + model = "TQ-Systems GmbH LS1043A TQMLS1043A SoM on MBLS10xxA board"; + compatible = "tq,ls1043a-tqmls1043a-mbls10xxa", "tq,ls1043a-tqmls1043a", + "fsl,ls1043a"; + + aliases { + qsgmii-s1-p1 = &qsgmii1_phy1; + qsgmii-s1-p2 = &qsgmii1_phy2; + qsgmii-s1-p3 = &qsgmii1_phy3; + qsgmii-s1-p4 = &qsgmii1_phy4; + qsgmii-s2-p1 = &qsgmii2_phy1; + qsgmii-s2-p2 = &qsgmii2_phy2; + qsgmii-s2-p3 = &qsgmii2_phy3; + qsgmii-s2-p4 = &qsgmii2_phy4; + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = &duart1; + }; +}; + +&esdhc { + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; +}; + +&usb2 { + status = "okay"; +}; + +#include "fsl-ls1043-post.dtsi" +#include "tqmls104xa-mbls10xxa-fman.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi new file mode 100644 index 000000000000..12d5f3938e5d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a-tqmls1043a.dtsi @@ -0,0 +1,32 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + * Device Tree Include file for LS1043A based SoM of TQ + */ + +#include "fsl-ls1043a.dtsi" +#include "tqmls10xxa.dtsi" + +&qspi { + num-cs = <2>; + status = "okay"; + + qflash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <62500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi index f8acbefc805b..d333b773bc45 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi @@ -447,46 +447,47 @@ reg = <0x0 0x1f00000 0x0 0x10000>; interrupts = <0 33 0x4>; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; - fsl,tmu-calibration = <0x00000000 0x00000023 - 0x00000001 0x0000002a - 0x00000002 0x00000031 - 0x00000003 0x00000037 - 0x00000004 0x0000003e - 0x00000005 0x00000044 - 0x00000006 0x0000004b - 0x00000007 0x00000051 - 0x00000008 0x00000058 - 0x00000009 0x0000005e - 0x0000000a 0x00000065 - 0x0000000b 0x0000006b - - 0x00010000 0x00000023 - 0x00010001 0x0000002b - 0x00010002 0x00000033 - 0x00010003 0x0000003b - 0x00010004 0x00000043 - 0x00010005 0x0000004b - 0x00010006 0x00000054 - 0x00010007 0x0000005c - 0x00010008 0x00000064 - 0x00010009 0x0000006c - - 0x00020000 0x00000021 - 0x00020001 0x0000002c - 0x00020002 0x00000036 - 0x00020003 0x00000040 - 0x00020004 0x0000004b - 0x00020005 0x00000055 - 0x00020006 0x0000005f - - 0x00030000 0x00000013 - 0x00030001 0x0000001d - 0x00030002 0x00000028 - 0x00030003 0x00000032 - 0x00030004 0x0000003d - 0x00030005 0x00000047 - 0x00030006 0x00000052 - 0x00030007 0x0000005c>; + fsl,tmu-calibration = + <0x00000000 0x00000023>, + <0x00000001 0x0000002a>, + <0x00000002 0x00000031>, + <0x00000003 0x00000037>, + <0x00000004 0x0000003e>, + <0x00000005 0x00000044>, + <0x00000006 0x0000004b>, + <0x00000007 0x00000051>, + <0x00000008 0x00000058>, + <0x00000009 0x0000005e>, + <0x0000000a 0x00000065>, + <0x0000000b 0x0000006b>, + + <0x00010000 0x00000023>, + <0x00010001 0x0000002b>, + <0x00010002 0x00000033>, + <0x00010003 0x0000003b>, + <0x00010004 0x00000043>, + <0x00010005 0x0000004b>, + <0x00010006 0x00000054>, + <0x00010007 0x0000005c>, + <0x00010008 0x00000064>, + <0x00010009 0x0000006c>, + + <0x00020000 0x00000021>, + <0x00020001 0x0000002c>, + <0x00020002 0x00000036>, + <0x00020003 0x00000040>, + <0x00020004 0x0000004b>, + <0x00020005 0x00000055>, + <0x00020006 0x0000005f>, + + <0x00030000 0x00000013>, + <0x00030001 0x0000001d>, + <0x00030002 0x00000028>, + <0x00030003 0x00000032>, + <0x00030004 0x0000003d>, + <0x00030005 0x00000047>, + <0x00030006 0x00000052>, + <0x00030007 0x0000005c>; #thermal-sensor-cells = <1>; }; @@ -526,20 +527,6 @@ status = "disabled"; }; - dspi1: spi@2110000 { - compatible = "fsl,ls1043a-dspi", "fsl,ls1021a-v1.0-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <0 65 0x4>; - clock-names = "dspi"; - clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL - QORIQ_CLK_PLL_DIV(1)>; - spi-num-chipselects = <5>; - big-endian; - status = "disabled"; - }; - i2c0: i2c@2180000 { compatible = "fsl,ls1043a-i2c", "fsl,vf610-i2c"; #address-cells = <1>; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts new file mode 100644 index 000000000000..37834ae3deac --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a-mbls10xxa.dts @@ -0,0 +1,56 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> + +#include "fsl-ls1046a-tqmls1046a.dtsi" +#include "tqmls10xxa-mbls10xxa.dtsi" + +/ { + model = "TQ-Systems GmbH LS1046A TQMLS1046A SoM on MBLS10xxA board"; + compatible = "tq,ls1046a-tqmls1046a-mbls10xxa", "tq,ls1046a-tqmls1046a", + "fsl,ls1046a"; + + aliases { + qsgmii-s1-p1 = &qsgmii1_phy1; + qsgmii-s1-p2 = &qsgmii1_phy2; + qsgmii-s1-p3 = &qsgmii1_phy3; + qsgmii-s1-p4 = &qsgmii1_phy4; + qsgmii-s2-p1 = &qsgmii2_phy1; + qsgmii-s2-p2 = &qsgmii2_phy2; + qsgmii-s2-p3 = &qsgmii2_phy3; + qsgmii-s2-p4 = &qsgmii2_phy4; + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = &duart1; + }; +}; + +&dspi { + status = "okay"; +}; + +&esdhc { + cd-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; +}; + +&usb2 { + status = "okay"; +}; + +#include "fsl-ls1046-post.dtsi" +#include "tqmls104xa-mbls10xxa-fman.dtsi" + +&enet7 { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi new file mode 100644 index 000000000000..4a8f8bc688f5 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a-tqmls1046a.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + * Device Tree Include file for LS1046A based SoM of TQ + */ + +#include "fsl-ls1046a.dtsi" +#include "tqmls10xxa.dtsi" + +&qspi { + num-cs = <2>; + status = "okay"; + + qflash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <62500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + qflash1: flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <62500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi index 50f68ca5a9af..1515cec23147 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi @@ -445,46 +445,46 @@ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = /* Calibration data group 1 */ - <0x00000000 0x00000023 - 0x00000001 0x00000029 - 0x00000002 0x0000002f - 0x00000003 0x00000036 - 0x00000004 0x0000003c - 0x00000005 0x00000042 - 0x00000006 0x00000049 - 0x00000007 0x0000004f - 0x00000008 0x00000055 - 0x00000009 0x0000005c - 0x0000000a 0x00000062 - 0x0000000b 0x00000068 + <0x00000000 0x00000023>, + <0x00000001 0x00000029>, + <0x00000002 0x0000002f>, + <0x00000003 0x00000036>, + <0x00000004 0x0000003c>, + <0x00000005 0x00000042>, + <0x00000006 0x00000049>, + <0x00000007 0x0000004f>, + <0x00000008 0x00000055>, + <0x00000009 0x0000005c>, + <0x0000000a 0x00000062>, + <0x0000000b 0x00000068>, /* Calibration data group 2 */ - 0x00010000 0x00000022 - 0x00010001 0x0000002a - 0x00010002 0x00000032 - 0x00010003 0x0000003a - 0x00010004 0x00000042 - 0x00010005 0x0000004a - 0x00010006 0x00000052 - 0x00010007 0x0000005a - 0x00010008 0x00000062 - 0x00010009 0x0000006a + <0x00010000 0x00000022>, + <0x00010001 0x0000002a>, + <0x00010002 0x00000032>, + <0x00010003 0x0000003a>, + <0x00010004 0x00000042>, + <0x00010005 0x0000004a>, + <0x00010006 0x00000052>, + <0x00010007 0x0000005a>, + <0x00010008 0x00000062>, + <0x00010009 0x0000006a>, /* Calibration data group 3 */ - 0x00020000 0x00000021 - 0x00020001 0x0000002b - 0x00020002 0x00000035 - 0x00020003 0x0000003e - 0x00020004 0x00000048 - 0x00020005 0x00000052 - 0x00020006 0x0000005c + <0x00020000 0x00000021>, + <0x00020001 0x0000002b>, + <0x00020002 0x00000035>, + <0x00020003 0x0000003e>, + <0x00020004 0x00000048>, + <0x00020005 0x00000052>, + <0x00020006 0x0000005c>, /* Calibration data group 4 */ - 0x00030000 0x00000011 - 0x00030001 0x0000001a - 0x00030002 0x00000024 - 0x00030003 0x0000002e - 0x00030004 0x00000038 - 0x00030005 0x00000042 - 0x00030006 0x0000004c - 0x00030007 0x00000056>; + <0x00030000 0x00000011>, + <0x00030001 0x0000001a>, + <0x00030002 0x00000024>, + <0x00030003 0x0000002e>, + <0x00030004 0x00000038>, + <0x00030005 0x00000042>, + <0x00030006 0x0000004c>, + <0x00030007 0x00000056>; big-endian; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts new file mode 100644 index 000000000000..e567918f6afc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a-mbls10xxa.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> + +#include "fsl-ls1088a-tqmls1088a.dtsi" +#include "tqmls10xxa-mbls10xxa.dtsi" + +/ { + model = "TQ-Systems GmbH LS1088A TQMLS1088A SoM on MBLS10xxA board"; + compatible = "tq,ls1088a-tqmls1088a-mbls10xxa", "tq,ls1088a-tqmls1088a", + "fsl,ls1088a"; + + aliases { + dpmac1 = &dpmac1; + dpmac2 = &dpmac2; + dpmac3 = &dpmac3; + dpmac4 = &dpmac4; + dpmac5 = &dpmac5; + dpmac6 = &dpmac6; + dpmac7 = &dpmac7; + dpmac8 = &dpmac8; + dpmac9 = &dpmac9; + dpmac10 = &dpmac10; + qsgmii-s1-p1 = &qsgmii1_phy1; + qsgmii-s1-p2 = &qsgmii1_phy2; + qsgmii-s1-p3 = &qsgmii1_phy3; + qsgmii-s1-p4 = &qsgmii1_phy4; + qsgmii-s2-p1 = &qsgmii2_phy1; + qsgmii-s2-p2 = &qsgmii2_phy2; + qsgmii-s2-p3 = &qsgmii2_phy3; + qsgmii-s2-p4 = &qsgmii2_phy4; + rgmii-s1 = &rgmii_phy1; + rgmii-s2 = &rgmii_phy2; + serial0 = &duart0; + serial1 = &duart1; + }; + + chosen { + stdout-path = &duart1; + }; +}; + +&esdhc { + cd-gpios = <&gpio3 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio3 13 GPIO_ACTIVE_HIGH>; +}; + +&sfp1_i2c { + status = "okay"; +}; + +&sfp2_i2c { + status = "okay"; +}; + +#include "tqmls1088a-mbls10xxa-mc.dtsi" diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi new file mode 100644 index 000000000000..9a0f21484be9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a-tqmls1088a.dtsi @@ -0,0 +1,42 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + * Device Tree Include file for LS1088A based SoM of TQ + */ + +#include "fsl-ls1088a.dtsi" +#include "tqmls10xxa.dtsi" + +&qspi { + num-cs = <2>; + status = "okay"; + + qflash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <62500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + qflash1: flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <62500000>; + spi-rx-bus-width = <4>; + spi-tx-bus-width = <4>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index 8f6090a9aef2..8616d5e0c388 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -284,46 +284,46 @@ fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x70062>; fsl,tmu-calibration = /* Calibration data group 1 */ - <0x00000000 0x00000023 - 0x00000001 0x0000002a - 0x00000002 0x00000030 - 0x00000003 0x00000037 - 0x00000004 0x0000003d - 0x00000005 0x00000044 - 0x00000006 0x0000004a - 0x00000007 0x00000051 - 0x00000008 0x00000057 - 0x00000009 0x0000005e - 0x0000000a 0x00000064 - 0x0000000b 0x0000006b + <0x00000000 0x00000023>, + <0x00000001 0x0000002a>, + <0x00000002 0x00000030>, + <0x00000003 0x00000037>, + <0x00000004 0x0000003d>, + <0x00000005 0x00000044>, + <0x00000006 0x0000004a>, + <0x00000007 0x00000051>, + <0x00000008 0x00000057>, + <0x00000009 0x0000005e>, + <0x0000000a 0x00000064>, + <0x0000000b 0x0000006b>, /* Calibration data group 2 */ - 0x00010000 0x00000022 - 0x00010001 0x0000002a - 0x00010002 0x00000032 - 0x00010003 0x0000003a - 0x00010004 0x00000042 - 0x00010005 0x0000004a - 0x00010006 0x00000052 - 0x00010007 0x0000005a - 0x00010008 0x00000062 - 0x00010009 0x0000006a + <0x00010000 0x00000022>, + <0x00010001 0x0000002a>, + <0x00010002 0x00000032>, + <0x00010003 0x0000003a>, + <0x00010004 0x00000042>, + <0x00010005 0x0000004a>, + <0x00010006 0x00000052>, + <0x00010007 0x0000005a>, + <0x00010008 0x00000062>, + <0x00010009 0x0000006a>, /* Calibration data group 3 */ - 0x00020000 0x00000021 - 0x00020001 0x0000002b - 0x00020002 0x00000035 - 0x00020003 0x00000040 - 0x00020004 0x0000004a - 0x00020005 0x00000054 - 0x00020006 0x0000005e + <0x00020000 0x00000021>, + <0x00020001 0x0000002b>, + <0x00020002 0x00000035>, + <0x00020003 0x00000040>, + <0x00020004 0x0000004a>, + <0x00020005 0x00000054>, + <0x00020006 0x0000005e>, /* Calibration data group 4 */ - 0x00030000 0x00000010 - 0x00030001 0x0000001c - 0x00030002 0x00000027 - 0x00030003 0x00000032 - 0x00030004 0x0000003e - 0x00030005 0x00000049 - 0x00030006 0x00000054 - 0x00030007 0x00000060>; + <0x00030000 0x00000010>, + <0x00030001 0x0000001c>, + <0x00030002 0x00000027>, + <0x00030003 0x00000032>, + <0x00030004 0x0000003e>, + <0x00030005 0x00000049>, + <0x00030006 0x00000054>, + <0x00030007 0x00000060>; little-endian; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index d2f5345d0560..0b7292835906 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -321,42 +321,43 @@ reg = <0x0 0x1f80000 0x0 0x10000>; interrupts = <0 23 0x4>; fsl,tmu-range = <0xb0000 0x9002a 0x6004c 0x30062>; - fsl,tmu-calibration = <0x00000000 0x00000026 - 0x00000001 0x0000002d - 0x00000002 0x00000032 - 0x00000003 0x00000039 - 0x00000004 0x0000003f - 0x00000005 0x00000046 - 0x00000006 0x0000004d - 0x00000007 0x00000054 - 0x00000008 0x0000005a - 0x00000009 0x00000061 - 0x0000000a 0x0000006a - 0x0000000b 0x00000071 - - 0x00010000 0x00000025 - 0x00010001 0x0000002c - 0x00010002 0x00000035 - 0x00010003 0x0000003d - 0x00010004 0x00000045 - 0x00010005 0x0000004e - 0x00010006 0x00000057 - 0x00010007 0x00000061 - 0x00010008 0x0000006b - 0x00010009 0x00000076 - - 0x00020000 0x00000029 - 0x00020001 0x00000033 - 0x00020002 0x0000003d - 0x00020003 0x00000049 - 0x00020004 0x00000056 - 0x00020005 0x00000061 - 0x00020006 0x0000006d - - 0x00030000 0x00000021 - 0x00030001 0x0000002a - 0x00030002 0x0000003c - 0x00030003 0x0000004e>; + fsl,tmu-calibration = + <0x00000000 0x00000026>, + <0x00000001 0x0000002d>, + <0x00000002 0x00000032>, + <0x00000003 0x00000039>, + <0x00000004 0x0000003f>, + <0x00000005 0x00000046>, + <0x00000006 0x0000004d>, + <0x00000007 0x00000054>, + <0x00000008 0x0000005a>, + <0x00000009 0x00000061>, + <0x0000000a 0x0000006a>, + <0x0000000b 0x00000071>, + + <0x00010000 0x00000025>, + <0x00010001 0x0000002c>, + <0x00010002 0x00000035>, + <0x00010003 0x0000003d>, + <0x00010004 0x00000045>, + <0x00010005 0x0000004e>, + <0x00010006 0x00000057>, + <0x00010007 0x00000061>, + <0x00010008 0x0000006b>, + <0x00010009 0x00000076>, + + <0x00020000 0x00000029>, + <0x00020001 0x00000033>, + <0x00020002 0x0000003d>, + <0x00020003 0x00000049>, + <0x00020004 0x00000056>, + <0x00020005 0x00000061>, + <0x00020006 0x0000006d>, + + <0x00030000 0x00000021>, + <0x00030001 0x0000002a>, + <0x00030002 0x0000003c>, + <0x00030003 0x0000004e>; little-endian; #thermal-sensor-cells = <1>; }; @@ -1186,26 +1187,34 @@ dma-coherent; }; - usb0: usb@3100000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <0 80 0x4>; /* Level high type */ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; - }; + bus: bus { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + dma-ranges = <0x0 0x0 0x0 0x0 0x100 0x00000000>; + + usb0: usb@3100000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <0 80 0x4>; /* Level high type */ + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; + }; - usb1: usb@3110000 { - status = "disabled"; - compatible = "snps,dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <0 81 0x4>; /* Level high type */ - dr_mode = "host"; - snps,quirk-frame-length-adjustment = <0x20>; - snps,dis_rxdet_inp3_quirk; - snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + usb1: usb@3110000 { + compatible = "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <0 81 0x4>; /* Level high type */ + dr_mode = "host"; + snps,quirk-frame-length-adjustment = <0x20>; + snps,dis_rxdet_inp3_quirk; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + status = "disabled"; + }; }; ccn@4000000 { diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts new file mode 100644 index 000000000000..da0f58e26b9a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a.dts @@ -0,0 +1,338 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger + */ + +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> + +#include "fsl-lx2160a-tqmlx2160a.dtsi" + +/ { + model = "TQ Systems GmbH MBLX2160A Starterkit"; + compatible = "tq,lx2160a-tqmlx2160a-mblx2160a", "tq,lx2160a-tqmlx2160a", + "fsl,lx2160a"; + + aliases { + mmc0 = &esdhc0; + mmc1 = &esdhc1; + serial0 = &uart0; + serial1 = &uart1; + serial2 = &uart2; + serial3 = &uart3; + }; + + chosen { + stdout-path = &uart0; + }; + + gpio-keys { + compatible = "gpio-keys"; + + button-user1 { + label = "button:user1"; + gpios = <&gpio2 9 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F1>; + }; + + button-user2 { + label = "button:user2"; + gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F2>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-user1 { + gpios = <&gpioex1 15 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <0>; + linux,default-trigger = "heartbeat"; + }; + + led-user2 { + gpios = <&gpio2 8 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_HEARTBEAT; + function-enumerator = <1>; + linux,default-trigger = "heartbeat"; + }; + }; + + sfp_xfi1: sfp-xfi1 { + compatible = "sff,sfp"; + i2c-bus = <&xfi1_i2c>; + mod-def0-gpios = <&gpioex2 2 GPIO_ACTIVE_LOW>; + los-gpios = <&gpioex2 3 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&gpioex2 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpioex2 1 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + sfp_xfi2: sfp-xfi2 { + compatible = "sff,sfp"; + i2c-bus = <&xfi2_i2c>; + mod-def0-gpios = <&gpioex2 6 GPIO_ACTIVE_LOW>; + los-gpios = <&gpioex2 7 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&gpioex2 4 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpioex2 5 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; +}; + +&can0 { + status = "okay"; +}; + +&can1 { + status = "okay"; +}; + +&dpmac17 { + phy-handle = <&dp83867_2_3>; + phy-connection-type = "rgmii-id"; +}; + +&dpmac18 { + phy-handle = <&dp83867_2_4>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; + + dp83867_1_1: ethernet-phy@1 { + reg = <1>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + dp83867_1_2: ethernet-phy@2 { + reg = <2>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + dp83867_1_3: ethernet-phy@3 { + reg = <3>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + dp83867_1_4: ethernet-phy@4 { + reg = <4>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + dp83867_1_5: ethernet-phy@5 { + reg = <5>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + dp83867_1_6: ethernet-phy@6 { + reg = <6>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; +}; + +&emdio2 { + status = "okay"; + + dp83867_2_1: ethernet-phy@1 { + reg = <1>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + dp83867_2_2: ethernet-phy@2 { + reg = <2>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + dp83867_2_3: ethernet-phy@3 { + reg = <3>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + + dp83867_2_4: ethernet-phy@4 { + reg = <4>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; +}; + +&esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + no-mmc; + no-sdio; + wp-gpios = <&gpio0 30 GPIO_ACTIVE_LOW>; + cd-gpios = <&gpio0 31 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&i2c0 { + gpioex3: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_vcc3v3>; + }; +}; + +&i2c4 { + status = "okay"; + + mux@70 { + compatible = "nxp,pca9544"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <®_vcc3v3>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + gpioex0: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_vcc3v3>; + }; + + gpioex1: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_vcc3v3>; + }; + + gpioex2: gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + #gpio-cells = <2>; + gpio-controller; + vcc-supply = <®_vcc3v3>; + }; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&i2c5 { + status = "okay"; + + mux@70 { + compatible = "nxp,pca9544"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + vdd-supply = <®_vcc3v3>; + + i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + xfi1_i2c: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + }; + + xfi2_i2c: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + }; + + i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&pcs_mdio17 { + status = "okay"; +}; + +&pcs_mdio18 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&uart1 { + status = "okay"; +}; + +&uart2 { + status = "okay"; +}; + +&uart3 { + status = "okay"; +}; + +&usb0 { + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + hub_2_0: hub@1 { + compatible = "usb451,8142"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&gpioex1 0 GPIO_ACTIVE_LOW>; + vcc-supply = <®_vcc3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8140"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&gpioex1 0 GPIO_ACTIVE_LOW>; + vcc-supply = <®_vcc3v3>; + }; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso new file mode 100644 index 000000000000..8284a564e20d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_12_x_x.dtso @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger + */ + +/dts-v1/; +/plugin/; + +&dpmac9 { + phy-handle = <&dp83867_2_1>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; +}; + +&dpmac10 { + phy-handle = <&dp83867_2_2>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; +}; + +&pcs_mdio9 { + status = "okay"; +}; + +&pcs_mdio10 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso new file mode 100644 index 000000000000..636b17a383ed --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_14_x_x.dtso @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger + */ + +/dts-v1/; +/plugin/; + +&dpmac1 { + managed = "in-band-status"; +}; + +&pcs_mdio1 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso new file mode 100644 index 000000000000..6d0c808cd840 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_11_x.dtso @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger + */ + +/dts-v1/; +/plugin/; + +&dpmac12 { + phy-handle = <&dp83867_1_1>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; +}; + +&dpmac13 { + phy-handle = <&dp83867_1_5>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; +}; + +&dpmac14 { + phy-handle = <&dp83867_1_6>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; +}; + +&dpmac16 { + phy-handle = <&dp83867_1_4>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; +}; + +&pcs_mdio12 { + status = "okay"; +}; + +&pcs_mdio13 { + status = "okay"; +}; + +&pcs_mdio14 { + status = "okay"; +}; + +&pcs_mdio16 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso new file mode 100644 index 000000000000..db88a86ff69c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_7_x.dtso @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger + */ + +/dts-v1/; +/plugin/; + +&dpmac12 { + phy-handle = <&dp83867_1_1>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; +}; + +&dpmac13 { + sfp = <&sfp_xfi1>; + managed = "in-band-status"; +}; + +&dpmac14 { + sfp = <&sfp_xfi2>; + managed = "in-band-status"; +}; + +&dpmac16 { + phy-handle = <&dp83867_1_4>; + phy-connection-type = "sgmii"; + managed = "in-band-status"; +}; + +&pcs_mdio12 { + status = "okay"; +}; + +&pcs_mdio13 { + status = "okay"; +}; + +&pcs_mdio14 { + status = "okay"; +}; + +&pcs_mdio16 { + status = "okay"; +}; + +&sfp_xfi1 { + status = "okay"; +}; + +&sfp_xfi2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso new file mode 100644 index 000000000000..f6dfa76aa0e7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a-mblx2160a_x_8_x.dtso @@ -0,0 +1,47 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger + */ + +/dts-v1/; +/plugin/; + +&dpmac13 { + sfp = <&sfp_xfi1>; + managed = "in-band-status"; +}; + +&dpmac14 { + sfp = <&sfp_xfi2>; + managed = "in-band-status"; +}; + +&pcs_mdio13 { + status = "okay"; +}; + +&pcs_mdio14 { + status = "okay"; +}; + +&sata0 { + status = "okay"; +}; + +&sata1 { + status = "okay"; +}; + +&sata2 { + status = "okay"; +}; + +&sfp_xfi1 { + status = "okay"; +}; + +&sfp_xfi2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi new file mode 100644 index 000000000000..89a4765737b4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a-tqmlx2160a.dtsi @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright (c) 2020-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger + */ + +#include "fsl-lx2160a.dtsi" + +/ { + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + + +&emdio1 { + status = "okay"; +}; + +&emdio2 { + status = "okay"; +}; + +&esdhc1 { + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + mmc-hs200-1_8v; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash0: flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <10000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + }; + }; + + flash1: flash@1 { + compatible = "jedec,spi-nor"; + reg = <1>; + #address-cells = <1>; + #size-cells = <1>; + spi-max-frequency = <10000000>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + }; +}; + +&i2c0 { + scl-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + status = "okay"; + + sensor0: temperature-sensor@1f { + compatible = "nxp,se97", "jedec,jc-42.4-temp"; + reg = <0x1f>; + }; + + eeprom1: eeprom@57 { + compatible = "atmel,24c02"; + reg = <0x57>; + pagesize = <16>; + read-only; + vcc-supply = <®_vcc3v3>; + }; + + rtc: rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + quartz-load-femtofarads = <12500>; + }; + + eeprom2: eeprom@50 { + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + vcc-supply = <®_vcc3v3>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi index ea6a94b57aeb..6640b49670ae 100644 --- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi @@ -626,6 +626,13 @@ #phy-cells = <1>; }; + serdes_2: phy@1eb0000 { + compatible = "fsl,lynx-28g"; + reg = <0x0 0x1eb0000 0x0 0x1e30>; + #phy-cells = <1>; + status = "disabled"; + }; + crypto: crypto@8000000 { compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; fsl,sec-era = <10>; @@ -725,9 +732,9 @@ fsl,tmu-range = <0x800000e6 0x8001017d>; fsl,tmu-calibration = /* Calibration data group 1 */ - <0x00000000 0x00000035 + <0x00000000 0x00000035>, /* Calibration data group 2 */ - 0x00000001 0x00000154>; + <0x00000001 0x00000154>; little-endian; #thermal-sensor-cells = <1>; }; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts new file mode 100644 index 000000000000..9f88583aa25e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-clearfog.dts @@ -0,0 +1,376 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162A Clearfog +// +// Copyright 2023 Josua Mayer <josua@solid-run.com> + +/dts-v1/; + +#include "fsl-lx2160a.dtsi" +#include "fsl-lx2162a-sr-som.dtsi" + +/ { + model = "SolidRun LX2162A Clearfog"; + compatible = "solidrun,lx2162a-clearfog", "solidrun,lx2162a-som", "fsl,lx2160a"; + + aliases { + crypto = &crypto; + i2c0 = &i2c0; + i2c1 = &i2c2; + i2c2 = &i2c4; + i2c3 = &sfp_i2c0; + i2c4 = &sfp_i2c1; + i2c5 = &sfp_i2c2; + i2c6 = &sfp_i2c3; + i2c7 = &mpcie1_i2c; + i2c8 = &mpcie0_i2c; + i2c9 = &pcieclk_i2c; + mmc0 = &esdhc0; + mmc1 = &esdhc1; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + led_sfp_at: led-sfp-at { + gpios = <&gpio2 5 GPIO_ACTIVE_HIGH>; /* PROC_IRQ5 */ + default-state = "off"; + }; + + led_sfp_ab: led-sfp-ab { + gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; /* PROC_IRQ11 */ + default-state = "off"; + }; + + led_sfp_bt: led-sfp-bt { + gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>; /* EVT1_B */ + default-state = "off"; + }; + + led_sfp_bb: led-sfp-bb { + gpios = <&gpio2 14 GPIO_ACTIVE_HIGH>; /* EVT2_B */ + default-state = "off"; + }; + }; + + sfp_at: sfp-at { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c0>; + mod-def0-gpios = <&gpio2 16 GPIO_ACTIVE_LOW>; /* EVT4_B */ + maximum-power-milliwatt = <2000>; + }; + + sfp_ab: sfp-ab { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c1>; + mod-def0-gpios = <&gpio2 1 GPIO_ACTIVE_LOW>; /* PROC_IRQ1 */ + maximum-power-milliwatt = <2000>; + }; + + sfp_bt: sfp-bt { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c2>; + mod-def0-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; /* PROC_IRQ10 */ + maximum-power-milliwatt = <2000>; + }; + + sfp_bb: sfp-bb { + compatible = "sff,sfp"; + i2c-bus = <&sfp_i2c3>; + mod-def0-gpios = <&gpio2 15 GPIO_ACTIVE_LOW>; /* EVT3_B */ + maximum-power-milliwatt = <2000>; + }; +}; + +&dpmac3 { + sfp = <&sfp_at>; + managed = "in-band-status"; + phys = <&serdes_1 7>; +}; + +&dpmac4 { + sfp = <&sfp_ab>; + managed = "in-band-status"; + phys = <&serdes_1 6>; +}; + +&dpmac5 { + sfp = <&sfp_bt>; + managed = "in-band-status"; + phys = <&serdes_1 5>; +}; + +&dpmac6 { + sfp = <&sfp_bb>; + managed = "in-band-status"; + phys = <&serdes_1 4>; +}; + +&dpmac11 { + phys = <&serdes_2 0>; + phy-handle = <ðernet_phy3>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac12 { + phys = <&serdes_2 1>; + phy-handle = <ðernet_phy1>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac13 { + phys = <&serdes_2 6>; + phy-handle = <ðernet_phy6>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac14 { + phys = <&serdes_2 7>; + phy-handle = <ðernet_phy8>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac15 { + phys = <&serdes_2 4>; + phy-handle = <ðernet_phy4>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac16 { + phys = <&serdes_2 5>; + phy-handle = <ðernet_phy2>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac17 { + /* override connection to on-SoM phy */ + /delete-property/ phy-handle; + /delete-property/ phy-connection-type; + + phys = <&serdes_2 2>; + phy-handle = <ðernet_phy5>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&dpmac18 { + phys = <&serdes_2 3>; + phy-handle = <ðernet_phy7>; + phy-connection-type = "sgmii"; + status = "okay"; +}; + +&emdio1 { + ethernet_phy1: ethernet-phy@8 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <8>; + max-speed = <1000>; + }; + + ethernet_phy2: ethernet-phy@9 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <9>; + max-speed = <1000>; + }; + + ethernet_phy3: ethernet-phy@10 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <10>; + max-speed = <1000>; + }; + + ethernet_phy4: ethernet-phy@11 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <11>; + max-speed = <1000>; + }; + + ethernet_phy5: ethernet-phy@12 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <12>; + max-speed = <1000>; + }; + + ethernet_phy6: ethernet-phy@13 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <13>; + max-speed = <1000>; + }; + + ethernet_phy7: ethernet-phy@14 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <14>; + max-speed = <1000>; + }; + + ethernet_phy8: ethernet-phy@15 { + compatible = "ethernet-phy-ieee802.3-c45"; + reg = <15>; + max-speed = <1000>; + }; +}; + +&esdhc0 { + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; + status = "okay"; +}; + +ðernet_phy0 { + /* + * SoM has a phy at address 1 connected to SoC Ethernet Controller 1. + * It competes for WRIOP MAC17, and no connector has been wired. + */ + status = "disabled"; +}; + +&i2c2 { + status = "okay"; + + /* retimer@18 */ + + i2c-mux@70 { + compatible = "nxp,pca9546"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + sfp_i2c0: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + sfp_i2c1: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + sfp_i2c2: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + }; + + sfp_i2c3: i2c@3 { + #address-cells = <1>; + #size-cells = <0>; + reg = <3>; + }; + }; + + i2c-mux@71 { + compatible = "nxp,pca9546"; + reg = <0x71>; + #address-cells = <1>; + #size-cells = <0>; + i2c-mux-idle-disconnect; + + mpcie1_i2c: i2c@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + }; + + mpcie0_i2c: i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + }; + + pcieclk_i2c: i2c@2 { + #address-cells = <1>; + #size-cells = <0>; + reg = <2>; + + /* clock-controller@6b */ + }; + }; +}; + +&pcie3 { + status = "disabled"; +}; + +&pcie4 { + status = "disabled"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio4 { + status = "okay"; +}; + +&pcs_mdio5 { + status = "okay"; +}; + +&pcs_mdio6 { + status = "okay"; +}; + +&pcs_mdio11 { + status = "okay"; +}; + +&pcs_mdio12 { + status = "okay"; +}; + +&pcs_mdio13 { + status = "okay"; +}; + +&pcs_mdio14 { + status = "okay"; +}; + +&pcs_mdio15 { + status = "okay"; +}; + +&pcs_mdio16 { + status = "okay"; +}; + +&pcs_mdio17 { + status = "okay"; +}; + +&pcs_mdio18 { + status = "okay"; +}; + +&serdes_1 { + status = "okay"; +}; + +&serdes_2 { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi new file mode 100644 index 000000000000..0580ea30cfbc --- /dev/null +++ b/arch/arm64/boot/dts/freescale/fsl-lx2162a-sr-som.dtsi @@ -0,0 +1,73 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +// +// Device Tree file for LX2162A-SOM +// +// Copyright 2021 Rabeeh Khoury <rabeeh@solid-run.com> +// Copyright 2023 Josua Mayer <josua@solid-run.com> + +&crypto { + status = "okay"; +}; + +&dpmac17 { + phy-handle = <ðernet_phy0>; + phy-connection-type = "rgmii-id"; +}; + +&emdio1 { + status = "okay"; + + ethernet_phy0: ethernet-phy@1 { + reg = <1>; + }; +}; + +&esdhc1 { + bus-width = <8>; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + status = "okay"; +}; + +&fspi { + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + m25p,fast-read; + spi-max-frequency = <50000000>; + /* The following setting enables 1-1-8 (CMD-ADDR-DATA) mode */ + spi-rx-bus-width = <8>; + spi-tx-bus-width = <1>; + }; +}; + +&i2c0 { + status = "okay"; + + fan-controller@18 { + compatible = "ti,amc6821"; + reg = <0x18>; + }; + + ddr_spd: eeprom@51 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x51>; + read-only; + }; + + config_eeprom: eeprom@57 { + compatible = "st,24c02", "atmel,24c02"; + reg = <0x57>; + }; +}; + +&i2c4 { + status = "okay"; + + variable_eeprom: eeprom@54 { + compatible = "st,24c2048", "atmel,24c2048"; + reg = <0x54>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi index c6d51f116298..5438923a905c 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.1.dtsi @@ -165,7 +165,6 @@ "gpio5-24", "UART24-FORCEOFF", "gpio5-26", "LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30", "gpio5-31"; - ngpios = <32>; }; /* Apalis PWM3, MXM3 pin 6 */ diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi index 40067ab8aa74..f6654fdcb147 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-ixora-v1.2.dtsi @@ -68,6 +68,7 @@ gpio = <&lsio_gpio5 22 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-name = "can1_supply"; + startup-delay-us = <1000>; }; reg_can2_supply: regulator-can2-supply { @@ -77,6 +78,7 @@ gpio = <&lsio_gpio2 8 GPIO_ACTIVE_HIGH>; enable-active-high; regulator-name = "can2_supply"; + startup-delay-us = <1000>; }; reg_usb_host_vbus: regulator-usb-host-vbus { @@ -212,7 +214,6 @@ "gpio5-24", "UART24-FORCEOFF", "gpio5-26", "LED-4-GREEN", "gpio5-28", "LED-4-RED", "gpio5-30", "gpio5-31"; - ngpios = <32>; }; /* Apalis PWM3, MXM3 pin 6 */ diff --git a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi index 9b1b522517f8..f69b0c17560a 100644 --- a/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-apalis-v1.1.dtsi @@ -82,12 +82,9 @@ pinctrl-0 = <&pinctrl_wifi_pdn>; gpio = <&lsio_gpio1 28 GPIO_ACTIVE_HIGH>; enable-active-high; + regulator-always-on; regulator-name = "wifi_pwrdn_fake_regulator"; regulator-settling-time-us = <100>; - - regulator-state-mem { - regulator-off-in-suspend; - }; }; reg_pcie_switch: regulator-pcie-switch { @@ -264,7 +261,7 @@ reset-assert-us = <2>; reset-deassert-us = <2>; reset-gpios = <&lsio_gpio1 11 GPIO_ACTIVE_LOW>; - reset-names = "phy-reset"; + reset-names = "phy"; }; }; }; @@ -503,15 +500,6 @@ "MXM3_185", "MXM3_187"; - /* - * Add GPIO2_20 as a wakeup source: - * Pin: 101 SC_P_SPI3_CS0 (MXM3_37/WAKE1_MICO) - * Type: 5 SC_PAD_WAKEUP_FALL_EDGE - * Line: 20 - */ - pad-wakeup = <IMX8QM_SPI3_CS0 5 20>; - pad-wakeup-num = <1>; - pcie-wifi-hog { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie_wifi_refclk>; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi index 6c8d75ef9250..f057c6b21b30 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-audio.dtsi @@ -7,17 +7,73 @@ #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> +audio_ipg_clk: clock-audio-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "audio_ipg_clk"; +}; + audio_subsys: bus@59000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x59000000 0x0 0x59000000 0x1000000>; - audio_ipg_clk: clock-audio-ipg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <120000000>; - clock-output-names = "audio_ipg_clk"; + edma0: dma-controller@591f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x591f0000 0x190000>; + #dma-cells = <3>; + dma-channels = <24>; + dma-channel-mask = <0x5c0c00>; + interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 0 */ + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 6 esai0 */ + <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* 7 */ + <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* 8 spdif0 */ + <GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>, /* 9 */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 10 unused */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 11 unused */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 12 sai0 */ + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* 13 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 14 sai1 */ + <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* 15 */ + <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, /* 16 sai2 */ + <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, /* 17 sai3 */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 18 unused */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 19 unused */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 20 unused */ + <GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>, /* 21 */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 22 unused */ + <GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>; /* 23 unused */ + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH10>, + <&pd IMX_SC_R_DMA_0_CH11>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>, + <&pd IMX_SC_R_DMA_0_CH22>, + <&pd IMX_SC_R_DMA_0_CH23>; }; dsp_lpcg: clock-controller@59580000 { @@ -65,4 +121,34 @@ audio_subsys: bus@59000000 { memory-region = <&dsp_reserved>; status = "disabled"; }; + + edma1: dma-controller@599f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x599f0000 0xc0000>; + #dma-cells = <3>; + dma-channels = <11>; + dma-channel-mask = <0xc0>; + interrupts = <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, /* 0 asrc 1 */ + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, /* 1 */ + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, /* 2 */ + <GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>, /* 3 */ + <GIC_SPI 386 IRQ_TYPE_LEVEL_HIGH>, /* 4 */ + <GIC_SPI 387 IRQ_TYPE_LEVEL_HIGH>, /* 5 */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 6 unused */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* 7 unused */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, /* sai4 */ + <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>; /* sai5 */ + power-domains = <&pd IMX_SC_R_DMA_1_CH0>, + <&pd IMX_SC_R_DMA_1_CH1>, + <&pd IMX_SC_R_DMA_1_CH2>, + <&pd IMX_SC_R_DMA_1_CH3>, + <&pd IMX_SC_R_DMA_1_CH4>, + <&pd IMX_SC_R_DMA_1_CH5>, + <&pd IMX_SC_R_DMA_1_CH6>, + <&pd IMX_SC_R_DMA_1_CH7>, + <&pd IMX_SC_R_DMA_1_CH8>, + <&pd IMX_SC_R_DMA_1_CH9>, + <&pd IMX_SC_R_DMA_1_CH10>; + }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi index fc1a5d34382b..3c42240e78e2 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-conn.dtsi @@ -7,33 +7,33 @@ #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> +conn_axi_clk: clock-conn-axi { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <333333333>; + clock-output-names = "conn_axi_clk"; +}; + +conn_ahb_clk: clock-conn-ahb { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <166666666>; + clock-output-names = "conn_ahb_clk"; +}; + +conn_ipg_clk: clock-conn-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <83333333>; + clock-output-names = "conn_ipg_clk"; +}; + conn_subsys: bus@5b000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5b000000 0x0 0x5b000000 0x1000000>; - conn_axi_clk: clock-conn-axi { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <333333333>; - clock-output-names = "conn_axi_clk"; - }; - - conn_ahb_clk: clock-conn-ahb { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <166666666>; - clock-output-names = "conn_ahb_clk"; - }; - - conn_ipg_clk: clock-conn-ipg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <83333333>; - clock-output-names = "conn_ipg_clk"; - }; - usbotg1: usb@5b0d0000 { compatible = "fsl,imx7ulp-usb", "fsl,imx6ul-usb", "fsl,imx27-usb"; reg = <0x5b0d0000 0x200>; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi index adb98a72bdfd..b0bb77150adc 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-dma.dtsi @@ -7,19 +7,19 @@ #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> +dma_ipg_clk: clock-dma-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <120000000>; + clock-output-names = "dma_ipg_clk"; +}; + dma_subsys: bus@5a000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x5a000000 0x0 0x5a000000 0x1000000>; - dma_ipg_clk: clock-dma-ipg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <120000000>; - clock-output-names = "dma_ipg_clk"; - }; - lpspi0: spi@5a000000 { compatible = "fsl,imx7ulp-spi"; reg = <0x5a000000 0x10000>; @@ -86,52 +86,135 @@ dma_subsys: bus@5a000000 { lpuart0: serial@5a060000 { reg = <0x5a060000 0x1000>; - interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart0_lpcg IMX_LPCG_CLK_4>, <&uart0_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_SC_R_UART_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_0>; + dma-names = "tx","rx"; + dmas = <&edma2 9 0 0>, <&edma2 8 0 1>; status = "disabled"; }; lpuart1: serial@5a070000 { reg = <0x5a070000 0x1000>; - interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart1_lpcg IMX_LPCG_CLK_4>, <&uart1_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_SC_R_UART_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_1>; + dma-names = "tx","rx"; + dmas = <&edma2 11 0 0>, <&edma2 10 0 1>; status = "disabled"; }; lpuart2: serial@5a080000 { reg = <0x5a080000 0x1000>; - interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart2_lpcg IMX_LPCG_CLK_4>, <&uart2_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_SC_R_UART_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_2>; + dma-names = "tx","rx"; + dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; status = "disabled"; }; lpuart3: serial@5a090000 { reg = <0x5a090000 0x1000>; - interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart3_lpcg IMX_LPCG_CLK_4>, <&uart3_lpcg IMX_LPCG_CLK_0>; clock-names = "ipg", "baud"; assigned-clocks = <&clk IMX_SC_R_UART_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <80000000>; power-domains = <&pd IMX_SC_R_UART_3>; + dma-names = "tx","rx"; + dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; status = "disabled"; }; + adma_pwm: pwm@5a190000 { + compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm"; + reg = <0x5a190000 0x1000>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&adma_pwm_lpcg 1>, + <&adma_pwm_lpcg 0>; + clock-names = "ipg", "per"; + assigned-clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <24000000>; + #pwm-cells = <3>; + power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; + }; + + edma2: dma-controller@5a1f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a1f0000 0x170000>; + #dma-cells = <3>; + dma-channels = <16>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_DMA_2_CH0>, + <&pd IMX_SC_R_DMA_2_CH1>, + <&pd IMX_SC_R_DMA_2_CH2>, + <&pd IMX_SC_R_DMA_2_CH3>, + <&pd IMX_SC_R_DMA_2_CH4>, + <&pd IMX_SC_R_DMA_2_CH5>, + <&pd IMX_SC_R_DMA_2_CH6>, + <&pd IMX_SC_R_DMA_2_CH7>, + <&pd IMX_SC_R_DMA_2_CH8>, + <&pd IMX_SC_R_DMA_2_CH9>, + <&pd IMX_SC_R_DMA_2_CH10>, + <&pd IMX_SC_R_DMA_2_CH11>, + <&pd IMX_SC_R_DMA_2_CH12>, + <&pd IMX_SC_R_DMA_2_CH13>, + <&pd IMX_SC_R_DMA_2_CH14>, + <&pd IMX_SC_R_DMA_2_CH15>; + }; + + edma3: dma-controller@5a9f0000 { + compatible = "fsl,imx8qm-edma"; + reg = <0x5a9f0000 0x90000>; + #dma-cells = <3>; + dma-channels = <8>; + interrupts = <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 427 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 428 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 429 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 430 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 431 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_DMA_3_CH0>, + <&pd IMX_SC_R_DMA_3_CH1>, + <&pd IMX_SC_R_DMA_3_CH2>, + <&pd IMX_SC_R_DMA_3_CH3>, + <&pd IMX_SC_R_DMA_3_CH4>, + <&pd IMX_SC_R_DMA_3_CH5>, + <&pd IMX_SC_R_DMA_3_CH6>, + <&pd IMX_SC_R_DMA_3_CH7>; + }; + spi0_lpcg: clock-controller@5a400000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a400000 0x10000>; @@ -228,6 +311,18 @@ dma_subsys: bus@5a000000 { power-domains = <&pd IMX_SC_R_UART_3>; }; + adma_pwm_lpcg: clock-controller@5a590000 { + compatible = "fsl,imx8qxp-lpcg"; + reg = <0x5a590000 0x10000>; + #clock-cells = <1>; + clocks = <&clk IMX_SC_R_LCD_0_PWM_0 IMX_SC_PM_CLK_PER>, + <&dma_ipg_clk>; + clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>; + clock-output-names = "adma_pwm_lpcg_clk", + "adma_pwm_lpcg_ipg_clk"; + power-domains = <&pd IMX_SC_R_LCD_0_PWM_0>; + }; + i2c0: i2c@5a800000 { reg = <0x5a800000 0x4000>; interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>; diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi index a90654155a88..e7783cc2d830 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-img.dtsi @@ -3,25 +3,22 @@ * Copyright 2019-2021 NXP * Zhou Guoniu <guoniu.zhou@nxp.com> */ +img_ipg_clk: clock-img-ipg { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <200000000>; + clock-output-names = "img_ipg_clk"; +}; + img_subsys: bus@58000000 { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <1>; ranges = <0x58000000 0x0 0x58000000 0x1000000>; - img_ipg_clk: clock-img-ipg { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "img_ipg_clk"; - }; - jpegdec: jpegdec@58400000 { reg = <0x58400000 0x00050000>; - interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>; clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; @@ -29,18 +26,13 @@ img_subsys: bus@58000000 { <&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>; assigned-clock-rates = <200000000>, <200000000>; power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, - <&pd IMX_SC_R_MJPEG_DEC_S0>, - <&pd IMX_SC_R_MJPEG_DEC_S1>, - <&pd IMX_SC_R_MJPEG_DEC_S2>, - <&pd IMX_SC_R_MJPEG_DEC_S3>; + <&pd IMX_SC_R_MJPEG_DEC_S0>; + slot = <0>; }; jpegenc: jpegenc@58450000 { reg = <0x58450000 0x00050000>; - interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>, <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; clock-names = "per", "ipg"; @@ -48,10 +40,8 @@ img_subsys: bus@58000000 { <&img_jpeg_enc_lpcg IMX_LPCG_CLK_4>; assigned-clock-rates = <200000000>, <200000000>; power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, - <&pd IMX_SC_R_MJPEG_ENC_S0>, - <&pd IMX_SC_R_MJPEG_ENC_S1>, - <&pd IMX_SC_R_MJPEG_ENC_S2>, - <&pd IMX_SC_R_MJPEG_ENC_S3>; + <&pd IMX_SC_R_MJPEG_ENC_S0>; + slot = <0>; }; img_jpeg_dec_lpcg: clock-controller@585d0000 { diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi index ea8c93757521..7e510b21bbac 100644 --- a/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lsio.dtsi @@ -7,6 +7,13 @@ #include <dt-bindings/clock/imx8-lpcg.h> #include <dt-bindings/firmware/imx/rsrc.h> +lsio_bus_clk: clock-lsio-bus { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + clock-output-names = "lsio_bus_clk"; +}; + lsio_subsys: bus@5d000000 { compatible = "simple-bus"; #address-cells = <1>; @@ -14,20 +21,6 @@ lsio_subsys: bus@5d000000 { ranges = <0x5d000000 0x0 0x5d000000 0x1000000>, <0x08000000 0x0 0x08000000 0x10000000>; - lsio_mem_clk: clock-lsio-mem { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <200000000>; - clock-output-names = "lsio_mem_clk"; - }; - - lsio_bus_clk: clock-lsio-bus { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - clock-output-names = "lsio_bus_clk"; - }; - lsio_pwm0: pwm@5d000000 { compatible = "fsl,imx27-pwm"; reg = <0x5d000000 0x10000>; @@ -36,7 +29,8 @@ lsio_subsys: bus@5d000000 { <&pwm0_lpcg 1>; assigned-clocks = <&clk IMX_SC_R_PWM_0 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; - #pwm-cells = <2>; + #pwm-cells = <3>; + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -48,7 +42,8 @@ lsio_subsys: bus@5d000000 { <&pwm1_lpcg 1>; assigned-clocks = <&clk IMX_SC_R_PWM_1 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; - #pwm-cells = <2>; + #pwm-cells = <3>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -60,7 +55,8 @@ lsio_subsys: bus@5d000000 { <&pwm2_lpcg 1>; assigned-clocks = <&clk IMX_SC_R_PWM_2 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; - #pwm-cells = <2>; + #pwm-cells = <3>; + interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; @@ -72,7 +68,8 @@ lsio_subsys: bus@5d000000 { <&pwm3_lpcg 1>; assigned-clocks = <&clk IMX_SC_R_PWM_3 IMX_SC_PM_CLK_PER>; assigned-clock-rates = <24000000>; - #pwm-cells = <2>; + #pwm-cells = <3>; + interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts index b9157ca08b03..b972658efb17 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8dxl-evk.dts @@ -186,7 +186,6 @@ &flexspi0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_flexspi0>; - nxp,fspi-dll-slvdly = <4>; status = "okay"; mt35xu512aba0: flash@0 { @@ -365,7 +364,6 @@ fsl,spi-only-use-cs1-sel; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpspi3>; - pinctrl-assert-gpios = <&pca6416_1 7 GPIO_ACTIVE_HIGH>; status = "okay"; spidev0: spi@0 { diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi index e2eeddf38aa3..0a477f6318f1 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-adma.dtsi @@ -15,23 +15,53 @@ interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>; }; +&edma2 { + interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 291 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 292 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; +}; + +&edma3 { + interrupts = <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 299 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 301 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 302 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>; +}; + &i2c0 { - compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>; }; &i2c1 { - compatible = "fsl,imx8dxl-lpi2c", "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; }; &i2c2 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; }; &i2c3 { - compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c"; + compatible = "fsl,imx8dxl-lpi2c", "fsl,imx7ulp-lpi2c"; interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi index 652493ae4bb5..6d13e4fafb76 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-conn.dtsi @@ -6,7 +6,7 @@ /delete-node/ &enet1_lpcg; /delete-node/ &fec2; -&conn_subsys { +/ { conn_enet0_root_clk: clock-conn-enet0-root { compatible = "fixed-clock"; #clock-cells = <0>; @@ -14,13 +14,22 @@ clock-output-names = "conn_enet0_root_clk"; }; + clk_dummy: clock-dummy { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <0>; + clock-output-names = "clk_dummy"; + }; +}; + +&conn_subsys { eqos: ethernet@5b050000 { compatible = "nxp,imx8dxl-dwmac-eqos", "snps,dwmac-5.10a"; reg = <0x5b050000 0x10000>; interrupt-parent = <&gic>; interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "eth_wake_irq", "macirq"; + interrupt-names = "macirq", "eth_wake_irq"; clocks = <&eqos_lpcg IMX_LPCG_CLK_4>, <&eqos_lpcg IMX_LPCG_CLK_6>, <&eqos_lpcg IMX_LPCG_CLK_0>, @@ -51,13 +60,6 @@ rx-burst-size-dword = <0x10>; power-domains = <&pd IMX_SC_R_USB_1>; status = "disabled"; - - clk_dummy: clock-dummy { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <0>; - clock-output-names = "clk_dummy"; - }; }; usbmisc2: usbmisc@5b0e0200 { @@ -116,7 +118,7 @@ }; &fec1 { - compatible = "fsl,imx8qm-fec"; + compatible = "fsl,imx8dxl-fec", "fsl,imx8qm-fec", "fsl,imx6sx-fec"; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, diff --git a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi index 550f513708d8..3569abb5bb9b 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl-ss-ddr.dtsi @@ -4,6 +4,6 @@ */ &ddr_pmu0 { - compatible = "fsl,imx8-ddr-pmu"; + compatible = "fsl,imx8dxl-ddr-pmu", "fsl,imx8-ddr-pmu"; interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi index 792b7224ca5b..f580eb6db9a6 100644 --- a/arch/arm64/boot/dts/freescale/imx8dxl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8dxl.dtsi @@ -122,10 +122,8 @@ &lsio_mu1 3 3>; pd: power-controller { - compatible = "fsl,scu-pd"; + compatible = "fsl,imx8dl-scu-pd", "fsl,scu-pd"; #power-domain-cells = <1>; - wakeup-irq = <160 163 235 236 237 228 229 230 231 238 - 239 240 166 169>; }; clk: clock-controller { @@ -168,12 +166,12 @@ }; watchdog { - compatible = "fsl,imx-sc-wdt"; + compatible = "fsl,imx8dxl-sc-wdt", "fsl,imx-sc-wdt"; timeout-sec = <60>; }; tsens: thermal-sensor { - compatible = "fsl,imx-sc-thermal"; + compatible = "fsl,imx8dxl-sc-thermal", "fsl,imx-sc-thermal"; #thermal-sensor-cells = <1>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi index b10e2a703a44..6086dae2e5fb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-baseboard.dtsi @@ -6,6 +6,13 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> / { + + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <1>; + #sound-dai-cells = <0>; + }; + leds { compatible = "gpio-leds"; @@ -98,18 +105,46 @@ enable-active-high; }; - sound { - compatible = "fsl,imx-audio-wm8962"; - model = "wm8962-audio"; - audio-cpu = <&sai3>; - audio-codec = <&wm8962>; - audio-routing = - "Headphone Jack", "HPOUTL", - "Headphone Jack", "HPOUTR", - "Ext Spk", "SPKOUTL", - "Ext Spk", "SPKOUTR", - "AMIC", "MICBIAS", - "IN3R", "AMIC"; + sound-dmic { + compatible = "simple-audio-card"; + simple-audio-card,name = "dmic"; + simple-audio-card,format = "pdm"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + + dailink_master: simple-audio-card,cpu { + sound-dai = <&micfil>; + }; + + simple-audio-card,codec { + sound-dai = <&dmic_codec>; + }; + }; + + sound-wm8962 { + compatible = "simple-audio-card"; + simple-audio-card,name = "wm8962"; + simple-audio-card,format = "i2s"; + simple-audio-card,widgets = "Headphone", "Headphones", + "Microphone", "Headset Mic", + "Speaker", "Speaker"; + simple-audio-card,routing = "Headphones", "HPOUTL", + "Headphones", "HPOUTR", + "Speaker", "SPKOUTL", + "Speaker", "SPKOUTR", + "Headset Mic", "MICBIAS", + "IN3R", "Headset Mic"; + + simple-audio-card,cpu { + sound-dai = <&sai3>; + }; + + simple-audio-card,codec { + sound-dai = <&wm8962>; + clocks = <&clk IMX8MM_CLK_SAI3_ROOT>; + frame-master; + bitclock-master; + }; }; }; @@ -192,6 +227,7 @@ 0x0000 /* 4:FN_DMICCDAT */ 0x0000 /* 5:Default */ >; + #sound-dai-cells = <0>; }; pca6416_0: gpio@20 { @@ -215,6 +251,15 @@ }; }; +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MM_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + &mipi_csi { status = "okay"; ports { @@ -352,6 +397,13 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MM_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MM_IOMUXC_SAI5_RXD0_PDM_DATA0 0xd6 + >; + }; + pinctrl_reg_usb_otg1: usbotg1grp { fsl,pins = < MX8MM_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi index f264102bdb27..62ed64663f49 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-beacon-som.dtsi @@ -3,6 +3,8 @@ * Copyright 2020 Compass Electronics Group, LLC */ +#include "imx8mm-overdrive.dtsi" + / { aliases { rtc0 = &rtc; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts index 010e836ebe5c..27848cee1670 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-ddr4-evk.dts @@ -23,7 +23,6 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi index d897a8527335..44c2cba41a1f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-emcon-avari.dtsi @@ -104,7 +104,7 @@ compatible = "nxp,pca8574"; reg = <0x3a>; gpio-controller; - #gpio-cells = <1>; + #gpio-cells = <2>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi index e31ab8b4f54f..b53104ed8919 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi @@ -26,7 +26,7 @@ port { hdmi_connector_in: endpoint { - remote-endpoint = <&adv7533_out>; + remote-endpoint = <&adv7535_out>; }; }; }; @@ -72,6 +72,13 @@ enable-active-high; }; + reg_vddext_3v3: regulator-vddext-3v3 { + compatible = "regulator-fixed"; + regulator-name = "VDDEXT_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + backlight: backlight { compatible = "pwm-backlight"; pwms = <&pwm1 0 5000000 0>; @@ -317,15 +324,16 @@ hdmi@3d { compatible = "adi,adv7535"; - reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; - reg-names = "main", "cec", "edid", "packet"; + reg = <0x3d>; + interrupt-parent = <&gpio1>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; adi,dsi-lanes = <4>; - - adi,input-depth = <8>; - adi,input-colorspace = "rgb"; - adi,input-clock = "1x"; - adi,input-style = <1>; - adi,input-justification = "evenly"; + avdd-supply = <&buck5_reg>; + dvdd-supply = <&buck5_reg>; + pvdd-supply = <&buck5_reg>; + a2vdd-supply = <&buck5_reg>; + v3p3-supply = <®_vddext_3v3>; + v1p2-supply = <&buck5_reg>; ports { #address-cells = <1>; @@ -334,7 +342,7 @@ port@0 { reg = <0>; - adv7533_in: endpoint { + adv7535_in: endpoint { remote-endpoint = <&dsi_out>; }; }; @@ -342,7 +350,7 @@ port@1 { reg = <1>; - adv7533_out: endpoint { + adv7535_out: endpoint { remote-endpoint = <&hdmi_connector_in>; }; }; @@ -359,12 +367,6 @@ interrupts = <11 8>; status = "okay"; - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - typec1_con: connector { compatible = "usb-c-connector"; label = "USB-C"; @@ -376,6 +378,12 @@ PDO_VAR(5000, 20000, 3000)>; op-sink-microwatt = <15000000>; self-powered; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; }; }; }; @@ -448,7 +456,7 @@ reg = <1>; dsi_out: endpoint { - remote-endpoint = <&adv7533_in>; + remote-endpoint = <&adv7535_in>; data-lanes = <1 2 3 4>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts index 0e8f0d7161ad..12fb79d20b29 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-nitrogen-r2.dts @@ -220,7 +220,7 @@ #address-cells = <1>; #size-cells = <0>; - i2c3@0 { + i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi new file mode 100644 index 000000000000..b31436b5e9b7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-overdrive.dtsi @@ -0,0 +1,29 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&gpu_2d { + assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; +}; + +&gpu_3d { + assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, + <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; + assigned-clock-rates = <0>, <1000000000>; +}; + +&vpu_blk_ctrl { + assigned-clocks = <&clk IMX8MM_CLK_VPU_G1>, + <&clk IMX8MM_CLK_VPU_G2>, + <&clk IMX8MM_CLK_VPU_H1>, + <&clk IMX8MM_VPU_PLL_OUT>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL3_OUT>, + <&clk IMX8MM_VPU_PLL_OUT>, + <&clk IMX8MM_SYS_PLL3_OUT>; + assigned-clock-rates = <750000000>, + <700000000>, + <750000000>, + <700000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts index 606a4f4d5f15..75bbedc6164c 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-phg.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-phg.dts @@ -111,6 +111,11 @@ }; }; +/* QSPI is not populated on the SoM */ +&flexspi { + status = "disabled"; +}; + &ecspi1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi1>; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts new file mode 100644 index 000000000000..27a902569e2a --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-phygate-tauri-l.dts @@ -0,0 +1,489 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright (C) 2023 PHYTEC Messtechnik GmbH + */ + +/dts-v1/; + +#include <dt-bindings/input/linux-event-codes.h> +#include <dt-bindings/leds/common.h> +#include "imx8mm-phycore-som.dtsi" + +/ { + model = "PHYTEC phyGATE-Tauri-L-iMX8MM"; + compatible = "phytec,imx8mm-phygate-tauri-l", + "phytec,imx8mm-phycore-som", "fsl,imx8mm"; + + chosen { + stdout-path = &uart3; + }; + + can_osc_40m: clock-can { + compatible = "fixed-clock"; + clock-frequency = <40000000>; + clock-output-names = "can_osc_40m"; + #clock-cells = <0>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpiokeys>; + + key { + gpios = <&gpio1 9 GPIO_ACTIVE_LOW>; + label = "KEY-A"; + linux,code = <KEY_A>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + led-1 { + color = <LED_COLOR_ID_RED>; + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + + led-2 { + color = <LED_COLOR_ID_YELLOW>; + gpios = <&gpio4 30 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "none"; + }; + }; + + usdhc1_pwrseq: pwr-seq { + compatible = "mmc-pwrseq-simple"; + post-power-on-delay-ms = <100>; + power-off-delay-us = <60>; + reset-gpios = <&gpio2 7 GPIO_ACTIVE_LOW>; + }; + + reg_usb_hub_vbus: regulator-hub-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbhubpwr>; + regulator-name = "usb_hub_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usb_otg1_vbus: regulator-usb-otg1 { + compatible = "regulator-fixed"; + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; + enable-active-high; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1pwr>; + regulator-name = "usb_otg1_vbus"; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + }; + + reg_usdhc2_vmmc: regulator-usdhc2 { + compatible = "regulator-fixed"; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + off-on-delay-us = <20000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "VSD_3V3"; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, + <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio5 2 GPIO_ACTIVE_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; + + /* CAN MCP251XFD */ + can0: can@0 { + compatible = "microchip,mcp251xfd"; + reg = <0>; + clocks = <&can_osc_40m>; + interrupts = <8 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can_int>; + spi-max-frequency = <10000000>; + }; + + tpm: tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + interrupt-parent = <&gpio2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm>; + reg = <1>; + spi-max-frequency = <38000000>; + }; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + pinctrl-1 = <&pinctrl_i2c2_gpio>; + scl-gpios = <&gpio5 16 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 17 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; + + temp_sense0: temperature-sensor@49 { + compatible = "ti,tmp102"; + reg = <0x49>; + interrupt-parent = <&gpio4>; + interrupts = <31 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tempsense>; + #thermal-sensor-cells = <1>; + }; +}; + +&i2c3 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + pinctrl-1 = <&pinctrl_i2c3_gpio>; + scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + pinctrl-1 = <&pinctrl_i2c4_gpio>; + scl-gpios = <&gpio5 20 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + sda-gpios = <&gpio5 21 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; + status = "okay"; +}; + +/* PCIe */ +&pcie0 { + assigned-clocks = <&clk IMX8MM_CLK_PCIE1_AUX>, + <&clk IMX8MM_CLK_PCIE1_PHY>, + <&clk IMX8MM_CLK_PCIE1_CTRL>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL2_50M>, + <&clk IMX8MM_SYS_PLL2_100M>, + <&clk IMX8MM_SYS_PLL2_250M>; + assigned-clock-rates = <10000000>, <100000000>, <250000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie>; + reset-gpio = <&gpio3 22 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&pwm3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm3>; + status = "okay"; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; + status = "okay"; +}; + +/* RTC */ +&rv3028 { + trickle-resistor-ohms = <3000>; +}; + +&uart1 { + assigned-clocks = <&clk IMX8MM_CLK_UART1>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +/* UART2 - RS232 */ +&uart2 { + assigned-clocks = <&clk IMX8MM_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +/* UART - console */ +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "okay"; +}; + +/* USB */ +&usbotg1 { + adp-disable; + dr_mode = "otg"; + over-current-active-low; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg1>; + srp-disable; + vbus-supply = <®_usb_otg1_vbus>; + status = "okay"; +}; + +&usbotg2 { + disable-over-current; + dr_mode = "host"; + samsung,picophy-pre-emp-curr-control = <3>; + samsung,picophy-dc-vol-level-adjust = <7>; + vbus-supply = <®_usb_hub_vbus>; + status = "okay"; +}; + +/* SD-Card */ +&usdhc2 { + assigned-clocks = <&clk IMX8MM_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + bus-width = <4>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + disable-wp; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_usdhc2_vmmc>; + vqmmc-supply = <®_nvcc_sd2>; + status = "okay"; +}; + +&iomuxc { + pinctrl_can_int: can-intgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x00 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x82 + MX8MM_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x82 + MX8MM_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x82 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX8MM_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x00 + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00 + MX8MM_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00 + >; + }; + + pinctrl_gpiokeys: keygrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x00 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c2 + MX8MM_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c2 + >; + }; + + pinctrl_i2c2_gpio: i2c2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C2_SDA_GPIO5_IO17 0x1e0 + MX8MM_IOMUXC_I2C2_SCL_GPIO5_IO16 0x1e0 + >; + }; + + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c2 + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3_gpio: i2c3gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C3_SDA_GPIO5_IO19 0x1e0 + MX8MM_IOMUXC_I2C3_SCL_GPIO5_IO18 0x1e0 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c2 + MX8MM_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4_gpio: i2c4gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_I2C4_SDA_GPIO5_IO21 0x1e0 + MX8MM_IOMUXC_I2C4_SCL_GPIO5_IO20 0x1e0 + >; + }; + + pinctrl_leds: leds1grp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_RXD_GPIO4_IO30 0x00 + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00 + >; + }; + + pinctrl_pcie: pciegrp { + fsl,pins = < + /* COEX2 */ + MX8MM_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x00 + /* COEX1 */ + MX8MM_IOMUXC_SAI1_TXD0_GPIO4_IO12 0x12 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO01_PWM1_OUT 0x40 + >; + }; + + pinctrl_pwm3: pwm3grp { + fsl,pins = < + MX8MM_IOMUXC_SPDIF_TX_PWM3_OUT 0x40 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO15_PWM4_OUT 0x40 + >; + }; + + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x40 + >; + }; + + pinctrl_tempsense: tempsensegrp { + fsl,pins = < + MX8MM_IOMUXC_SAI3_TXFS_GPIO4_IO31 0x00 + >; + }; + + pinctrl_tpm: tpmgrp { + fsl,pins = < + MX8MM_IOMUXC_SD1_STROBE_GPIO2_IO11 0x140 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x00 + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x00 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x00 + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x00 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 + >; + }; + + pinctrl_usbhubpwr: usbhubpwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00 + >; + }; + + pinctrl_usbotg1pwr: usbotg1pwrgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00 + >; + }; + + pinctrl_usbotg1: usbotg1grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x80 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MM_IOMUXC_SD1_CLK_USDHC1_CLK 0x182 + MX8MM_IOMUXC_SD1_CMD_USDHC1_CMD 0xc6 + MX8MM_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc6 + MX8MM_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc6 + MX8MM_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc6 + MX8MM_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12 0x40 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x192 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d2 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d2 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d2 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d2 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d2 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2100mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x194 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d4 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d4 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d4 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d4 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2200mhzgrp { + fsl,pins = < + MX8MM_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0x1d0 + MX8MM_IOMUXC_SD2_CLK_USDHC2_CLK 0x196 + MX8MM_IOMUXC_SD2_CMD_USDHC2_CMD 0x1d6 + MX8MM_IOMUXC_SD2_DATA0_USDHC2_DATA0 0x1d6 + MX8MM_IOMUXC_SD2_DATA1_USDHC2_DATA1 0x1d6 + MX8MM_IOMUXC_SD2_DATA2_USDHC2_DATA2 0x1d6 + MX8MM_IOMUXC_SD2_DATA3_USDHC2_DATA3 0x1d6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso new file mode 100644 index 000000000000..e44249c6d8a0 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx-lvds-tm070jvhg33.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +&{/} { + compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; +}; + +&backlight_lvds { + status = "okay"; +}; + +&dsi_lvds_bridge { + status = "okay"; +}; + +&expander0 { + dsi-mux-oe-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-high; + line-name = "DSI_MUX_OE#"; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +&panel { + compatible = "tianma,tm070jvhg33"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts index 156d793a0c97..ea6e8b85169f 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml-mba8mx.dts @@ -11,6 +11,7 @@ / { model = "TQ-Systems GmbH i.MX8MM TQMa8MxML on MBa8Mx"; compatible = "tq,imx8mm-tqma8mqml-mba8mx", "tq,imx8mm-tqma8mqml", "fsl,imx8mm"; + chassis-type = "embedded"; aliases { eeprom0 = &eeprom3; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi index b4466a26d838..8c0c6e715924 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-tqma8mqml.dtsi @@ -230,6 +230,11 @@ }; }; +&mipi_dsi { + vddcore-supply = <&ldo4_reg>; + vddio-supply = <&ldo3_reg>; +}; + &pcie_phy { fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; fsl,clkreq-unsupported; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi index 0ce60ad9c7d5..6425773f68e0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi @@ -96,7 +96,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio4>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi index 570992a52b75..752caa38eb03 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi @@ -84,8 +84,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -118,7 +125,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio4>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; @@ -153,23 +159,30 @@ pcie@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; - pcie@1,0 { + pcie@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; - pcie@2,3 { + pcie@3,0 { reg = <0x1800 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; - eth1: pcie@5,0 { + eth1: ethernet@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; local-mac-address = [00 00 00 00 00 00]; }; @@ -313,6 +326,7 @@ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi index 1800c6a4b1fc..2aa6c1090fc7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi @@ -104,8 +104,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio1 { @@ -138,7 +145,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio4>; interrupts = <5 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; @@ -173,23 +179,30 @@ pcie@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; - pcie@1,0 { + pcie@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; - pcie@2,4 { + pcie@4,0 { reg = <0x2000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; - eth1: pcie@6,0 { + eth1: ethernet@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; local-mac-address = [00 00 00 00 00 00]; }; @@ -362,6 +375,7 @@ MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 MX8MM_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0xd6 MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 + MX8MM_IOMUXC_GPIO1_IO10_GPIO1_IO10 0xd6 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts index ed46d4f3e66f..87b80e2412cb 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7901.dts @@ -357,6 +357,8 @@ interrupts = <16 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; adc { compatible = "gw,gsc-adc"; @@ -642,7 +644,6 @@ pinctrl-0 = <&pinctrl_ksz>; interrupt-parent = <&gpio4>; interrupts = <18 IRQ_TYPE_EDGE_FALLING>; - phy-mode = "rgmii-id"; ports { #address-cells = <1>; @@ -678,7 +679,6 @@ port@5 { reg = <5>; - label = "cpu"; ethernet = <&fec1>; phy-mode = "rgmii-id"; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts index b318c2d08038..c11260c26d0b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7902.dts @@ -314,6 +314,8 @@ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; adc { compatible = "gw,gsc-adc"; @@ -585,7 +587,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio1>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; @@ -634,13 +635,16 @@ pcie@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + ranges; - eth1: pcie@1,0 { + eth1: ethernet@0,0 { reg = <0x0000 0 0 0 0>; - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <3>; + #size-cells = <2>; + ranges; local-mac-address = [00 00 00 00 00 00]; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts index 0e102a12bca4..db1737bf637d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7903.dts @@ -280,6 +280,8 @@ interrupts = <26 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; adc { compatible = "gw,gsc-adc"; @@ -541,7 +543,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio1>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts index 6afbabc89c02..05489a31e7fd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw7904.dts @@ -330,6 +330,8 @@ interrupts = <26 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; adc { compatible = "gw,gsc-adc"; @@ -585,7 +587,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio1>; interrupts = <15 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi new file mode 100644 index 000000000000..4a0799d63446 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-mallow.dtsi @@ -0,0 +1,173 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin IMX8MM SoM on Mallow carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-mini-nano + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +#include <dt-bindings/leds/common.h> + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + /* SODIMM 52 - USER_LED_1_RED */ + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 54 - USER_LED_1_GREEN */ + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 56 - USER_LED_2_RED */ + led-2 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 58 - USER_LED_2_GREEN */ + led-3 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +/* Verdin SPI_1 */ +&ecspi2 { + pinctrl-0 = <&pinctrl_ecspi2>, <&pinctrl_tpm_cs>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, <&gpio3 2 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm_irq>; + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <18500000>; + }; +}; + +/* EEPROM on Mallow */ +&eeprom_carrier_board { + status = "okay"; +}; + +/* Verdin ETH_1 */ +&fec1 { + status = "okay"; +}; + +/* Temperature sensor on Mallow */ +&hwmon_temp { + compatible = "ti,tmp1075"; + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&i2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie0 { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm3 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_1 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usbotg1 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usbotg2 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&iomuxc { + pinctrl_leds: ledsgrp { + fsl,pins = + <MX8MM_IOMUXC_NAND_ALE_GPIO3_IO0 0x106>, /* SODIMM 52 */ + <MX8MM_IOMUXC_NAND_CE0_B_GPIO3_IO1 0x106>, /* SODIMM 54 */ + <MX8MM_IOMUXC_NAND_DATA00_GPIO3_IO6 0x106>, /* SODIMM 56 */ + <MX8MM_IOMUXC_NAND_DATA01_GPIO3_IO7 0x106>; /* SODIMM 58 */ + }; + + pinctrl_tpm_cs: tpmcsgrp { + fsl,pins = + <MX8MM_IOMUXC_NAND_CE1_B_GPIO3_IO2 0x146>; /* SODIMM 64 */ + }; + + pinctrl_tpm_irq: tpmirqgrp { + fsl,pins = + <MX8MM_IOMUXC_NAND_DQS_GPIO3_IO14 0x141>; /* SODIMM 66 */ + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts new file mode 100644 index 000000000000..1b1999f3a80e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-nonwifi-mallow.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-nonwifi.dtsi" +#include "imx8mm-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini on Mallow"; + compatible = "toradex,verdin-imx8mm-nonwifi-mallow", + "toradex,verdin-imx8mm-nonwifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts new file mode 100644 index 000000000000..2916145f31bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mm-verdin-wifi-mallow.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + */ + +/dts-v1/; + +#include "imx8mm-verdin.dtsi" +#include "imx8mm-verdin-wifi.dtsi" +#include "imx8mm-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin iMX8M Mini WB on Mallow"; + compatible = "toradex,verdin-imx8mm-wifi-mallow", + "toradex,verdin-imx8mm-wifi", + "toradex,verdin-imx8mm", + "fsl,imx8mm"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm.dtsi index 236fe44f779d..8a1b42b94dce 100644 --- a/arch/arm64/boot/dts/freescale/imx8mm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mm.dtsi @@ -399,6 +399,7 @@ "pll8k", "pll11k", "clkext3"; dmas = <&sdma2 24 25 0x80000000>; dma-names = "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -635,6 +636,8 @@ clk: clock-controller@30380000 { compatible = "fsl,imx8mm-ccm"; reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; @@ -646,7 +649,6 @@ <&clk IMX8MM_CLK_AUDIO_AHB>, <&clk IMX8MM_CLK_IPG_AUDIO_ROOT>, <&clk IMX8MM_SYS_PLL3>, - <&clk IMX8MM_VIDEO_PLL1>, <&clk IMX8MM_AUDIO_PLL1>; assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_800M>, <&clk IMX8MM_ARM_PLL_OUT>, @@ -656,7 +658,6 @@ <400000000>, <400000000>, <750000000>, - <594000000>, <393216000>; }; @@ -1132,7 +1133,7 @@ assigned-clock-parents = <&clk IMX8MM_VIDEO_PLL1_OUT>, <&clk IMX8MM_SYS_PLL2_1000M>, <&clk IMX8MM_SYS_PLL1_800M>; - assigned-clock-rates = <594000000>, <500000000>, <200000000>; + assigned-clock-rates = <24000000>, <500000000>, <200000000>; interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_LCDIF>; status = "disabled"; @@ -1150,12 +1151,8 @@ clocks = <&clk IMX8MM_CLK_DSI_CORE>, <&clk IMX8MM_CLK_DSI_PHY_REF>; clock-names = "bus_clk", "sclk_mipi"; - assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>, - <&clk IMX8MM_CLK_DSI_PHY_REF>; - assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>, - <&clk IMX8MM_CLK_24M>; - assigned-clock-rates = <266000000>, <24000000>; - samsung,pll-clock-frequency = <24000000>; + assigned-clocks = <&clk IMX8MM_CLK_DSI_CORE>; + assigned-clock-parents = <&clk IMX8MM_SYS_PLL1_266M>; interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; power-domains = <&disp_blk_ctrl IMX8MM_DISPBLK_PD_MIPI_DSI>; status = "disabled"; @@ -1407,7 +1404,7 @@ assigned-clocks = <&clk IMX8MM_CLK_GPU3D_CORE>, <&clk IMX8MM_GPU_PLL_OUT>; assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; - assigned-clock-rates = <0>, <1000000000>; + assigned-clock-rates = <0>, <800000000>; power-domains = <&pgc_gpu>; }; @@ -1422,7 +1419,7 @@ assigned-clocks = <&clk IMX8MM_CLK_GPU2D_CORE>, <&clk IMX8MM_GPU_PLL_OUT>; assigned-clock-parents = <&clk IMX8MM_GPU_PLL_OUT>; - assigned-clock-rates = <0>, <1000000000>; + assigned-clock-rates = <0>, <800000000>; power-domains = <&pgc_gpu>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi index 16761975f56e..20018ee2c803 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-baseboard.dtsi @@ -4,6 +4,12 @@ */ / { + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <1>; + #sound-dai-cells = <0>; + }; + leds { compatible = "gpio-leds"; @@ -74,6 +80,22 @@ enable-active-high; }; + sound-dmic { + compatible = "simple-audio-card"; + simple-audio-card,name = "dmic"; + simple-audio-card,format = "pdm"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + + dailink_master: simple-audio-card,cpu { + sound-dai = <&micfil>; + }; + + simple-audio-card,codec { + sound-dai = <&dmic_codec>; + }; + }; + sound-wm8962 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8962"; @@ -221,6 +243,15 @@ }; }; +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MN_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MN_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; @@ -311,6 +342,13 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI5_RXC_PDM_CLK 0xd6 + MX8MN_IOMUXC_SAI5_RXD0_PDM_BIT_STREAM0 0xd6 + >; + }; + pinctrl_reg_usb_otg: reg-otggrp { fsl,pins = < MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x19 diff --git a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi index 90073b16536f..2a64115eebf1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-beacon-som.dtsi @@ -3,6 +3,8 @@ * Copyright 2020 Compass Electronics Group, LLC */ +#include "imx8mn-overdrive.dtsi" + / { aliases { rtc0 = &rtc; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi index 22a754d438f1..bbb07c650da9 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-common.dtsi @@ -7,6 +7,7 @@ /dts-v1/; #include "imx8mn.dtsi" +#include "imx8mn-bsh-smm-s2-display.dtsi" / { chosen { diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi new file mode 100644 index 000000000000..7675583a6b67 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2-display.dtsi @@ -0,0 +1,121 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2021 BSH + */ + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 700000 0>; /* 700000 ns = 1337Hz */ + brightness-levels = <0 100>; + num-interpolated-steps = <100>; + default-brightness-level = <50>; + status = "okay"; + }; + + reg_3v3_dvdd: regulator-3v3-O3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_dvdd>; + regulator-name = "3v3-dvdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + + reg_v3v3_avdd: regulator-3v3-O2 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_avdd>; + regulator-name = "3v3-avdd-supply"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_bl>; + status = "okay"; +}; + +&lcdif { + assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>; + assigned-clock-rates = <594000000>; + status = "okay"; +}; + +&pgc_dispmix { + assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB>; + assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <500000000>, <200000000>; +}; + +&mipi_dsi { + #address-cells = <1>; + #size-cells = <0>; + samsung,esc-clock-frequency = <20000000>; + samsung,pll-clock-frequency = <12000000>; + status = "okay"; + + panel@0 { + compatible = "sharp,ls068b3sx02", "syna,r63353"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_panel>; + reg = <0>; + + backlight = <&backlight>; + dvdd-supply = <®_3v3_dvdd>; + avdd-supply = <®_v3v3_avdd>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + }; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&gpu { + status = "okay"; +}; + +&iomuxc { + pinctrl_avdd: avddgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */ + >; + }; + + /* This is for both PWM and voltage regulators for display */ + pinctrl_bl: blgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16 + >; + }; + + pinctrl_dvdd: dvddgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */ + >; + }; + + pinctrl_panel: panelgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */ + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts index 7acc5a960dd9..11a1ba5bfdb7 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-bsh-smm-s2.dts @@ -21,7 +21,6 @@ &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; - nand-on-flash-bbt; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts b/arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts new file mode 100644 index 000000000000..6f9b82958b96 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-dimonoff-gateway-evk.dts @@ -0,0 +1,160 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2022 DimOnOff + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mn-var-som-symphony.dts" + +/ { + model = "DimOnOff Gateway EVK board"; + compatible = "dimonoff,gateway-evk", "variscite,var-som-mx8mn", + "fsl,imx8mn"; + + /* + * U30 FPF2193 regulator. + * Source = BASE_PER_3V3 = SOM_3V3 (COM pin 49). + */ + reg_disp_3v3: regulator-disp-3v3 { + compatible = "regulator-fixed"; + regulator-name = "Display 3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-boot-on; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-enter { + label = "enter"; + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + wakeup-source; + }; + }; + + /* Bourns PEC12R rotary encoder, 24 steps. */ + rotary: rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rotary>; + gpios = <&gpio5 12 GPIO_ACTIVE_LOW>, /* A */ + <&gpio5 13 GPIO_ACTIVE_LOW>; /* B */ + linux,axis = <0>; /* REL_X */ + rotary-encoder,encoding = "gray"; + rotary-encoder,relative-axis; + }; +}; + +/* Disable Asynchronous Sample Rate Converter (audio) */ +&easrc { + status = "disabled"; +}; + +&ecspi1 { + /* Resistive touch controller */ + /delete-node/ touchscreen@0; +}; + +&gpu { + status = "disabled"; +}; + +&i2c2 { + adc@48 { + compatible = "ti,ads7924"; + reg = <0x48>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_adc>; + vref-supply = <®_disp_3v3>; + reset-gpios = <&gpio5 5 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + channel@0 { + reg = <0>; + label = "Pot0"; + }; + channel@1 { + reg = <1>; + label = "Pot1"; + }; + channel@2 { + reg = <2>; + label = "Pot2"; + }; + channel@3 { + reg = <3>; + label = "Pot3"; + }; + }; + + rtc@51 { + compatible = "nxp,pcf2129"; + reg = <0x51>; + reset-source; /* For watchdog. */ + }; + + rtc@53 { + compatible = "nxp,pcf2131"; + reg = <0x53>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + reset-source; /* For watchdog. */ + interrupt-parent = <&gpio5>; + interrupts = <10 IRQ_TYPE_EDGE_FALLING>; /* J17.6 on EVK */ + }; +}; + +&i2c3 { + touchscreen@38 { + status = "disabled"; + }; + + codec@1a { + status = "disabled"; + }; + + /* DS1337 RTC module */ + rtc@68 { + status = "disabled"; + }; +}; + +&sai5 { + status = "disabled"; +}; + +&iomuxc { + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xc6 + >; + }; + + pinctrl_rotary: rotarygrp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x00000156 + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x00000156 + >; + }; + + pinctrl_adc: adcgrp { + fsl,pins = < + MX8MN_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x00000156 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x00000156 + MX8MN_IOMUXC_ECSPI2_MOSI_GPIO5_IO11 0x00000156 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi index 0e60995a5727..a0e13d3324ed 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-evk.dtsi @@ -71,8 +71,6 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_wlf>; wlf,mute-gpios = <&gpio5 21 GPIO_ACTIVE_LOW>; - clocks = <&clk IMX8MN_CLK_SAI3_ROOT>; - clock-names = "mclk"; }; sound-bt-sco { @@ -223,12 +221,6 @@ interrupts = <11 IRQ_TYPE_LEVEL_LOW>; status = "okay"; - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; - }; - }; - typec1_con: connector { compatible = "usb-c-connector"; label = "USB-C"; @@ -240,6 +232,12 @@ PDO_VAR(5000, 20000, 3000)>; op-sink-microwatt = <15000000>; self-powered; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi new file mode 100644 index 000000000000..5d03fb893e90 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-overdrive.dtsi @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +&gpu { + assigned-clocks = <&clk IMX8MN_CLK_GPU_CORE>, + <&clk IMX8MN_CLK_GPU_SHADER>, + <&clk IMX8MN_CLK_GPU_AXI>, + <&clk IMX8MN_CLK_GPU_AHB>, + <&clk IMX8MN_GPU_PLL>; + assigned-clock-parents = <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_GPU_PLL_OUT>, + <&clk IMX8MN_SYS_PLL1_800M>, + <&clk IMX8MN_SYS_PLL1_800M>; + assigned-clock-rates = <600000000>, + <600000000>, + <800000000>, + <400000000>, + <1200000000>; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts new file mode 100644 index 000000000000..1b633bd1ebb6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-rve-gateway.dts @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 DimOnOff + */ + +/dts-v1/; + +#include <dt-bindings/usb/pd.h> +#include "imx8mn-var-som.dtsi" + +/ { + model = "RVE gateway"; + compatible = "rve,rve-gateway", "variscite,var-som-mx8mn", "fsl,imx8mn"; + + crystal_duart_24m: crystal-duart-24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_keys>; + + key-enter { + label = "enter"; + gpios = <&gpio1 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_ENTER>; + }; + + key-exit { + label = "exit"; + gpios = <&gpio3 23 GPIO_ACTIVE_LOW>; + linux,code = <KEY_ESC>; + }; + }; + + lcd { + compatible = "hit,hd44780"; + display-height-chars = <2>; + display-width-chars = <20>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lcd>; + data-gpios = <&gpio5 1 GPIO_ACTIVE_HIGH>, + <&gpio1 6 GPIO_ACTIVE_HIGH>, + <&gpio1 14 GPIO_ACTIVE_HIGH>, + <&gpio4 28 GPIO_ACTIVE_HIGH>, + <&gpio5 24 GPIO_ACTIVE_HIGH>, + <&gpio5 2 GPIO_ACTIVE_HIGH>, + <&gpio1 12 GPIO_ACTIVE_HIGH>, + <&gpio5 25 GPIO_ACTIVE_HIGH>; + enable-gpios = <&gpio5 23 GPIO_ACTIVE_HIGH>; + rs-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + rw-gpios = <&gpio4 27 GPIO_ACTIVE_HIGH>; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + /* Bourns PEC12R rotary encoder, 24 steps. */ + rotary: rotary-encoder { + compatible = "rotary-encoder"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rotary>; + gpios = <&gpio1 5 GPIO_ACTIVE_LOW>, /* A */ + <&gpio3 21 GPIO_ACTIVE_LOW>; /* B */ + linux,axis = <0>; /* REL_X */ + rotary-encoder,encoding = "gray"; + rotary-encoder,relative-axis; + }; +}; + +&ecspi1 { + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + + duart1: serial@0 { + compatible = "nxp,sc16is752"; + reg = <0>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + spi-max-frequency = <4000000>; + clocks = <&crystal_duart_24m>; + interrupt-parent = <&gpio3>; + interrupts = <22 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "RADIO0", "RADIO1", "RADIO2", "RADIO3", + "RADIO4", "RADIO_RESET", "TP12", "TP11"; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + }; + + /delete-node/ touchscreen@0; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + /delete-property/ dmas; + /delete-property/ dma-names; + status = "okay"; + + duart2: serial@0 { + compatible = "nxp,sc16is752"; + reg = <0>; + spi-rx-bus-width = <1>; + spi-tx-bus-width = <1>; + spi-max-frequency = <4000000>; + clocks = <&crystal_duart_24m>; + interrupt-parent = <&gpio3>; + interrupts = <20 IRQ_TYPE_EDGE_FALLING>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "LED_B_USER", "LED_R_USER", "LED_G_USER", + "GPIO_EXT3", "GPIO_EXT2", "GPIO_EXT1", + "GPIO_EXT0", "TP13"; + linux,rs485-enabled-at-boot-time; + rs485-rts-active-low; + }; +}; + +/* Configure PWM pins in GPIO mode: */ +&gpio5 { + gpio-line-names = "", "", "", "PWM3", "PWM2", "PWM1"; +}; + +&gpu { + status = "disabled"; +}; + +&i2c2 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + /* Carrier board EEPROM */ + eeprom_cb: eeprom@56 { + compatible = "atmel,24c04"; + reg = <0x56>; + pagesize = <16>; + vcc-supply = <®_3p3v>; + }; + + lm75: sensor@48 { + compatible = "st,stlm75"; + reg = <0x48>; + vs-supply = <®_3p3v>; + }; + + mcp7940: rtc@6f { + compatible = "microchip,mcp7940x"; + reg = <0x6f>; + }; +}; + +&i2c3 { + codec@1a { + status = "disabled"; + }; +}; + +&i2c4 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + pcf8574_1: gpio@38 { + compatible = "nxp,pcf8574"; + reg = <0x38>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "LED_B_COMM3", "LED_R_COMM3", "LED_G_COMM3", + "TP14", "TP15", "LED_G_COMM4", "LED_R_COMM4", + "LED_B_COMM4"; + }; + + pcf8574_2: gpio@39 { + compatible = "nxp,pcf8574"; + reg = <0x39>; + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = "LED_B_COMM2", "LED_G_COMM2", "LED_B_COMM1", + "LED_R_COMM2", "LED_R_COMM1", "LED_G_COMM1", + "TP16", "TP17"; + }; +}; + +/* Bluetooth */ +&uart2 { + status = "disabled"; +}; + +&usbotg1 { + dr_mode = "host"; + disable-over-current; + status = "okay"; +}; + +/* SD interface on expansion connector. */ +&usdhc2 { + vmmc-supply = <®_3p3v>; + cd-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK 0x13 + MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI 0x13 + MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO 0x13 + MX8MN_IOMUXC_ECSPI1_SS0_GPIO5_IO9 0x13 /* SS0 */ + MX8MN_IOMUXC_SAI5_RXD1_GPIO3_IO22 0x13 /* SC16 IRQ */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MN_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0x13 + MX8MN_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0x13 + MX8MN_IOMUXC_ECSPI2_MISO_ECSPI2_MISO 0x13 + MX8MN_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0x13 /* SS0 */ + MX8MN_IOMUXC_SAI5_RXC_GPIO3_IO20 0x13 /* SC16 IRQ */ + >; + }; + + pinctrl_gpio_keys: gpiokeysgrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO01_GPIO1_IO1 0xc6 /* Enter */ + MX8MN_IOMUXC_SAI5_RXD2_GPIO3_IO23 0xc6 /* Exit */ + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL 0x400001c3 + MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA 0x400001c3 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MN_IOMUXC_I2C4_SCL_I2C4_SCL 0x400001c3 + MX8MN_IOMUXC_I2C4_SDA_I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_lcd: lcdgrp { + fsl,pins = < + MX8MN_IOMUXC_SAI3_TXD_GPIO5_IO1 0x00000156 /* D0 */ + MX8MN_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x00000156 /* D1 */ + MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14 0x00000156 /* D2 */ + MX8MN_IOMUXC_SAI3_RXFS_GPIO4_IO28 0x00000156 /* D3 */ + MX8MN_IOMUXC_UART2_RXD_GPIO5_IO24 0x00000156 /* D4 */ + MX8MN_IOMUXC_SAI3_MCLK_GPIO5_IO2 0x00000156 /* D5 */ + MX8MN_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x00000156 /* D6 */ + MX8MN_IOMUXC_UART2_TXD_GPIO5_IO25 0x00000156 /* D7 */ + MX8MN_IOMUXC_UART1_TXD_GPIO5_IO23 0x00000156 /* E */ + MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x00000156 /* RS */ + MX8MN_IOMUXC_SAI2_MCLK_GPIO4_IO27 0x00000156 /* R/W */ + >; + }; + + pinctrl_rotary: rotarygrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x00000156 /* A */ + MX8MN_IOMUXC_SAI5_RXD0_GPIO3_IO21 0x00000156 /* B */ + >; + }; + + /* Override Card Detect function GPIO value (GPIO1_IO10) from SOM: */ + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MN_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x41 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso new file mode 100644 index 000000000000..29235e390a5d --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx-lvds-tm070jvhg33.dtso @@ -0,0 +1,45 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +&{/} { + compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; +}; + +&backlight_lvds { + status = "okay"; +}; + +&dsi_lvds_bridge { + status = "okay"; +}; + +&expander0 { + dsi-mux-oe-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-high; + line-name = "DSI_MUX_OE#"; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +&panel { + compatible = "tianma,tm070jvhg33"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts index 3f1e49bfe38f..c07d59147ab5 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl-mba8mx.dts @@ -11,6 +11,7 @@ / { model = "TQ-Systems GmbH i.MX8MN TQMa8MxNL on MBa8Mx"; compatible = "tq,imx8mn-tqma8mqnl-mba8mx", "tq,imx8mn-tqma8mqnl", "fsl,imx8mn"; + chassis-type = "embedded"; aliases { eeprom0 = &eeprom3; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi index 391ca5516e4c..fb24b9aa1b93 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-tqma8mqnl.dtsi @@ -219,6 +219,11 @@ }; }; +&mipi_dsi { + vddcore-supply = <&ldo4_reg>; + vddio-supply = <&ldo3_reg>; +}; + &usdhc3 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc3>; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts index a7a57442cb81..f38ee2266b25 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som-symphony.dts @@ -57,6 +57,15 @@ linux,default-trigger = "heartbeat"; }; }; + + /* Peripherals supply, enabled by Q2 after SOM_3V3 rises. */ + reg_per_3v3: regulator-peripheral-3v3 { + compatible = "regulator-fixed"; + regulator-name = "per_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; ðphy { @@ -79,6 +88,7 @@ interrupts = <7 IRQ_TYPE_EDGE_FALLING>; #gpio-cells = <2>; wakeup-source; + vcc-supply = <®_per_3v3>; /* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */ usb3-sata-sel-hog { @@ -118,9 +128,14 @@ pinctrl-0 = <&pinctrl_ptn5150>; status = "okay"; - port { - typec1_dr_sw: endpoint { - remote-endpoint = <&usb1_drd_sw>; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + + port { + typec1_dr_sw: endpoint { + remote-endpoint = <&usb1_drd_sw>; + }; }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi index b8946edf317b..b364307868f2 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn-var-som.dtsi @@ -31,6 +31,14 @@ gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + reg_3v3_fixed: regulator-3v3-fixed { + compatible = "regulator-fixed"; + regulator-name = "fixed_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; }; &A53_0 { @@ -234,6 +242,7 @@ compatible = "atmel,24c04"; reg = <0x52>; pagesize = <16>; + vcc-supply = <®_3v3_fixed>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts index 08746fb82561..0b1fa04f1d67 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts +++ b/arch/arm64/boot/dts/freescale/imx8mn-venice-gw7902.dts @@ -312,6 +312,8 @@ interrupts = <6 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <1>; + #address-cells = <1>; + #size-cells = <0>; adc { compatible = "gw,gsc-adc"; @@ -583,7 +585,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio1>; interrupts = <12 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi index aa38dd6dc9ba..136e75c51251 100644 --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi @@ -371,6 +371,7 @@ "pll8k", "pll11k", "clkext3"; dmas = <&sdma2 24 25 0x80000000>; dma-names = "rx"; + #sound-dai-cells = <0>; status = "disabled"; }; @@ -636,6 +637,8 @@ clk: clock-controller@30380000 { compatible = "fsl,imx8mn-ccm"; reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts index 06e91297fb16..a08057410bde 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-beacon-kit.dts @@ -23,6 +23,12 @@ stdout-path = &uart2; }; + clk_xtal25: clock-xtal25 { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <25000000>; + }; + connector { compatible = "usb-c-connector"; label = "USB-C"; @@ -49,6 +55,12 @@ }; }; + dmic_codec: dmic-codec { + compatible = "dmic-codec"; + num-channels = <1>; + #sound-dai-cells = <0>; + }; + gpio-keys { compatible = "gpio-keys"; autorepeat; @@ -82,6 +94,17 @@ }; }; + bridge-connector { + compatible = "hdmi-connector"; + type = "a"; + + port { + hdmi_con: endpoint { + remote-endpoint = <&adv7535_out>; + }; + }; + }; + leds { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -112,12 +135,6 @@ }; }; - pcie0_refclk: clock-pcie { - compatible = "fixed-clock"; - #clock-cells = <0>; - clock-frequency = <100000000>; - }; - reg_audio: regulator-wm8962 { compatible = "regulator-fixed"; regulator-name = "3v3_aud"; @@ -147,6 +164,37 @@ enable-active-high; }; + sound-adv7535 { + compatible = "simple-audio-card"; + simple-audio-card,name = "sound-adv7535"; + simple-audio-card,format = "i2s"; + + simple-audio-card,cpu { + sound-dai = <&sai5>; + system-clock-direction-out; + }; + + simple-audio-card,codec { + sound-dai = <&adv_bridge>; + }; + }; + + sound-dmic { + compatible = "simple-audio-card"; + simple-audio-card,name = "sound-pdm"; + simple-audio-card,format = "i2s"; + simple-audio-card,bitclock-master = <&dailink_master>; + simple-audio-card,frame-master = <&dailink_master>; + + dailink_master: simple-audio-card,cpu { + sound-dai = <&micfil>; + }; + + simple-audio-card,codec { + sound-dai = <&dmic_codec>; + }; + }; + sound-wm8962 { compatible = "simple-audio-card"; simple-audio-card,name = "wm8962"; @@ -174,6 +222,11 @@ }; }; +&audio_blk_ctrl { + assigned-clocks = <&clk IMX8MP_AUDIO_PLL1>, <&clk IMX8MP_AUDIO_PLL2>; + assigned-clock-rates = <393216000>, <135475200>; +}; + &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi2>; @@ -181,7 +234,7 @@ status = "okay"; tpm: tpm@0 { - compatible = "infineon,slb9670"; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_tpm>; @@ -246,6 +299,42 @@ interrupt-controller; #interrupt-cells = <2>; }; + + adv_bridge: hdmi@3d { + compatible = "adi,adv7535"; + reg = <0x3d>, <0x3c>, <0x3e>, <0x3f>; + reg-names = "main", "cec", "edid", "packet"; + adi,dsi-lanes = <4>; + #sound-dai-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + adv7535_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + + port@1 { + reg = <1>; + + adv7535_out: endpoint { + remote-endpoint = <&hdmi_con>; + }; + }; + }; + }; + + pcieclk: clock-generator@68 { + compatible = "renesas,9fgv0241"; + reg = <0x68>; + clocks = <&clk_xtal25>; + #clock-cells = <1>; + }; }; &i2c3 { @@ -364,6 +453,34 @@ }; }; +&lcdif1 { + status = "okay"; +}; + +&micfil { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pdm>; + assigned-clocks = <&clk IMX8MP_CLK_PDM>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; + assigned-clock-rates = <49152000>; + status = "okay"; +}; + +&mipi_dsi { + samsung,esc-clock-frequency = <10000000>; + status = "okay"; + + ports { + port@1 { + reg = <1>; + + dsi_out: endpoint { + remote-endpoint = <&adv7535_in>; + }; + }; + }; +}; + &pcie { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pcie>; @@ -372,8 +489,9 @@ }; &pcie_phy { + fsl,clkreq-unsupported; fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; - clocks = <&pcie0_refclk>; + clocks = <&pcieclk 1>; clock-names = "ref"; status = "okay"; }; @@ -381,8 +499,19 @@ &sai3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_sai3>; - assigned-clocks = <&clk IMX8MP_CLK_SAI3>; + assigned-clocks = <&clk IMX8MP_CLK_SAI3>, + <&clk IMX8MP_AUDIO_PLL2> ; assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL2_OUT>; + assigned-clock-rates = <12288000>, <361267200>; + fsl,sai-mclk-direction-output; + status = "okay"; +}; + +&sai5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_sai5>; + assigned-clocks = <&clk IMX8MP_CLK_SAI5>; + assigned-clock-parents = <&clk IMX8MP_AUDIO_PLL1_OUT>; assigned-clock-rates = <12288000>; fsl,sai-mclk-direction-output; status = "okay"; @@ -544,6 +673,13 @@ >; }; + pinctrl_pdm: pdmgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__AUDIOMIX_PDM_CLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD0__AUDIOMIX_PDM_BIT_STREAM00 0xd6 + >; + }; + pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { fsl,pins = < MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 @@ -560,6 +696,14 @@ >; }; + pinctrl_sai5: sai5grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD3__AUDIOMIX_SAI5_TX_DATA00 0xd6 + MX8MP_IOMUXC_SAI5_RXD2__AUDIOMIX_SAI5_TX_BCLK 0xd6 + MX8MP_IOMUXC_SAI5_RXD1__AUDIOMIX_SAI5_TX_SYNC 0xd6 + >; + }; + pinctrl_tpm: tpmgrp { fsl,pins = < MX8MP_IOMUXC_SAI1_RXFS__GPIO4_IO00 0x19 /* Reset */ diff --git a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts index 13674dc64be9..d98a040860a4 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-data-modul-edm-sbc.dts @@ -362,6 +362,8 @@ }; buck2: BUCK2 { /* VDD_ARM */ + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1000000>; regulator-ramp-delay = <3125>; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts index 28db9349ed62..2c19766ebf09 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-model-a.dts @@ -75,7 +75,7 @@ &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; - phy-connection-type = "rgmii-id"; + phy-mode = "rgmii-id"; phy-handle = <ðphy0>; status = "okay"; @@ -284,7 +284,6 @@ usb_hub_2_x: hub@1 { compatible = "usbbda,5411"; reg = <1>; - reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; vdd-supply = <®_usb_hub>; peer-hub = <&usb_hub_3_x>; }; @@ -293,7 +292,6 @@ usb_hub_3_x: hub@2 { compatible = "usbbda,411"; reg = <2>; - reset-gpios = <&gpio4 25 GPIO_ACTIVE_LOW>; vdd-supply = <®_usb_hub>; peer-hub = <&usb_hub_2_x>; }; @@ -443,7 +441,6 @@ pinctrl_usb1: usb1grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10 - MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts index 0b0c95432bdc..b11d694b98e1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a-bmb-08.dts @@ -63,6 +63,50 @@ regulator-always-on; }; + reg_csi1_1v8: regulator-csi1-vdd1v8 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "CSI1_VDD1V8"; + gpio = <&expander0 13 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_baseboard_vdd3v3>; + }; + + reg_csi1_3v3: regulator-csi1-vdd3v3 { + compatible = "regulator-fixed"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "CSI1_VDD3V3"; + gpio = <&expander0 14 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vdd5v0>; + }; + + reg_csi2_1v8: regulator-csi2-vdd1v8 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_csi2_1v8>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "CSI2_VDD1V8"; + gpio = <&gpio3 21 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_baseboard_vdd3v3>; + }; + + reg_csi2_3v3: regulator-csi2-vdd3v3 { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_csi2_3v3>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "CSI2_VDD3V3"; + gpio = <&gpio4 25 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_vdd5v0>; + }; + regulator-vbus-usb20 { compatible = "regulator-fixed"; regulator-min-microvolt = <5000000>; @@ -220,7 +264,7 @@ reg = <0x52>; pagesize = <16>; #address-cells = <1>; - #size-cells = <0>; + #size-cells = <1>; /* MACs stored in ASCII */ ethmac1: mac-address@0 { @@ -413,6 +457,18 @@ >; }; + pinctrl_reg_csi2_1v8: regcsi21v8grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x19 + >; + }; + + pinctrl_reg_csi2_3v3: regcsi23v3grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x19 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f diff --git a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi index bc312aa1bfc8..91094c227744 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-debix-som-a.dtsi @@ -6,6 +6,8 @@ #include "imx8mp.dtsi" +#include <dt-bindings/leds/common.h> + / { model = "Polyhex i.MX8MPlus Debix SOM A"; compatible = "polyhex,imx8mp-debix-som-a", "fsl,imx8mp"; @@ -20,6 +22,20 @@ gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; enable-active-high; }; + + gpio-leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + gpios = <&gpio3 16 GPIO_ACTIVE_HIGH>; + default-state = "on"; + linux,default-trigger = "heartbeat"; + function = LED_FUNCTION_STATUS; + color = <LED_COLOR_ID_GREEN>; + }; + }; }; &A53_0 { @@ -203,6 +219,12 @@ }; &iomuxc { + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 + >; + }; + pinctrl_i2c1: i2c1grp { fsl,pins = < MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts index e9fb5f7f39b5..3b1c940860e0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk2.dts @@ -186,9 +186,9 @@ &pcie_phy { clock-names = "ref"; - clocks = <&clk IMX8MP_SYS_PLL2_100M>; + clocks = <&hsio_blk_ctrl>; fsl,clkreq-unsupported; - fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_UNUSED>; + fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_OUTPUT>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts index 31d85d5871c9..fea67a9282f0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-pdk3.dts @@ -35,33 +35,6 @@ clock-frequency = <25000000>; }; - connector { - compatible = "usb-c-connector"; - label = "USB-C"; - data-role = "dual"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - usb_c_0_hs_ep: endpoint { - remote-endpoint = <&dwc3_0_hs_ep>; - }; - }; - - port@1 { - reg = <1>; - - usb_c_0_ss_ep: endpoint { - remote-endpoint = <&ptn5150_in_ep>; - }; - }; - }; - }; - gpio-keys { compatible = "gpio-keys"; @@ -202,33 +175,23 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ptn5150>; - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ptn5150_in_ep: endpoint { - remote-endpoint = <&usb_c_0_ss_ep>; - }; - }; - - port@1 { - reg = <1>; + connector { + compatible = "usb-c-connector"; + label = "USB-C"; + port { ptn5150_out_ep: endpoint { - remote-endpoint = <&dwc3_0_ss_ep>; + remote-endpoint = <&dwc3_0_ep>; }; }; }; }; power-sensor@40 { - compatible = "ti,ina238"; - reg = <0x40>; - shunt-resistor = <20000>; /* 0.02 R */ - ti,shunt-gain = <1>; /* Drop cca. 40mV */ + compatible = "ti,ina238"; + reg = <0x40>; + shunt-resistor = <20000>; /* 0.02 R */ + ti,shunt-gain = <1>; /* Drop cca. 40mV */ }; eeprom_board: eeprom@54 { @@ -253,10 +216,6 @@ }; }; -ðphy0g { - reg = <7>; -}; - &fec { /* Second ethernet */ pinctrl-0 = <&pinctrl_fec_rgmii>; phy-handle = <ðphypdk>; @@ -310,16 +269,7 @@ usb-role-switch; port { - #address-cells = <1>; - #size-cells = <0>; - - dwc3_0_hs_ep: endpoint@0 { - reg = <0>; - remote-endpoint = <&usb_c_0_hs_ep>; - }; - - dwc3_0_ss_ep: endpoint@1 { - reg = <1>; + dwc3_0_ep: endpoint { remote-endpoint = <&ptn5150_out_ep>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi index cb1953d14aa9..4ae4fdab461e 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-dhcom-som.dtsi @@ -25,9 +25,7 @@ reg_eth_vio: regulator-eth-vio { compatible = "regulator-fixed"; - gpio = <&gpio2 10 GPIO_ACTIVE_LOW>; - pinctrl-0 = <&pinctrl_enet_vio>; - pinctrl-names = "default"; + gpio = <&ioexp 2 GPIO_ACTIVE_LOW>; regulator-always-on; regulator-boot-on; regulator-min-microvolt = <3300000>; @@ -57,6 +55,11 @@ regulator-max-microvolt = <3300000>; regulator-name = "VDD_3P3V_AWO"; }; + + wlan_pwrseq: wifi-pwrseq { + compatible = "mmc-pwrseq-simple"; + reset-gpios = <&ioexp 1 GPIO_ACTIVE_LOW>; + }; }; &A53_0 { @@ -112,7 +115,7 @@ reg = <0>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; /* Non-default PHY population option. */ status = "disabled"; }; @@ -128,7 +131,7 @@ reg = <5>; reset-assert-us = <1000>; reset-deassert-us = <1000>; - reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; + reset-gpios = <&ioexp 4 GPIO_ACTIVE_LOW>; /* Default PHY population option. */ status = "okay"; }; @@ -293,6 +296,8 @@ }; buck2: BUCK2 { /* VDD_ARM */ + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; regulator-min-microvolt = <850000>; regulator-max-microvolt = <1000000>; regulator-ramp-delay = <3125>; @@ -348,8 +353,9 @@ }; adc@48 { - compatible = "ti,tla2024"; + compatible = "ti,ads1015"; reg = <0x48>; + interrupts-extended = <&ioexp 7 IRQ_TYPE_EDGE_FALLING>; #address-cells = <1>; #size-cells = <0>; @@ -396,24 +402,54 @@ }; eeprom0: eeprom@50 { /* EEPROM with EQoS MAC address */ - compatible = "atmel,24c02"; - pagesize = <16>; + compatible = "atmel,24c32"; /* M24C32-D */ + pagesize = <32>; reg = <0x50>; }; rv3032: rtc@51 { compatible = "microcrystal,rv3032"; reg = <0x51>; - interrupts-extended = <&gpio5 5 IRQ_TYPE_LEVEL_LOW>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&ioexp 3 IRQ_TYPE_EDGE_FALLING>; + wakeup-source; }; eeprom1: eeprom@53 { /* EEPROM with FEC MAC address */ - compatible = "atmel,24c02"; - pagesize = <16>; + compatible = "atmel,24c32"; /* M24C32-D */ + pagesize = <32>; reg = <0x53>; }; + + eeprom0wl: eeprom@58 { + compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x50 */ + pagesize = <32>; + reg = <0x58>; + }; + + eeprom1wl: eeprom@5b { + compatible = "atmel,24c32d-wl"; /* M24C32-D WL page of 0x53 */ + pagesize = <32>; + reg = <0x5b>; + }; + + ioexp: gpio@74 { + compatible = "nxp,pca9539"; + reg = <0x74>; + gpio-controller; + #gpio-cells = <2>; + interrupts-extended = <&gpio3 20 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ioexp>; + wakeup-source; + + gpio-line-names = + "BT_REG_EN", "WL_REG_EN", "VIO_SWITCHED_#EN", "RTC_#INT", + "ENET_QOS_#RST", "RGB_OSZ_ENABLE", "USB1_ID", "ADC_ALTER_RDY", + "DHCOM-W", "DHCOM-V", "DHCOM-U", "DHCOM-T", + "BT_HOST_WAKE", "BT_DEV_WAKE", "", ""; + }; }; &i2c4 { @@ -463,6 +499,7 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart1>; status = "okay"; + wakeup-source; }; &uart2 { @@ -484,10 +521,8 @@ assigned-clock-rates = <80000000>; bluetooth { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2_bt>; compatible = "cypress,cyw4373a0-bt"; - shutdown-gpios = <&gpio1 12 GPIO_ACTIVE_HIGH>; + shutdown-gpios = <&ioexp 0 GPIO_ACTIVE_HIGH>; max-speed = <4000000>; }; }; @@ -514,8 +549,6 @@ }; &usb_dwc3_0 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb0_vbus>; dr_mode = "otg"; status = "okay"; }; @@ -541,6 +574,7 @@ pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + mmc-pwrseq = <&wlan_pwrseq>; vmmc-supply = <&buck4>; bus-width = <4>; non-removable; @@ -559,7 +593,6 @@ * connected to the SoC, but can be connected on to * SoC pin on the carrier board. */ - reset-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>; }; }; @@ -601,8 +634,9 @@ &pinctrl_dhcom_d &pinctrl_dhcom_e &pinctrl_dhcom_f &pinctrl_dhcom_g &pinctrl_dhcom_h &pinctrl_dhcom_i &pinctrl_dhcom_j &pinctrl_dhcom_k &pinctrl_dhcom_l - /* GPIO_M is connected to CLKOUT1 */ - &pinctrl_dhcom_int>; + &pinctrl_dhcom_m &pinctrl_dhcom_n &pinctrl_dhcom_o + &pinctrl_dhcom_p &pinctrl_dhcom_q &pinctrl_dhcom_r + &pinctrl_dhcom_s &pinctrl_dhcom_int>; pinctrl-names = "default"; pinctrl_dhcom_a: dhcom-a-grp { @@ -689,6 +723,55 @@ >; }; + pinctrl_dhcom_m: dhcom-m-grp { + fsl,pins = < + /* CSIx_MCLK */ + MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x2 + >; + }; + + pinctrl_dhcom_n: dhcom-n-grp { + fsl,pins = < + /* CSI2_D3- */ + MX8MP_IOMUXC_SD1_DATA7__GPIO2_IO09 0x2 + >; + }; + + pinctrl_dhcom_o: dhcom-o-grp { + fsl,pins = < + /* CSI2_D3+ */ + MX8MP_IOMUXC_SD1_DATA6__GPIO2_IO08 0x2 + >; + }; + + pinctrl_dhcom_p: dhcom-p-grp { + fsl,pins = < + /* CSI2_D2- */ + MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x2 + >; + }; + + pinctrl_dhcom_q: dhcom-q-grp { + fsl,pins = < + /* CSI2_D2+ */ + MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x2 + >; + }; + + pinctrl_dhcom_r: dhcom-r-grp { + fsl,pins = < + /* CSI2_D1- */ + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x2 + >; + }; + + pinctrl_dhcom_s: dhcom-s-grp { + fsl,pins = < + /* CSI2_D1+ */ + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x2 + >; + }; + pinctrl_dhcom_int: dhcom-int-grp { fsl,pins = < /* INT_HIGHEST_PRIO */ @@ -762,16 +845,8 @@ >; }; - pinctrl_enet_vio: dhcom-enet-vio-grp { - fsl,pins = < - MX8MP_IOMUXC_SD1_RESET_B__GPIO2_IO10 0x22 - >; - }; - pinctrl_ethphy0: dhcom-ethphy0-grp { fsl,pins = < - /* ENET_QOS_#RST Reset */ - MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 /* ENET_QOS_#INT Interrupt */ MX8MP_IOMUXC_SAI5_RXFS__GPIO3_IO19 0x22 >; @@ -897,6 +972,13 @@ >; }; + pinctrl_ioexp: dhcom-ioexp-grp { + fsl,pins = < + /* #GPIO_EXP_INT */ + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x22 + >; + }; + pinctrl_pmic: dhcom-pmic-grp { fsl,pins = < /* PMIC_nINT */ @@ -910,13 +992,6 @@ >; }; - pinctrl_rtc: dhcom-rtc-grp { - fsl,pins = < - /* RTC_#INT Interrupt */ - MX8MP_IOMUXC_SPDIF_EXT_CLK__GPIO5_IO05 0x40000080 - >; - }; - pinctrl_tc9595: dhcom-tc9595-grp { fsl,pins = < /* RESET_DSIBRIDGE */ @@ -962,13 +1037,6 @@ >; }; - pinctrl_uart2_bt: dhcom-uart2-bt-grp { - fsl,pins = < - /* BT_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x144 - >; - }; - pinctrl_uart3: dhcom-uart3-grp { fsl,pins = < MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX 0x49 @@ -985,12 +1053,6 @@ >; }; - pinctrl_usb0_vbus: dhcom-usb0-grp { - fsl,pins = < - MX8MP_IOMUXC_GPIO1_IO10__USB1_OTG_ID 0x0 - >; - }; - pinctrl_usb1_vbus: dhcom-usb1-grp { fsl,pins = < MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x6 @@ -1006,8 +1068,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; }; @@ -1019,8 +1079,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; }; @@ -1032,8 +1090,6 @@ MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 - /* WL_REG_EN */ - MX8MP_IOMUXC_GPIO1_IO13__GPIO1_IO13 0x144 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts index cc9d468b43ab..f87fa5a948cc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-evk.dts @@ -137,6 +137,28 @@ }; }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + dsp_vdev0vring0: vdev0vring0@942f0000 { + reg = <0 0x942f0000 0 0x8000>; + no-map; + }; + + dsp_vdev0vring1: vdev0vring1@942f8000 { + reg = <0 0x942f8000 0 0x8000>; + no-map; + }; + + dsp_vdev0buffer: vdev0buffer@94300000 { + compatible = "shared-dma-pool"; + reg = <0 0x94300000 0 0x100000>; + no-map; + }; + }; }; &flexspi { diff --git a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts index e4215c83ee0f..da4b1807c275 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-msc-sm2s-ep1.dts @@ -57,8 +57,8 @@ clocks = <&clk IMX8MP_CLK_CLKOUT1>; #sound-dai-cells = <0>; - VDDA-supply = <®_vcc_3v3_audio>; - VDDD-supply = <®_vcc_1v8_audio>; + VDDA-supply = <®_vcc_3v3_audio>; + VDDD-supply = <®_vcc_1v8_audio>; VDDIO-supply = <®_vcc_1v8_audio>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 1e14c4cd3128..c8640cac3edc 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -19,6 +19,36 @@ stdout-path = &uart1; }; + reg_can1_stby: regulator-can1-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1_reg>; + gpio = <&gpio3 20 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can1-stby"; + }; + + reg_can2_stby: regulator-can2-stby { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2_reg>; + gpio = <&gpio3 21 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <3300000>; + regulator-min-microvolt = <3300000>; + regulator-name = "can2-stby"; + }; + + reg_usb1_vbus: regulator-usb1-vbus { + compatible = "regulator-fixed"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb1_vbus>; + gpio = <&gpio1 12 GPIO_ACTIVE_LOW>; + regulator-max-microvolt = <5000000>; + regulator-min-microvolt = <5000000>; + regulator-name = "usb1_host_vbus"; + }; + reg_usdhc2_vmmc: regulator-usdhc2 { compatible = "regulator-fixed"; pinctrl-names = "default"; @@ -57,6 +87,21 @@ }; }; +/* CAN FD */ +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_can1_stby>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2_stby>; + status = "okay"; +}; + &i2c2 { clock-frequency = <400000>; pinctrl-names = "default", "gpio"; @@ -101,6 +146,47 @@ status = "okay"; }; +/* USB1 Host mode Type-A */ +&usb3_phy0 { + vbus-supply = <®_usb1_vbus>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +/* USB2 4-port USB3.0 HUB */ +&usb3_phy1 { + status = "okay"; +}; + +&usb3_1 { + fsl,permanently-attached; + fsl,disable-port-power-control; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +/* RS232/RS485 */ +&uart2 { + assigned-clocks = <&clk IMX8MP_CLK_UART2>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + uart-has-rtscts; + status = "okay"; +}; + /* SD-Card */ &usdhc2 { assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; @@ -115,6 +201,33 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "", "", "X_PMIC_WDOG_B", "", + "PMIC_SD_VSEL", "", "", "", "", "", + "", "", "USB1_OTG_PWR", "", "", "X_nETHPHY_INT"; +}; + +&gpio2 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "X_SD2_CD_B", "", "", "", + "", "", "", "SD2_RESET_B"; +}; + +&gpio3 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "nCAN1_EN", "nCAN2_EN"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "", "", + "", "", "X_PMIC_IRQ_B", "", "nENET0_INT_PWDN"; +}; + &iomuxc { pinctrl_eqos: eqosgrp { fsl,pins = < @@ -136,6 +249,32 @@ >; }; + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD2__CAN1_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD1__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI5_RXD3__CAN2_TX 0x154 + >; + }; + + pinctrl_flexcan1_reg: flexcan1reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXC__GPIO3_IO20 0x154 + >; + }; + + pinctrl_flexcan2_reg: flexcan2reggrp { + fsl,pins = < + MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x154 + >; + }; + pinctrl_i2c2: i2c2grp { fsl,pins = < MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 @@ -163,6 +302,21 @@ >; }; + pinctrl_usb1_vbus: usb1vbusgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x10 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140 + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140 + MX8MP_IOMUXC_SAI3_RXC__UART2_DCE_CTS 0x140 + MX8MP_IOMUXC_SAI3_RXD__UART2_DCE_RTS 0x140 + >; + }; + pinctrl_usdhc2_pins: usdhc2-gpiogrp { fsl,pins = < MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi index d8df97060e8f..c976c3b6cbc6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi @@ -199,6 +199,19 @@ status = "okay"; }; +&gpio1 { + gpio-line-names = "", "", "X_PMIC_WDOG_B", "", + "", "", "", "", "", "", + "", "", "", "", "", "X_nETHPHY_INT"; +}; + +&gpio4 { + gpio-line-names = "", "", "", "", + "", "", "", "", "", "", + "", "", "", "", "", "", + "", "", "X_PMIC_IRQ_B"; +}; + &iomuxc { pinctrl_fec: fecgrp { fsl,pins = < diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi new file mode 100644 index 000000000000..59813ef8e2bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-reva.dtsi @@ -0,0 +1,711 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +#include "imx8mp.dtsi" + +#include <dt-bindings/leds/common.h> + +/ { + aliases { + /* some of this aliases like backlight0, ethernetX and switch0 + * are needed for the bootloader. + */ + backlight0 = &backlight; + ethernet0 = &eqos; + ethernet1 = &lan1; + ethernet2 = &lan2; + rtc0 = &i2c_rtc; + rtc1 = &snvs_rtc; + switch0 = &switch; + }; + + /* + * Backlight is present only on some of boards, so it is disabled by + * default. + */ + backlight: backlight { + compatible = "pwm-backlight"; + pinctrl-0 = <&pinctrl_backlight>; + pwms = <&pwm1 0 20000 0>; + power-supply = <®_24v>; + enable-gpios = <&gpio4 24 GPIO_ACTIVE_HIGH>; + brightness-levels = <0 255>; + num-interpolated-steps = <17>; + default-brightness-level = <8>; + status = "disabled"; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio_led>; + + led-0 { + label = "D1"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; + function = LED_FUNCTION_STATUS; + default-state = "on"; + linux,default-trigger = "heartbeat"; + }; + + led-1 { + label = "D2"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + default-state = "off"; + }; + + led-2 { + label = "D3"; + color = <LED_COLOR_ID_GREEN>; + gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + reg_1v2: regulator-1v2 { + compatible = "regulator-fixed"; + vin-supply = <®_5v_p>; + regulator-name = "1V2"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + reg_2v5: regulator-2v5 { + compatible = "regulator-fixed"; + vin-supply = <®_5v_s>; + regulator-name = "2V5"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + vin-supply = <®_5v_s>; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + /* + * This regulator will provide power as long as possible even if + * undervoltage is detected. + */ + reg_5v_p: regulator-5v-p { + compatible = "regulator-fixed"; + regulator-name = "5V_P"; + vin-supply = <®_24v>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + /* + * This regulator will be automatically shutdown if undervoltage is + * detected. + */ + reg_5v_s: regulator-5v-s { + compatible = "regulator-fixed"; + regulator-name = "5V_S"; + vin-supply = <®_24v>; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_24v: regulator-24v { + compatible = "regulator-fixed"; + regulator-name = "24V"; + regulator-min-microvolt = <24000000>; + regulator-max-microvolt = <24000000>; + }; + + reg_can2rs: regulator-can2rs { + compatible = "regulator-fixed"; + regulator-name = "CAN2RS"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can2rs>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 22 GPIO_ACTIVE_LOW>; + }; + + reg_canrs: regulator-canrs { + compatible = "regulator-fixed"; + regulator-name = "CANRS"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_canrs>; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio4 21 GPIO_ACTIVE_LOW>; + }; + + reg_tft_vcom: regulator-tft-vcom { + compatible = "pwm-regulator"; + pwms = <&pwm4 0 20000 0>; + regulator-name = "VCOM"; + vin-supply = <®_5v_s>; + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + regulator-always-on; + voltage-table = <3600000 26>; + status = "disabled"; + }; + + reg_vsd_3v3: regulator-vsd-3v3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_vsd_3v3>; + vin-supply = <®_vdd_3v3>; + compatible = "regulator-fixed"; + regulator-name = "VSD_3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; +}; + +&A53_0 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_1 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_2 { + cpu-supply = <®_vdd_arm>; +}; + +&A53_3 { + cpu-supply = <®_vdd_arm>; +}; + +&ecspi2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + status = "okay"; + + adc: adc@0 { + compatible = "microchip,mcp3002"; + reg = <0>; + vref-supply = <®_vdd_3v3>; + spi-max-frequency = <1000000>; + #io-channel-cells = <1>; + }; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-txid"; + status = "okay"; + + fixed-link { + speed = <1000>; + full-duplex; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_canrs>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_can2rs>; + status = "okay"; +}; + +&i2c1 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@25 { + compatible = "nxp,pca9450c"; + reg = <0x25>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pmic>; + interrupts-extended = <&gpio1 3 IRQ_TYPE_EDGE_RISING>; + sd-vsel-gpios = <&gpio1 4 GPIO_ACTIVE_HIGH>; + + regulators { + reg_vdd_soc: BUCK1 { + regulator-name = "VDD_SOC"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + vin-supply = <®_5v_p>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + }; + + reg_vdd_arm: BUCK2 { + regulator-name = "VDD_ARM"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <2187500>; + vin-supply = <®_5v_p>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <3125>; + nxp,dvs-run-voltage = <950000>; + nxp,dvs-standby-voltage = <850000>; + }; + + reg_vdd_3v3: BUCK4 { + regulator-name = "VDD_3V3"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + vin-supply = <®_5v_p>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdd_1v8: BUCK5 { + regulator-name = "VDD_1V8"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + vin-supply = <®_5v_p>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_dram_1v1: BUCK6 { + regulator-name = "NVCC_DRAM_1V1"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <3400000>; + vin-supply = <®_5v_p>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_snvs_1v8: LDO1 { + regulator-name = "NVCC_SNVS_1V8"; + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_5v_p>; + regulator-boot-on; + regulator-always-on; + }; + + reg_vdda_1v8: LDO3 { + regulator-name = "VDDA_1V8"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_5v_p>; + regulator-boot-on; + regulator-always-on; + }; + + reg_nvcc_sd2: LDO5 { + regulator-name = "NVCC_SD2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + vin-supply = <®_5v_p>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; +}; + +&i2c3 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + i2c_rtc: rtc@51 { + compatible = "nxp,pcf85063tp"; + reg = <0x51>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rtc>; + interrupts-extended = <&gpio4 31 IRQ_TYPE_EDGE_FALLING>; + quartz-load-femtofarads = <12500>; + }; +}; + +&i2c4 { + clock-frequency = <380000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + switch: switch@5f { + compatible = "microchip,ksz9893"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_switch>; + reset-gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + reg = <0x5f>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + lan1: port@0 { + reg = <0>; + phy-mode = "internal"; + label = "lan1"; + }; + + lan2: port@1 { + reg = <1>; + phy-mode = "internal"; + label = "lan2"; + }; + + port@2 { + reg = <2>; + label = "cpu"; + ethernet = <&eqos>; + phy-mode = "rgmii"; + /* 2ns RX delay is implemented on PCB */ + tx-internal-delay-ps = <2000>; + rx-internal-delay-ps = <0>; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; +}; + +&pwm4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm4>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&uart2 { + /* console */ + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_0 { + status = "okay"; +}; + +&usb3_1 { + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_3v3>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_3v3>; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; +}; + +/* SD Card */ +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; + vmmc-supply = <®_vsd_3v3>; + vqmmc-supply = <®_nvcc_sd2>; + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 20 GPIO_ACTIVE_HIGH>; + bus-width = <4>; + status = "okay"; +}; + +/* eMMC */ +&usdhc3 { + assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc3>; + pinctrl-1 = <&pinctrl_usdhc3_100mhz>; + pinctrl-2 = <&pinctrl_usdhc3_200mhz>; + vmmc-supply = <®_vdd_3v3>; + vqmmc-supply = <®_vdd_1v8>; + bus-width = <8>; + no-sd; + no-sdio; + non-removable; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_backlight: backlightgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_TXFS__GPIO4_IO24 0x0100 + >; + }; + + pinctrl_can2rs: can2rsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x154 + >; + }; + + pinctrl_canrs: canrsgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x154 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x44 + MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x44 + MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x44 + MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x40 + >; + }; + + pinctrl_eqos: eqosgrp { + fsl,pins = < + MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 + MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 + MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 + MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 + MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 + MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 + MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f + MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f + MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f + MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f + MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f + MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_RX__CAN1_RX 0x154 + MX8MP_IOMUXC_SPDIF_TX__CAN1_TX 0x154 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX8MP_IOMUXC_SAI2_MCLK__CAN2_RX 0x154 + MX8MP_IOMUXC_SAI2_TXD0__CAN2_TX 0x154 + >; + }; + + pinctrl_gpio_led: gpioledgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO05__GPIO1_IO05 0x19 + MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x19 + MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x19 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2 + MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2 + MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 + MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 + >; + }; + + pinctrl_pmic: pmicirqgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 0x41 + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX8MP_IOMUXC_SPDIF_EXT_CLK__PWM1_OUT 0x116 + >; + }; + + pinctrl_pwm4: pwm4grp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_MCLK__PWM4_OUT 0x116 + >; + }; + + pinctrl_reg_vsd_3v3: regvsd3v3grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 + >; + }; + + pinctrl_rtc: rtcgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x41 + >; + }; + + pinctrl_switch: switchgrp { + fsl,pins = < + MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x41 + MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x41 + >; + }; + + pinctrl_touchscreen: touchscreengrp { + fsl,pins = < + /* external 10 k pull up */ + /* CTP_INT */ + MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x41 + /* CTP_RST */ + MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x41 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 + MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 + MX8MP_IOMUXC_UART3_RXD__UART1_DTE_RTS 0x140 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x14f + MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x14f + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 + >; + }; + + pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 + >; + }; + + pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 + MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 + MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 + MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 + MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 + MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 + MX8MP_IOMUXC_SD2_WP__GPIO2_IO20 0x1c4 + >; + }; + + pinctrl_usdhc3: usdhc3grp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190 + >; + }; + + pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194 + >; + }; + + pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { + fsl,pins = < + MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 + MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 + MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d6 + MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d6 + MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d6 + MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d6 + MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d6 + MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d6 + MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d6 + MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d6 + MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196 + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO02__WDOG1_WDOG_B 0xc6 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts new file mode 100644 index 000000000000..c1ca69da3cb8 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-hdmi.dts @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revB - HDMI"; + compatible = "skov,imx8mp-skov-revb-hdmi", "fsl,imx8mp"; +}; + +&iomuxc { + pinctrl_hdmi: hdmigrp { + fsl,pins = < + MX8MP_IOMUXC_HDMI_DDC_SCL__HDMIMIX_HDMI_SCL 0x1c3 + MX8MP_IOMUXC_HDMI_DDC_SDA__HDMIMIX_HDMI_SDA 0x1c3 + MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x19 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts new file mode 100644 index 000000000000..ccbd3abedd69 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-lt6.dts @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revB - LT6"; + compatible = "skov,imx8mp-skov-revb-lt6", "fsl,imx8mp"; + + touchscreen { + compatible = "resistive-adc-touch"; + io-channels = <&adc_ts 1>, <&adc_ts 3>, <&adc_ts 4>, <&adc_ts 5>; + io-channel-names = "y", "z1", "z2", "x"; + touchscreen-min-pressure = <65000>; + touchscreen-inverted-y; + touchscreen-swapped-x-y; + touchscreen-x-plate-ohms = <300>; + }; +}; + +®_tft_vcom { + regulator-min-microvolt = <3600000>; + regulator-max-microvolt = <3600000>; + voltage-table = <3600000 26>; + status = "okay"; +}; + +&pwm4 { + status = "okay"; +}; + +&backlight { + status = "okay"; +}; + +&ecspi1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + status = "okay"; + + adc_ts: adc@0 { + compatible = "ti,tsc2046e-adc"; + reg = <0>; + pinctrl-0 = <&pinctrl_touch>; + pinctrl-names ="default"; + spi-max-frequency = <1000000>; + interrupts-extended = <&gpio4 25 IRQ_TYPE_LEVEL_LOW>; + #io-channel-cells = <1>; + + #address-cells = <1>; + #size-cells = <0>; + + channel@1 { + reg = <1>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@3 { + reg = <3>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@4 { + reg = <4>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + + channel@5 { + reg = <5>; + settling-time-us = <700>; + oversampling-ratio = <5>; + }; + }; +}; + +&pwm1 { + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x44 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x44 + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x44 + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x40 + >; + }; + + pinctrl_touch: touchgrp { + fsl,pins = < + /* external pull up */ + MX8MP_IOMUXC_SAI2_TXC__GPIO4_IO25 0x40 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts new file mode 100644 index 000000000000..3c2efdc59bfa --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-skov-revb-mi1010ait-1cp1.dts @@ -0,0 +1,100 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +/dts-v1/; + +#include "imx8mp-skov-reva.dtsi" + +/ { + model = "SKOV IMX8MP CPU revB - MI1010AIT-1CP1"; + compatible = "skov,imx8mp-skov-revb-mi1010ait-1cp1", "fsl,imx8mp"; + + panel { + compatible = "multi-inno,mi1010ait-1cp"; + backlight = <&backlight>; + power-supply = <®_tft_vcom>; + + port { + in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + }; +}; + +&backlight { + status = "okay"; +}; + +&i2c2 { + clock-frequency = <100000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; + + touchscreen@38 { + compatible = "edt,edt-ft5406"; + reg = <0x38>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_touchscreen>; + interrupts-extended = <&gpio4 28 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&gpio4 29 GPIO_ACTIVE_LOW>; + touchscreen-size-x = <1280>; + touchscreen-size-y = <800>; + vcc-supply = <®_vdd_3v3>; + iovcc-supply = <®_vdd_3v3>; + wakeup-source; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + /* IMX8MP_CLK_MEDIA_LDB = IMX8MP_CLK_MEDIA_DISP2_PIX * 7 */ + assigned-clock-rates = <482300000>; + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&in_lvds0>; + }; + }; + }; +}; + +&media_blk_ctrl { + /* currently it is not possible to let display clocks confugure + * automatically, so we need to set them manually + */ + assigned-clock-rates = <500000000>, <200000000>, <0>, + /* IMX8MP_CLK_MEDIA_DISP2_PIX = pixelclk of lvds panel */ + <68900000>, + /* IMX8MP_VIDEO_PLL1 = IMX8MP_CLK_MEDIA_LDB * 2 */ + <964600000>; +}; + +&pwm4 { + status = "okay"; +}; + +&pwm1 { + status = "okay"; +}; + +®_tft_vcom { + regulator-min-microvolt = <3160000>; + regulator-max-microvolt = <3160000>; + voltage-table = <3160000 73>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2 + MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso new file mode 100644 index 000000000000..5058cd9409c7 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl-lvds-g133han01.dtso @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/clock/imx8mp-clock.h> + +&{/} { + compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; +}; + +&backlight_lvds { + status = "okay"; +}; + +&display { + compatible = "auo,g133han01"; + status = "okay"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dual-lvds-odd-pixels; + + panel_in_lvds0: endpoint { + remote-endpoint = <&ldb_lvds_ch0>; + }; + }; + + port@1 { + reg = <1>; + dual-lvds-even-pixels; + + panel_in_lvds1: endpoint { + remote-endpoint = <&ldb_lvds_ch1>; + }; + }; + }; +}; + +&lcdif2 { + status = "okay"; +}; + +&lvds_bridge { + assigned-clocks = <&clk IMX8MP_CLK_MEDIA_LDB>, + <&clk IMX8MP_VIDEO_PLL1>; + assigned-clock-parents = <&clk IMX8MP_VIDEO_PLL1_OUT>; + assigned-clock-rates = <0>, <988400000>; + status = "okay"; + + ports { + port@1 { + ldb_lvds_ch0: endpoint { + remote-endpoint = <&panel_in_lvds0>; + }; + }; + + port@2 { + ldb_lvds_ch1: endpoint { + remote-endpoint = <&panel_in_lvds1>; + }; + }; + }; +}; + +&pwm2 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts index 4240e20d38ac..a2d5d19b2de0 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-tqma8mpql-mba8mpxl.dts @@ -15,6 +15,7 @@ / { model = "TQ-Systems i.MX8MPlus TQMa8MPxL on MBa8MPxL"; compatible = "tq,imx8mp-tqma8mpql-mba8mpxl", "tq,imx8mp-tqma8mpql", "fsl,imx8mp"; + chassis-type = "embedded"; chosen { stdout-path = &uart4; @@ -55,6 +56,21 @@ clock-frequency = <25000000>; }; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "X29"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon0>; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_dwc>; + }; + }; + }; + fan0: pwm-fan { compatible = "pwm-fan"; pinctrl-names = "default"; @@ -602,7 +618,6 @@ &usb3_1 { fsl,disable-port-power-control; fsl,permanently-attached; - dr_mode = "host"; status = "okay"; }; @@ -626,13 +641,10 @@ role-switch-default-mode = "peripheral"; status = "okay"; - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "X29"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon0>; - id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + port { + usb3_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi index c531564c7ebb..0e8d0f3c7ea8 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw71xx.dtsi @@ -8,6 +8,21 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> / { + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + type = "micro"; + label = "Type-C"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_dwc>; + }; + }; + }; + led-controller { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -78,7 +93,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio4>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; @@ -133,13 +147,10 @@ role-switch-default-mode = "peripheral"; status = "okay"; - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - type = "micro"; - label = "Type-C"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + port { + usb3_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi index f3bab22d5e68..41c79d2ebdd6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw72xx.dtsi @@ -8,6 +8,21 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> / { + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + type = "micro"; + label = "otg"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_dwc>; + }; + }; + }; + led-controller { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -83,8 +98,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -113,7 +135,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio4>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; @@ -176,13 +197,10 @@ role-switch-default-mode = "peripheral"; status = "okay"; - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - type = "micro"; - label = "otg"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + port { + usb3_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; }; }; @@ -286,6 +304,7 @@ MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 + MX8MP_IOMUXC_GPIO1_IO10__GPIO1_IO10 0x140 >; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi index 68c62def4c06..d5c400b355af 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw73xx.dtsi @@ -8,6 +8,21 @@ #include <dt-bindings/phy/phy-imx8-pcie.h> / { + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + type = "micro"; + label = "otg"; + id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_dwc>; + }; + }; + }; + led-controller { compatible = "gpio-leds"; pinctrl-names = "default"; @@ -95,8 +110,15 @@ &ecspi2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_spi2>; - cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>; + cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, + <&gpio1 10 GPIO_ACTIVE_LOW>; status = "okay"; + + tpm@1 { + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; + reg = <0x1>; + spi-max-frequency = <36000000>; + }; }; &gpio4 { @@ -125,7 +147,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio4>; interrupts = <21 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; }; @@ -195,13 +216,10 @@ role-switch-default-mode = "peripheral"; status = "okay"; - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - type = "micro"; - label = "otg"; - id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; + port { + usb3_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso new file mode 100644 index 000000000000..270a9114da97 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx-imx219.dtso @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2023 Gateworks Corporation + */ + +#include <dt-bindings/gpio/gpio.h> + +#include "imx8mp-pinfunc.h" + +/dts-v1/; +/plugin/; + +&{/} { + compatible = "gw,imx8mp-gw74xx", "fsl,imx8mp"; + + reg_cam: regulator-cam { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_reg_cam>; + compatible = "regulator-fixed"; + regulator-name = "reg_cam"; + gpio = <&gpio1 4 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + cam24m: cam24m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <24000000>; + clock-output-names = "cam24m"; + }; +}; + +&i2c4 { + #address-cells = <1>; + #size-cells = <0>; + + imx219: sensor@10 { + compatible = "sony,imx219"; + reg = <0x10>; + clocks = <&cam24m>; + VDIG-supply = <®_cam>; + + port { + /* MIPI CSI-2 bus endpoint */ + imx219_to_mipi_csi2: endpoint { + remote-endpoint = <&mipi_csi_0_in>; + clock-lanes = <0>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <456000000>; + }; + }; + }; +}; + +&isi_0 { + status = "okay"; +}; + +&mipi_csi_0 { + status = "okay"; + + ports { + port@0 { + mipi_csi_0_in: endpoint { + remote-endpoint = <&imx219_to_mipi_csi2>; + data-lanes = <1 2>; + }; + }; + }; +}; + +&iomuxc { + pinctrl_reg_cam: regcamgrp { + fsl,pins = < + MX8MP_IOMUXC_GPIO1_IO04__GPIO1_IO04 0x41 + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts index faa370a5885f..cae586cd45bd 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts @@ -35,6 +35,21 @@ reg = <0x0 0x40000000 0 0x80000000>; }; + connector { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbcon1>; + compatible = "gpio-usb-b-connector", "usb-b-connector"; + type = "micro"; + label = "Type-C"; + id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_dwc>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; @@ -181,9 +196,7 @@ status = "okay"; tpm@0 { - compatible = "tcg,tpm_tis-spi"; - #address-cells = <0x1>; - #size-cells = <0x1>; + compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; reg = <0x0>; spi-max-frequency = <36000000>; }; @@ -461,7 +474,6 @@ st,drdy-int-pin = <1>; interrupt-parent = <&gpio1>; interrupts = <7 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "INT1"; }; switch: switch@5f { @@ -512,7 +524,6 @@ port@5 { reg = <5>; - label = "cpu"; ethernet = <&fec>; phy-mode = "rgmii-id"; @@ -696,13 +707,10 @@ role-switch-default-mode = "peripheral"; status = "okay"; - connector { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbcon1>; - compatible = "gpio-usb-b-connector", "usb-b-connector"; - type = "micro"; - label = "Type-C"; - id-gpios = <&gpio1 10 GPIO_ACTIVE_HIGH>; + port { + usb3_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi new file mode 100644 index 000000000000..8482393f3cac --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-mallow.dtsi @@ -0,0 +1,199 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + * + * Common dtsi for Verdin IMX8MP SoM on Mallow carrier board + * + * https://www.toradex.com/computer-on-modules/verdin-arm-family/nxp-imx-8m-plus + * https://www.toradex.com/products/carrier-board/mallow-carrier-board + */ + +#include <dt-bindings/leds/common.h> + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_leds>; + + /* SODIMM 52 - USER_LED_1_RED */ + led-0 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 54 - USER_LED_1_GREEN */ + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <1>; + gpios = <&gpio3 1 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 56 - USER_LED_2_RED */ + led-2 { + color = <LED_COLOR_ID_RED>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio3 6 GPIO_ACTIVE_HIGH>; + }; + + /* SODIMM 58 - USER_LED_2_GREEN */ + led-3 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_DEBUG; + function-enumerator = <2>; + gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&backlight { + power-supply = <®_3p3v>; +}; + +/* Verdin SPI_1 */ +&ecspi1 { + pinctrl-0 = <&pinctrl_ecspi1>, <&pinctrl_tpm_cs>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>, <&gpio3 16 GPIO_ACTIVE_LOW>; + status = "okay"; + + tpm@1 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm_irq>; + interrupt-parent = <&gpio3>; + interrupts = <14 IRQ_TYPE_LEVEL_LOW>; + spi-max-frequency = <18500000>; + }; +}; + +/* EEPROM on Mallow */ +&eeprom_carrier_board { + status = "okay"; +}; + +/* Verdin ETH_1 */ +&eqos { + status = "okay"; +}; + +/* Verdin CAN_1 */ +&flexcan1 { + status = "okay"; +}; + +/* Verdin CAN_2 */ +&flexcan2 { + status = "okay"; +}; + +/* Temperature sensor on Mallow */ +&hwmon_temp { + compatible = "ti,tmp1075"; + status = "okay"; +}; + +/* Verdin I2C_2_DSI */ +&i2c2 { + status = "okay"; +}; + +/* Verdin I2C_4_CSI */ +&i2c3 { + status = "okay"; +}; + +/* Verdin I2C_1 */ +&i2c4 { + status = "okay"; +}; + +/* Verdin PCIE_1 */ +&pcie { + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +/* Verdin PWM_1 */ +&pwm1 { + status = "okay"; +}; + +/* Verdin PWM_2 */ +&pwm2 { + status = "okay"; +}; + +/* Verdin PWM_3_DSI */ +&pwm3 { + status = "okay"; +}; + +®_usdhc2_vmmc { + vin-supply = <®_3p3v>; +}; + +/* Verdin UART_1 */ +&uart1 { + status = "okay"; +}; + +/* Verdin UART_2 */ +&uart2 { + status = "okay"; +}; + +/* Verdin UART_3 */ +&uart3 { + status = "okay"; +}; + +/* Verdin USB_1 */ +&usb3_0 { + status = "okay"; +}; + +&usb3_phy0 { + status = "okay"; +}; + +/* Verdin USB_2 */ +&usb3_1 { + status = "okay"; +}; + +&usb3_phy1 { + status = "okay"; +}; + +/* Verdin SD_1 */ +&usdhc2 { + status = "okay"; +}; + +&iomuxc { + pinctrl_leds: ledsgrp { + fsl,pins = + <MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x106>, /* SODIMM 52 */ + <MX8MP_IOMUXC_NAND_CE0_B__GPIO3_IO01 0x106>, /* SODIMM 54 */ + <MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x106>, /* SODIMM 56 */ + <MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x106>; /* SODIMM 58 */ + }; + + pinctrl_tpm_cs: tpmcsgrp { + fsl,pins = + <MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x82>; /* SODIMM 64 */ + }; + + pinctrl_tpm_irq: tpmirqgrp { + fsl,pins = + <MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x16>; /* SODIMM 66 */ + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts new file mode 100644 index 000000000000..6a536a4964bb --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-nonwifi-mallow.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-nonwifi.dtsi" +#include "imx8mp-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus on Mallow Board"; + compatible = "toradex,verdin-imx8mp-nonwifi-mallow", + "toradex,verdin-imx8mp-nonwifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts new file mode 100644 index 000000000000..08b7aef3fdde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin-wifi-mallow.dts @@ -0,0 +1,18 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR MIT +/* + * Copyright 2023 Toradex + */ + +/dts-v1/; + +#include "imx8mp-verdin.dtsi" +#include "imx8mp-verdin-wifi.dtsi" +#include "imx8mp-verdin-mallow.dtsi" + +/ { + model = "Toradex Verdin iMX8M Plus WB on Mallow Board"; + compatible = "toradex,verdin-imx8mp-wifi-mallow", + "toradex,verdin-imx8mp-wifi", + "toradex,verdin-imx8mp", + "fsl,imx8mp"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi index e9e4fcb562f1..c3305f0d4001 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp-verdin.dtsi @@ -45,6 +45,23 @@ status = "disabled"; }; + connector { + compatible = "gpio-usb-b-connector", "usb-b-connector"; + id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + label = "Type-C"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usb_1_id>; + self-powered; + type = "micro"; + vbus-supply = <®_usb1_vbus>; + + port { + usb_dr_connector: endpoint { + remote-endpoint = <&usb3_dwc>; + }; + }; + }; + gpio-keys { compatible = "gpio-keys"; pinctrl-names = "default"; @@ -184,7 +201,6 @@ &eqos { phy-handle = <ðphy0>; phy-mode = "rgmii-id"; - phy-supply = <®_module_eth1phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; snps,force_thresh_dma_mode; @@ -836,15 +852,10 @@ srp-disable; usb-role-switch; - connector { - compatible = "gpio-usb-b-connector", "usb-b-connector"; - id-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; - label = "Type-C"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usb_1_id>; - self-powered; - type = "micro"; - vbus-supply = <®_usb1_vbus>; + port { + usb3_dwc: endpoint { + remote-endpoint = <&usb_dr_connector>; + }; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index 6f2f50e1639c..76c73daf546b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi @@ -202,6 +202,60 @@ clock-output-names = "clk_ext4"; }; + funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + reserved-memory { #address-cells = <2>; #size-cells = <2>; @@ -210,6 +264,7 @@ dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; + status = "disabled"; }; }; @@ -368,59 +423,6 @@ }; }; - funnel { - /* - * non-configurable funnel don't show up on the AMBA - * bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-funnel"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ca_funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - - ca_funnel_in_port1: endpoint { - remote-endpoint = <&etm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - - ca_funnel_in_port2: endpoint { - remote-endpoint = <&etm2_out_port>; - }; - }; - - port@3 { - reg = <3>; - - ca_funnel_in_port3: endpoint { - remote-endpoint = <&etm3_out_port>; - }; - }; - }; - - out-ports { - port { - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - }; - }; - funnel@28c03000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x28c03000 0x1000>; @@ -725,6 +727,8 @@ clk: clock-controller@30380000 { compatible = "fsl,imx8mp-ccm"; reg = <0x30380000 0x10000>; + interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>, <&clk_ext2>, <&clk_ext3>, <&clk_ext4>; @@ -790,6 +794,12 @@ reg = <IMX8MP_POWER_DOMAIN_AUDIOMIX>; clocks = <&clk IMX8MP_CLK_AUDIO_ROOT>, <&clk IMX8MP_CLK_AUDIO_AXI>; + assigned-clocks = <&clk IMX8MP_CLK_AUDIO_AHB>, + <&clk IMX8MP_CLK_AUDIO_AXI_SRC>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <400000000>, + <600000000>; }; pgc_gpu2d: power-domain@6 { @@ -880,6 +890,15 @@ clocks = <&clk IMX8MP_CLK_ML_AXI>, <&clk IMX8MP_CLK_ML_AHB>, <&clk IMX8MP_CLK_NPU_ROOT>; + assigned-clocks = <&clk IMX8MP_CLK_ML_CORE>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>, + <&clk IMX8MP_SYS_PLL1_800M>; + assigned-clock-rates = <800000000>, + <800000000>, + <300000000>; }; }; }; @@ -1453,6 +1472,47 @@ interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; + + easrc: easrc@30c90000 { + compatible = "fsl,imx8mp-easrc", "fsl,imx8mn-easrc"; + reg = <0x30c90000 0x10000>; + interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_ASRC_IPG>; + clock-names = "mem"; + dmas = <&sdma2 16 23 0> , <&sdma2 17 23 0>, + <&sdma2 18 23 0> , <&sdma2 19 23 0>, + <&sdma2 20 23 0> , <&sdma2 21 23 0>, + <&sdma2 22 23 0> , <&sdma2 23 23 0>; + dma-names = "ctx0_rx", "ctx0_tx", + "ctx1_rx", "ctx1_tx", + "ctx2_rx", "ctx2_tx", + "ctx3_rx", "ctx3_tx"; + firmware-name = "imx/easrc/easrc-imx8mn.bin"; + fsl,asrc-rate = <8000>; + fsl,asrc-format = <2>; + status = "disabled"; + }; + + micfil: audio-controller@30ca0000 { + compatible = "fsl,imx8mp-micfil"; + reg = <0x30ca0000 0x10000>; + #sound-dai-cells = <0>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_IPG>, + <&audio_blk_ctrl IMX8MP_CLK_AUDIOMIX_PDM_SEL>, + <&clk IMX8MP_AUDIO_PLL1_OUT>, + <&clk IMX8MP_AUDIO_PLL2_OUT>, + <&clk IMX8MP_CLK_EXT3>; + clock-names = "ipg_clk", "ipg_clk_app", + "pll8k", "pll11k", "clkext3"; + dmas = <&sdma2 24 25 0x80000000>; + dma-names = "rx"; + status = "disabled"; + }; + }; sdma3: dma-controller@30e00000 { @@ -1964,6 +2024,18 @@ interconnect-names = "g1", "g2", "vc8000e"; }; + npu: npu@38500000 { + compatible = "vivante,gc"; + reg = <0x38500000 0x200000>; + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_NPU_ROOT>, + <&clk IMX8MP_CLK_ML_AXI>, + <&clk IMX8MP_CLK_ML_AHB>; + clock-names = "core", "shader", "bus", "reg"; + power-domains = <&pgc_mlmix>; + }; + gic: interrupt-controller@38800000 { compatible = "arm,gic-v3"; reg = <0x38800000 0x10000>, @@ -2024,6 +2096,7 @@ phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; }; }; @@ -2066,6 +2139,7 @@ phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; snps,gfladj-refclk-lpm-sel-quirk; + snps,parkmode-disable-ss-quirk; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts index 6376417e918c..d8cf1f27c3ec 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-kontron-pitx-imx8m.dts @@ -65,7 +65,7 @@ status = "okay"; tpm@0 { - compatible = "infineon,slb9670"; + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; reg = <0>; spi-max-frequency = <43000000>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi index 138a4d36a7ef..ffb5fe61630d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-librem5.dtsi @@ -381,7 +381,7 @@ gpio-hog; gpios = <1 GPIO_ACTIVE_HIGH>; input; - lane-mapping = "pmic-5v"; + line-name = "pmic-5v"; }; }; @@ -1001,7 +1001,7 @@ }; regulator@3e { - compatible = "tps65132"; + compatible = "ti,tps65132"; reg = <0x3e>; reg_lcd_avdd: outp { @@ -1154,15 +1154,12 @@ pinctrl-0 = <&pinctrl_charger_in>; interrupt-parent = <&gpio3>; interrupts = <3 IRQ_TYPE_EDGE_FALLING>; - phys = <&usb3_phy0>; ti,battery-regulation-voltage = <4208000>; /* uV */ ti,termination-current = <128000>; /* uA */ ti,precharge-current = <128000>; /* uA */ ti,minimum-sys-voltage = <3700000>; /* uV */ ti,boost-voltage = <5000000>; /* uV */ ti,boost-max-current = <1500000>; /* uA */ - ti,use-vinmin-threshold = <1>; /* enable VINDPM */ - ti,vinmin-threshold = <3900000>; /* uV */ monitored-battery = <&bat>; power-supplies = <&typec_pd>; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts index 8614c18b5998..767819cce886 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-nitrogen.dts @@ -142,7 +142,7 @@ #address-cells = <1>; #size-cells = <0>; - i2c1a: i2c1@0 { + i2c1a: i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -159,7 +159,7 @@ }; }; - i2c1b: i2c1@1 { + i2c1b: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; @@ -176,7 +176,7 @@ }; }; - i2c1c: i2c1@2 { + i2c1c: i2c@2 { reg = <2>; #address-cells = <1>; #size-cells = <0>; @@ -193,7 +193,7 @@ }; }; - i2c1d: i2c1@3 { + i2c1d: i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; @@ -222,7 +222,7 @@ #address-cells = <1>; #size-cells = <0>; - i2c4@0 { + i2c@0 { reg = <0>; #address-cells = <1>; #size-cells = <0>; @@ -257,14 +257,14 @@ }; }; - ddc_i2c_bus: i2c4@1 { + ddc_i2c_bus: i2c@1 { reg = <1>; #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; }; - i2c4@3 { + i2c@3 { reg = <3>; #address-cells = <1>; #size-cells = <0>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts index a3b9d615a3b4..e34045d10a12 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-phanbell.dts @@ -39,7 +39,7 @@ fan: gpio-fan { compatible = "gpio-fan"; - gpio-fan,speed-map = <0 0 8600 1>; + gpio-fan,speed-map = <0 0>, <8600 1>; gpios = <&gpio3 5 GPIO_ACTIVE_HIGH>; #cooling-cells = <2>; pinctrl-names = "default"; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts index 89cbec5c41b2..ec89b5adeb93 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-pico-pi.dts @@ -67,12 +67,12 @@ compatible = "rohm,bd71837"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_pmic>; + #clock-cells = <0>; clocks = <&pmic_osc>; clock-names = "osc"; clock-output-names = "pmic_clk"; interrupt-parent = <&gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - interrupt-names = "irq"; regulators { buck1: BUCK1 { diff --git a/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts b/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts index 6e6182709d22..eaa9d0c0fcc1 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-thor96.dts @@ -107,7 +107,7 @@ compatible = "mmc-pwrseq-simple"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_wifi_reg_on>; - gpio = <&gpio3 3 GPIO_ACTIVE_HIGH>; + reset-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; }; }; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso new file mode 100644 index 000000000000..306977d6ba0c --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx-lvds-tm070jvhg33.dtso @@ -0,0 +1,49 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2019-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +/dts-v1/; +/plugin/; + +#include <dt-bindings/gpio/gpio.h> + +&{/} { + compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq"; +}; + +&backlight_lvds { + status = "okay"; +}; + +&dphy { + status = "okay"; +}; + +&dsi_lvds_bridge { + status = "okay"; +}; + +&expander0 { + dsi-mux-oe-hog { + gpio-hog; + gpios = <10 GPIO_ACTIVE_LOW>; + output-high; + line-name = "DSI_MUX_OE#"; + }; +}; + +&lcdif { + status = "okay"; +}; + +&mipi_dsi { + status = "okay"; +}; + +&panel { + compatible = "tianma,tm070jvhg33"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts index 0d8def2766f5..b302daca4ce6 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts +++ b/arch/arm64/boot/dts/freescale/imx8mq-tqma8mq-mba8mx.dts @@ -11,6 +11,7 @@ / { model = "TQ-Systems GmbH i.MX8MQ TQMa8MQ on MBa8Mx"; compatible = "tq,imx8mq-tqma8mq-mba8mx", "tq,imx8mq-tqma8mq", "fsl,imx8mq"; + chassis-type = "embedded"; aliases { eeprom0 = &eeprom3; diff --git a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi index cb777b47baf9..0c960efd9b3d 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq-zii-ultra.dtsi @@ -15,7 +15,7 @@ stdout-path = &uart1; }; - mdio0: bitbang-mdio { + mdio0: mdio { compatible = "virtual,mdio-gpio"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_mdio_bitbang>, <&pinctrl_fec1_phy_reset>; diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 35f07dfb4ca8..c6dc3ba0d43b 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -225,6 +225,59 @@ }; }; + funnel { + /* + * non-configurable funnel don't show up on the AMBA + * bus. As such no need to add "arm,primecell". + */ + compatible = "arm,coresight-static-funnel"; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + ca_funnel_in_port0: endpoint { + remote-endpoint = <&etm0_out_port>; + }; + }; + + port@1 { + reg = <1>; + + ca_funnel_in_port1: endpoint { + remote-endpoint = <&etm1_out_port>; + }; + }; + + port@2 { + reg = <2>; + + ca_funnel_in_port2: endpoint { + remote-endpoint = <&etm2_out_port>; + }; + }; + + port@3 { + reg = <3>; + + ca_funnel_in_port3: endpoint { + remote-endpoint = <&etm3_out_port>; + }; + }; + }; + + out-ports { + port { + ca_funnel_out_port0: endpoint { + remote-endpoint = <&hugo_funnel_in_port0>; + }; + }; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; @@ -394,59 +447,6 @@ }; }; - funnel { - /* - * non-configurable funnel don't show up on the AMBA - * bus. As such no need to add "arm,primecell". - */ - compatible = "arm,coresight-static-funnel"; - - in-ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - - ca_funnel_in_port0: endpoint { - remote-endpoint = <&etm0_out_port>; - }; - }; - - port@1 { - reg = <1>; - - ca_funnel_in_port1: endpoint { - remote-endpoint = <&etm1_out_port>; - }; - }; - - port@2 { - reg = <2>; - - ca_funnel_in_port2: endpoint { - remote-endpoint = <&etm2_out_port>; - }; - }; - - port@3 { - reg = <3>; - - ca_funnel_in_port3: endpoint { - remote-endpoint = <&etm3_out_port>; - }; - }; - }; - - out-ports { - port { - ca_funnel_out_port0: endpoint { - remote-endpoint = <&hugo_funnel_in_port0>; - }; - }; - }; - }; - funnel@28c03000 { compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; reg = <0x28c03000 0x1000>; @@ -1649,6 +1649,7 @@ phys = <&usb3_phy0>, <&usb3_phy0>; phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg1>; + snps,parkmode-disable-ss-quirk; status = "disabled"; }; @@ -1680,6 +1681,7 @@ phys = <&usb3_phy1>, <&usb3_phy1>; phy-names = "usb2-phy", "usb3-phy"; power-domains = <&pgc_otg2>; + snps,parkmode-disable-ss-quirk; status = "disabled"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi index 1c6af9f549a8..4d6427fbe875 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-apalis.dtsi @@ -21,7 +21,6 @@ * this PHY model. Use delay on MAC side instead. */ &fec1 { - fsl,rgmii_txc_dly; phy-mode = "rgmii-rxid"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts index 0b34cc2250e1..6d50838ad17d 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qm-mek.dts @@ -47,6 +47,18 @@ status = "okay"; }; +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -118,6 +130,20 @@ >; }; + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QM_UART0_RTS_B_DMA_UART2_RX 0x06000020 + IMX8QM_UART0_CTS_B_DMA_UART2_TX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QM_M41_GPIO0_00_DMA_UART3_RX 0x06000020 + IMX8QM_M41_GPIO0_01_DMA_UART3_TX 0x06000020 + >; + }; + pinctrl_usdhc1: usdhc1grp { fsl,pins = < IMX8QM_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index e9b198c13b2f..69cb8676732e 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -44,6 +44,69 @@ }; }; +&edma2 { + reg = <0x5a1f0000 0x170000>; + #dma-cells = <3>; + dma-channels = <22>; + dma-channel-mask = <0xf00>; + interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ + <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, /* unused */ + <GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 440 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 441 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 442 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 443 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_DMA_0_CH0>, + <&pd IMX_SC_R_DMA_0_CH1>, + <&pd IMX_SC_R_DMA_0_CH2>, + <&pd IMX_SC_R_DMA_0_CH3>, + <&pd IMX_SC_R_DMA_0_CH4>, + <&pd IMX_SC_R_DMA_0_CH5>, + <&pd IMX_SC_R_DMA_0_CH6>, + <&pd IMX_SC_R_DMA_0_CH7>, + <&pd IMX_SC_R_DMA_0_CH8>, + <&pd IMX_SC_R_DMA_0_CH9>, + <&pd IMX_SC_R_DMA_0_CH10>, + <&pd IMX_SC_R_DMA_0_CH11>, + <&pd IMX_SC_R_DMA_0_CH12>, + <&pd IMX_SC_R_DMA_0_CH13>, + <&pd IMX_SC_R_DMA_0_CH14>, + <&pd IMX_SC_R_DMA_0_CH15>, + <&pd IMX_SC_R_DMA_0_CH16>, + <&pd IMX_SC_R_DMA_0_CH17>, + <&pd IMX_SC_R_DMA_0_CH18>, + <&pd IMX_SC_R_DMA_0_CH19>, + <&pd IMX_SC_R_DMA_0_CH20>, + <&pd IMX_SC_R_DMA_0_CH21>; + status = "okay"; +}; + +&edma3 { + power-domains = <&pd IMX_SC_R_DMA_1_CH0>, + <&pd IMX_SC_R_DMA_1_CH1>, + <&pd IMX_SC_R_DMA_1_CH2>, + <&pd IMX_SC_R_DMA_1_CH3>, + <&pd IMX_SC_R_DMA_1_CH4>, + <&pd IMX_SC_R_DMA_1_CH5>, + <&pd IMX_SC_R_DMA_1_CH6>, + <&pd IMX_SC_R_DMA_1_CH7>; +}; + &flexcan1 { fsl,clk-source = /bits/ 8 <1>; }; @@ -64,18 +127,26 @@ &lpuart0 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 13 0 0>, <&edma2 12 0 1>; + dma-names = "rx","tx"; }; &lpuart1 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 15 0 0>, <&edma2 14 0 1>; + dma-names = "rx","tx"; }; &lpuart2 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 17 0 0>, <&edma2 16 0 1>; + dma-names = "rx","tx"; }; &lpuart3 { compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + dmas = <&edma2 19 0 0>, <&edma2 18 0 1>; + dma-names = "rx","tx"; }; &i2c0 { diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi index 7764b4146e0a..2bbdacb1313f 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-img.dtsi @@ -8,5 +8,5 @@ }; &jpegenc { - compatible = "nxp,imx8qm-jpgdec", "nxp,imx8qxp-jpgenc"; + compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc"; }; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts index 7924b0969ad8..8360bb851ac0 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts +++ b/arch/arm64/boot/dts/freescale/imx8qxp-mek.dts @@ -31,7 +31,7 @@ }; gpio-sbu-mux { - compatible = "gpio-sbu-mux"; + compatible = "nxp,cbdtu02043", "gpio-sbu-mux"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_typec_mux>; select-gpios = <&lsio_gpio5 9 GPIO_ACTIVE_HIGH>; @@ -50,6 +50,10 @@ status = "okay"; }; +&dsp_reserved { + status = "okay"; +}; + &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; @@ -152,12 +156,6 @@ interrupt-parent = <&lsio_gpio1>; interrupts = <3 IRQ_TYPE_LEVEL_LOW>; - port { - typec_dr_sw: endpoint { - remote-endpoint = <&usb3_drd_sw>; - }; - }; - usb_con1: connector { compatible = "usb-c-connector"; label = "USB-C"; @@ -169,8 +167,17 @@ #address-cells = <1>; #size-cells = <0>; + port@0 { + reg = <0>; + + typec_dr_sw: endpoint { + remote-endpoint = <&usb3_drd_sw>; + }; + }; + port@1 { reg = <1>; + typec_con_ss: endpoint { remote-endpoint = <&usb3_data_ss>; }; @@ -187,6 +194,18 @@ status = "okay"; }; +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart2>; + status = "okay"; +}; + +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_lpuart3>; + status = "okay"; +}; + &mu_m0 { status = "okay"; }; @@ -340,6 +359,20 @@ >; }; + pinctrl_lpuart2: lpuart2grp { + fsl,pins = < + IMX8QXP_UART2_TX_ADMA_UART2_TX 0x06000020 + IMX8QXP_UART2_RX_ADMA_UART2_RX 0x06000020 + >; + }; + + pinctrl_lpuart3: lpuart3grp { + fsl,pins = < + IMX8QXP_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 + IMX8QXP_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 + >; + }; + pinctrl_typec: typecgrp { fsl,pins = < IMX8QXP_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 diff --git a/arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi new file mode 100644 index 000000000000..7894a3ab26d6 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8qxp-ss-vpu.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR X11) +/* + * Copyright 2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Alexander Stein + */ + +&vpu_core0 { + reg = <0x2d040000 0x10000>; +}; + +&vpu_core1 { + reg = <0x2d050000 0x10000>; +}; + +/delete-node/ &mu2_m0; +/delete-node/ &vpu_core2; diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi index c80c85a4b405..958267b33340 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -48,7 +48,6 @@ serial3 = &lpuart3; vpu-core0 = &vpu_core0; vpu-core1 = &vpu_core1; - vpu-core2 = &vpu_core2; }; cpus { @@ -184,6 +183,7 @@ dsp_reserved: dsp@92400000 { reg = <0 0x92400000 0 0x2000000>; no-map; + status = "disabled"; }; encoder_rpc: encoder-rpc@94400000 { @@ -317,6 +317,7 @@ }; #include "imx8qxp-ss-img.dtsi" +#include "imx8qxp-ss-vpu.dtsi" #include "imx8qxp-ss-adma.dtsi" #include "imx8qxp-ss-conn.dtsi" #include "imx8qxp-ss-lsio.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index 8a6596d5a581..c4a0082f30d3 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -360,7 +360,7 @@ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>, <&pcc4 IMX8ULP_CLK_FLEXSPI2>; - clock-names = "fspi", "fspi_en"; + clock-names = "fspi_en", "fspi"; assigned-clocks = <&pcc4 IMX8ULP_CLK_FLEXSPI2>; assigned-clock-parents = <&cgc1 IMX8ULP_CLK_SPLL3_PFD3_DIV2>; status = "disabled"; @@ -483,12 +483,13 @@ }; }; - gpioe: gpio@2d000080 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x2d000080 0x1000>, <0x2d000040 0x40>; + gpioe: gpio@2d000000 { + compatible = "fsl,imx8ulp-gpio"; + reg = <0x2d000000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&pcc4 IMX8ULP_CLK_RGPIOE>, @@ -497,12 +498,13 @@ gpio-ranges = <&iomuxc1 0 32 24>; }; - gpiof: gpio@2d010080 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x2d010080 0x1000>, <0x2d010040 0x40>; + gpiof: gpio@2d010000 { + compatible = "fsl,imx8ulp-gpio"; + reg = <0x2d010000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&pcc4 IMX8ULP_CLK_RGPIOF>, @@ -532,12 +534,13 @@ }; }; - gpiod: gpio@2e200080 { - compatible = "fsl,imx8ulp-gpio", "fsl,imx7ulp-gpio"; - reg = <0x2e200080 0x1000>, <0x2e200040 0x40>; + gpiod: gpio@2e200000 { + compatible = "fsl,imx8ulp-gpio"; + reg = <0x2e200000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&pcc5 IMX8ULP_CLK_RGPIOD>, diff --git a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi index 98202a437040..58ec0b399c4f 100644 --- a/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8x-colibri-iris-v2.dtsi @@ -23,11 +23,11 @@ pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lvds_converter &pinctrl_gpio_iris>; - pinctrl_enable_3v3_vmmc: enable_3v3_vmmc { + pinctrl_enable_3v3_vmmc: enable-3v3-vmmc-grp { fsl,pins = <IMX8QXP_SAI1_RXFS_LSIO_GPIO0_IO31 0x20>; /* SODIMM 100 */ }; - pinctrl_lvds_converter: lcd-lvds { + pinctrl_lvds_converter: lvds-converter-grp { fsl,pins = <IMX8QXP_FLEXCAN1_TX_LSIO_GPIO1_IO18 0x20>, /* SODIMM 55 */ /* 6B/8B mode. Select LOW - 8B mode (24bit) */ <IMX8QXP_FLEXCAN1_RX_LSIO_GPIO1_IO17 0x20>, /* SODIMM 63 */ diff --git a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts index cafd39130eb8..9921ea13ab48 100644 --- a/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts +++ b/arch/arm64/boot/dts/freescale/imx93-11x11-evk.dts @@ -76,6 +76,7 @@ regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; + off-on-delay-us = <12000>; enable-active-high; }; }; @@ -149,6 +150,12 @@ status = "okay"; }; +&lpuart5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart5>; + status = "okay"; +}; + &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; @@ -222,18 +229,28 @@ >; }; + pinctrl_uart5: uart5grp { + fsl,pins = < + MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e + MX93_PAD_DAP_TDI__LPUART5_RX 0x31e + MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e + MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e + >; + }; + + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe - MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe - MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe - MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe - MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe - MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe - MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe - MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe - MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe - MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe + MX93_PAD_SD1_CMD__USDHC1_CMD 0x400013fe + MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x400013fe + MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x400013fe + MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x400013fe + MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x400013fe + MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x400013fe + MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x400013fe + MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x400013fe + MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x400013fe MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe >; }; @@ -250,14 +267,15 @@ >; }; + /* need to config the SION for data and cmd pad, refer to ERR052021 */ pinctrl_usdhc2: usdhc2grp { fsl,pins = < MX93_PAD_SD2_CLK__USDHC2_CLK 0x15fe - MX93_PAD_SD2_CMD__USDHC2_CMD 0x13fe - MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe - MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe - MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe - MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe + MX93_PAD_SD2_CMD__USDHC2_CMD 0x400013fe + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x400013fe + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x400013fe + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x400013fe + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x400013fe MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e >; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts new file mode 100644 index 000000000000..af795ecf678b --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxca.dts @@ -0,0 +1,709 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2022-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Markus Niebel + * Author: Alexander Stein + */ +/dts-v1/; + +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/net/ti-dp83867.h> +#include <dt-bindings/pwm/pwm.h> + +#include "imx93-tqma9352.dtsi" + +/{ + model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa93xxCA starter kit"; + compatible = "tq,imx93-tqma9352-mba93xxca", + "tq,imx93-tqma9352", "fsl,imx93"; + chassis-type = "embedded"; + + chosen { + stdout-path = &lpuart1; + }; + + aliases { + eeprom0 = &eeprom0; + rtc0 = &pcf85063; + rtc1 = &bbnsm_rtc; + }; + + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pwms = <&tpm5 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v0>; + enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + + fan0: pwm-fan { + compatible = "pwm-fan"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwmfan>; + fan-supply = <®_pwm_fan>; + #cooling-cells = <2>; + /* typical 25 kHz -> 40.000 nsec */ + pwms = <&tpm6 0 40000 PWM_POLARITY_INVERTED>; + cooling-levels = <0 32 64 128 196 240>; + pulses-per-revolution = <2>; + interrupt-parent = <&gpio2>; + interrupts = <9 IRQ_TYPE_EDGE_FALLING>; + status = "disabled"; + }; + + gpio-keys { + compatible = "gpio-keys"; + autorepeat; + + switch-a { + label = "switcha"; + linux,code = <BTN_0>; + gpios = <&expander0 6 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + + switch-b { + label = "switchb"; + linux,code = <BTN_1>; + gpios = <&expander0 7 GPIO_ACTIVE_LOW>; + wakeup-source; + }; + }; + + gpio-leds { + compatible = "gpio-leds"; + + led-1 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_STATUS; + gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "default-on"; + }; + + led-2 { + color = <LED_COLOR_ID_AMBER>; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; + + iio-hwmon { + compatible = "iio-hwmon"; + io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_5v0: regulator-5v0 { + compatible = "regulator-fixed"; + regulator-name = "V_5V0_MB"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_12v0: regulator-12v0 { + compatible = "regulator-fixed"; + regulator-name = "V_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_1v5: regulator-mpcie-1v5 { + compatible = "regulator-fixed"; + regulator-name = "V_1V5_MPCIE"; + regulator-min-microvolt = <1500000>; + regulator-max-microvolt = <1500000>; + gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_mpcie_3v3: regulator-mpcie-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MPCIE"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + reg_pwm_fan: regulator-pwm-fan { + compatible = "regulator-fixed"; + regulator-name = "FAN_PWR"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + gpio = <&expander0 0 GPIO_ACTIVE_HIGH>; + enable-active-high; + vin-supply = <®_12v0>; + }; + + thermal-zones { + cpu-thermal { + trips { + cpu_active0: trip-active0 { + temperature = <40000>; + hysteresis = <5000>; + type = "active"; + }; + + cpu_active1: trip-active1 { + temperature = <48000>; + hysteresis = <3000>; + type = "active"; + }; + + cpu_active2: trip-active2 { + temperature = <60000>; + hysteresis = <10000>; + type = "active"; + }; + }; + + cooling-maps { + map1 { + trip = <&cpu_active0>; + cooling-device = <&fan0 1 1>; + }; + + map2 { + trip = <&cpu_active1>; + cooling-device = <&fan0 2 2>; + }; + + map3 { + trip = <&cpu_active2>; + cooling-device = <&fan0 3 3>; + }; + }; + }; + }; +}; + +&adc1 { + status = "okay"; +}; + +&eqos { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_eqos>; + status = "okay"; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ethphy_eqos: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_eqos_phy>; + reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy_fec>; + fsl,magic-packet; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <5000000>; + + ethphy_fec: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec_phy>; + reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; + reset-assert-us = <500000>; + reset-deassert-us = <50000>; + interrupt-parent = <&gpio3>; + interrupts = <27 IRQ_TYPE_EDGE_FALLING>; + enet-phy-lane-no-swap; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; + ti,dp83867-rxctrl-strap-quirk; + ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; + }; + }; +}; + +&flexcan1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&flexcan2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + xceiver-supply = <®_3v3>; + status = "okay"; +}; + +&gpio1 { + expander-irq-hog { + gpio-hog; + gpios = <12 GPIO_ACTIVE_LOW>; + input; + line-name = "PEX_INT#"; + }; + + tcpc-irq-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + input; + line-name = "USB_C_ALERT#"; + }; +}; + +&lpi2c3 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c3>; + pinctrl-1 = <&pinctrl_lpi2c3>; + status = "okay"; + + temperature-sensor@1c { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x1c>; + }; + + eeprom2: eeprom@54 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x54>; + pagesize = <16>; + vcc-supply = <®_3v3>; + }; + + expander0: gpio@70 { + compatible = "nxp,pca9538"; + reg = <0x70>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pexp_irq>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + interrupt-parent = <&gpio1>; + interrupts = <12 IRQ_TYPE_LEVEL_LOW>; + vcc-supply = <®_3v3>; + gpio-line-names = "FAN_PWR_EN", "MPCIE_WAKE#", + "MPCIE_1V5_EN", "MPCIE_3V3_EN", + "MPCIE_PERST#", "MPCIE_WDISABLE#", + "BUTTON_A#", "BUTTON_B#"; + + mpcie-wake-hog { + gpio-hog; + gpios = <1 GPIO_ACTIVE_LOW>; + input; + line-name = "MPCIE_WAKE#"; + }; + + /* + * Controls the mPCIE slot reset which is low active as + * reset signal. The output-low states, the signal is + * inactive, e.g. not in reset + */ + mpcie_rst_hog: mpcie-rst-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_PERST#"; + }; + + /* + * Controls the mPCIE slot WDISABLE pin which is low active + * as disable signal. The output-low states, the signal is + * inactive, e.g. not disabled + */ + mpcie_wdisable_hog: mpcie-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-low; + line-name = "MPCIE_WDISABLE#"; + }; + }; + + expander1: gpio@71 { + compatible = "nxp,pca9538"; + reg = <0x71>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", + "USB_RESET#", "", + "WLAN_PD#", "WLAN_W_DISABLE#", + "WLAN_PERST#", "12V_EN"; + + /* + * Controls the on board USB Hub reset which is low + * active as reset signal. The output-low states, the + * signal is inactive, e.g. no reset + */ + usb-reset-hog { + gpio-hog; + gpios = <2 GPIO_ACTIVE_LOW>; + output-low; + line-name = "USB_RESET#"; + }; + + /* + * Controls the WiFi card PD pin which is low active + * as power down signal. The output-high states, the signal + * is active, e.g. card is powered down + */ + wlan-pd-hog { + gpio-hog; + gpios = <4 GPIO_ACTIVE_LOW>; + output-high; + line-name = "WLAN_PD#"; + }; + + /* + * Controls the WiFi card disable pin which is low active + * as disable signal. The output-high states, the signal + * is active, e.g. card is disabled + */ + wlan-wdisable-hog { + gpio-hog; + gpios = <5 GPIO_ACTIVE_LOW>; + output-high; + line-name = "WLAN_W_DISABLE#"; + }; + + /* + * Controls the WiFi card reset pin which is low active + * as reset signal. The output-high states, the signal + * is active, e.g. card in reset + */ + wlan-perst-hog { + gpio-hog; + gpios = <6 GPIO_ACTIVE_LOW>; + output-high; + line-name = "WLAN_PERST#"; + }; + }; + + expander2: gpio@72 { + compatible = "nxp,pca9538"; + reg = <0x72>; + gpio-controller; + #gpio-cells = <2>; + vcc-supply = <®_3v3>; + gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", + "LCD_BLT_EN", "DP_EN", + "MIPI_CSI_EN", "MIPI_CSI_RST#", + "USER_LED1", "USER_LED2"; + }; +}; + +&lpi2c5 { + #address-cells = <1>; + #size-cells = <0>; + clock-frequency = <400000>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpi2c5>; + pinctrl-1 = <&pinctrl_lpi2c5>; + status = "okay"; +}; + +&lpspi6 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pinctrl_lpspi6>; + pinctrl-1 = <&pinctrl_lpspi6>; + status = "okay"; +}; + +&lpuart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&lpuart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + linux,rs485-enabled-at-boot-time; + status = "okay"; +}; + +/* disabled per default, console for M33 */ +&lpuart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + status = "disabled"; +}; + +&lpuart6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart6>; + status = "okay"; +}; + +&lpuart8 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart8>; + status = "okay"; +}; + +&tpm5 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm5>; +}; + +&tpm6 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tpm6>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; + pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; + cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; + vmmc-supply = <®_usdhc2_vmmc>; + bus-width = <4>; + no-sdio; + no-mmc; + disable-wp; + status = "okay"; +}; + +&iomuxc { + pinctrl_eqos: eqosgrp { + fsl,pins = < + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e + MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000051e + /* PD | FSEL_2 | DSE X6 */ + MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e + MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e + MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e + MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e + /* PD | FSEL_3 | DSE X6 */ + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e + MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e + MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e + MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e + MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e + >; + }; + + pinctrl_eqos_phy: eqosphygrp { + fsl,pins = < + MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1306 + >; + }; + + pinctrl_fec: fecgrp { + fsl,pins = < + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e + MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000051e + /* PD | FSEL_2 | DSE X6 */ + MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x57e + MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x57e + MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x57e + MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x57e + /* PD | FSEL_3 | DSE X6 */ + MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x5fe + MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x57e + /* PD | FSEL_2 | DSE X4 */ + MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e + MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e + MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e + MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e + MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e + /* PD | FSEL_3 | DSE X3 */ + MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e + >; + }; + + pinctrl_fec_phy: fecphygrp { + fsl,pins = < + MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1306 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x139e + MX93_PAD_PDM_CLK__CAN1_TX 0x139e + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX93_PAD_GPIO_IO25__CAN2_TX 0x139e + MX93_PAD_GPIO_IO27__CAN2_RX 0x139e + >; + }; + + pinctrl_lpi2c3: lpi2c3grp { + fsl,pins = < + MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e + MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e + >; + }; + + pinctrl_lpi2c5: lpi2c5grp { + fsl,pins = < + MX93_PAD_GPIO_IO22__LPI2C5_SDA 0x40000b9e + MX93_PAD_GPIO_IO23__LPI2C5_SCL 0x40000b9e + >; + }; + + pinctrl_lpspi6: lpspi6grp { + fsl,pins = < + MX93_PAD_GPIO_IO00__LPSPI6_PCS0 0x3fe + MX93_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe + MX93_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe + MX93_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe + >; + }; + + pinctrl_pexp_irq: pexpirqgrp { + fsl,pins = < + MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1306 + >; + }; + + pinctrl_pwmfan: pwmfangrp { + fsl,pins = < + MX93_PAD_GPIO_IO09__GPIO2_IO09 0x1306 + >; + }; + + pinctrl_tpm5: tpm5grp { + fsl,pins = < + MX93_PAD_GPIO_IO06__TPM5_CH0 0x57e + >; + }; + + pinctrl_tpm6: tpm6grp { + fsl,pins = < + MX93_PAD_GPIO_IO08__TPM6_CH0 0x57e + >; + }; + + pinctrl_typec: typecgrp { + fsl,pins = < + MX93_PAD_I2C2_SCL__GPIO1_IO02 0x1306 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX93_PAD_UART1_RXD__LPUART1_RX 0x31e + MX93_PAD_UART1_TXD__LPUART1_TX 0x31e + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX93_PAD_UART2_TXD__LPUART2_TX 0x31e + MX93_PAD_UART2_RXD__LPUART2_RX 0x31e + MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX93_PAD_GPIO_IO14__LPUART3_TX 0x31e + MX93_PAD_GPIO_IO15__LPUART3_RX 0x31e + >; + }; + + pinctrl_uart6: uart6grp { + fsl,pins = < + MX93_PAD_GPIO_IO04__LPUART6_TX 0x31e + MX93_PAD_GPIO_IO05__LPUART6_RX 0x31e + >; + }; + + pinctrl_uart8: uart8grp { + fsl,pins = < + MX93_PAD_GPIO_IO12__LPUART8_TX 0x31e + MX93_PAD_GPIO_IO13__LPUART8_RX 0x31e + >; + }; + + pinctrl_usdhc2_gpio: usdhc2gpiogrp { + fsl,pins = < + MX93_PAD_SD2_CD_B__GPIO3_IO00 0x31e + >; + }; + + pinctrl_usdhc2_hs: usdhc2hsgrp { + fsl,pins = < + /* HYS | PD | PU | FSEL_3 | DSE X5 */ + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17be + /* HYS | PD | PU | FSEL_3 | DSE X4 */ + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + /* HYS | PD | PU | FSEL_3 | DSE X3 */ + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x138e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x138e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x138e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x138e + /* PD | PU | FSEL_2 | DSE X3 */ + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e + >; + }; + + pinctrl_usdhc2_uhs: usdhc2uhsgrp { + fsl,pins = < + /* HYS | PD | PU | FSEL_3 | DSE X6 */ + MX93_PAD_SD2_CLK__USDHC2_CLK 0x17fe + /* HYS | PD | PU | FSEL_3 | DSE X4 */ + MX93_PAD_SD2_CMD__USDHC2_CMD 0x139e + MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x139e + MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x139e + MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x139e + MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x139e + /* PD | PU | FSEL_2 | DSE X3 */ + MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x50e + >; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts index f06139bdff97..eb3f4cfb6986 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352-mba93xxla.dts @@ -18,6 +18,7 @@ model = "TQ-Systems i.MX93 TQMa93xxLA on MBa93xxLA SBC"; compatible = "tq,imx93-tqma9352-mba93xxla", "tq,imx93-tqma9352", "fsl,imx93"; + chassis-type = "embedded"; chosen { stdout-path = &lpuart1; @@ -577,7 +578,7 @@ fsl,pins = < MX93_PAD_UART2_TXD__LPUART2_TX 0x31e MX93_PAD_UART2_RXD__LPUART2_RX 0x31e - MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x31e + MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x51e >; }; diff --git a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi index 1c71c08becde..f6e422dc2663 100644 --- a/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-tqma9352.dtsi @@ -81,7 +81,7 @@ &gpio1 { pmic-irq-hog { gpio-hog; - gpios = <2 GPIO_ACTIVE_LOW>; + gpios = <3 GPIO_ACTIVE_LOW>; input; line-name = "PMIC_IRQ#"; }; diff --git a/arch/arm64/boot/dts/freescale/imx93.dtsi b/arch/arm64/boot/dts/freescale/imx93.dtsi index 6f85a05ee7e1..8f2e7c42ad6e 100644 --- a/arch/arm64/boot/dts/freescale/imx93.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93.dtsi @@ -171,6 +171,18 @@ status = "disabled"; }; + mqs1: mqs1 { + compatible = "fsl,imx93-mqs"; + gpr = <&aonmix_ns_gpr>; + status = "disabled"; + }; + + mqs2: mqs2 { + compatible = "fsl,imx93-mqs"; + gpr = <&wakeupmix_gpr>; + status = "disabled"; + }; + soc@0 { compatible = "simple-bus"; #address-cells = <1>; @@ -185,7 +197,47 @@ #size-cells = <1>; ranges; - anomix_ns_gpr: syscon@44210000 { + edma1: dma-controller@44000000 { + compatible = "fsl,imx93-edma3"; + reg = <0x44000000 0x200000>; + #dma-cells = <3>; + dma-channels = <31>; + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, // 0: Reserved + <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, // 1: CANFD1 + <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, // 2: Reserved + <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, // 3: GPIO1 CH0 + <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, // 4: GPIO1 CH1 + <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, // 5: I3C1 TO Bus + <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, // 6: I3C1 From Bus + <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, // 7: LPI2C1 M TX + <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, // 8: LPI2C1 S TX + <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, // 9: LPI2C2 M RX + <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, // 10: LPI2C2 S RX + <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, // 11: LPSPI1 TX + <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, // 12: LPSPI1 RX + <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, // 13: LPSPI2 TX + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, // 14: LPSPI2 RX + <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, // 15: LPTMR1 + <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, // 16: LPUART1 TX + <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, // 17: LPUART1 RX + <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, // 18: LPUART2 TX + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, // 19: LPUART2 RX + <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, // 20: S400 + <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, // 21: SAI TX + <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, // 22: SAI RX + <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, // 23: TPM1 CH0/CH2 + <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, // 24: TPM1 CH1/CH3 + <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, // 25: TPM1 Overflow + <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, // 26: TMP2 CH0/CH2 + <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, // 27: TMP2 CH1/CH3 + <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, // 28: TMP2 Overflow + <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, // 29: PDM + <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>; // 30: ADC1 + clocks = <&clk IMX93_CLK_EDMA1_GATE>; + clock-names = "dma"; + }; + + aonmix_ns_gpr: syscon@44210000 { compatible = "fsl,imx93-aonmix-ns-syscfg", "syscon"; reg = <0x44210000 0x1000>; }; @@ -242,6 +294,19 @@ status = "disabled"; }; + i3c1: i3c-master@44330000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x44330000 0x10000>; + interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&clk IMX93_CLK_BUS_AON>, + <&clk IMX93_CLK_I3C1_GATE>, + <&clk IMX93_CLK_I3C1_SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c1: i2c@44340000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x44340000 0x10000>; @@ -296,6 +361,8 @@ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART1_GATE>; clock-names = "ipg"; + dmas = <&edma1 17 0 1>, <&edma1 16 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -305,6 +372,8 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART2_GATE>; clock-names = "ipg"; + dmas = <&edma1 19 0 1>, <&edma1 18 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -319,6 +388,20 @@ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&aonmix_ns_gpr 0x14 0>; + status = "disabled"; + }; + + sai1: sai@443b0000 { + compatible = "fsl,imx93-sai"; + reg = <0x443b0000 0x10000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI1_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI1_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma1 22 0 1>, <&edma1 21 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -350,6 +433,8 @@ #clock-cells = <1>; clocks = <&osc_32k>, <&osc_24m>, <&clk_ext1>; clock-names = "osc_32k", "osc_24m", "clk_ext1"; + assigned-clocks = <&clk IMX93_CLK_AUDIO_PLL>; + assigned-clock-rates = <393216000>; status = "okay"; }; @@ -372,19 +457,21 @@ compatible = "fsl,imx93-src-slice"; reg = <0x44462400 0x400>, <0x44465800 0x400>; #power-domain-cells = <0>; - clocks = <&clk IMX93_CLK_MEDIA_AXI>, + clocks = <&clk IMX93_CLK_NIC_MEDIA_GATE>, <&clk IMX93_CLK_MEDIA_APB>; }; }; - anatop: anatop@44480000 { - compatible = "fsl,imx93-anatop", "syscon"; + clock-controller@44480000 { + compatible = "fsl,imx93-anatop"; reg = <0x44480000 0x2000>; + #clock-cells = <1>; }; tmu: tmu@44482000 { compatible = "fsl,qoriq-tmu"; reg = <0x44482000 0x1000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_TMC_GATE>; little-endian; fsl,tmu-range = <0x800000da 0x800000e9 @@ -401,6 +488,21 @@ #thermal-sensor-cells = <1>; }; + micfil: micfil@44520000 { + compatible = "fsl,imx93-micfil"; + reg = <0x44520000 0x10000>; + interrupts = <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_PDM_IPG>, + <&clk IMX93_CLK_PDM_GATE>, + <&clk IMX93_CLK_AUDIO_PLL>; + clock-names = "ipg_clk", "ipg_clk_app", "pll8k"; + dmas = <&edma1 29 0 5>; + dma-names = "rx"; + status = "disabled"; + }; adc1: adc@44530000 { compatible = "nxp,imx93-adc"; @@ -423,6 +525,79 @@ #size-cells = <1>; ranges; + edma2: dma-controller@42000000 { + compatible = "fsl,imx93-edma4"; + reg = <0x42000000 0x210000>; + #dma-cells = <3>; + dma-channels = <64>; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_EDMA2_GATE>; + clock-names = "dma"; + }; + wakeupmix_gpr: syscon@42420000 { compatible = "fsl,imx93-wakeupmix-syscfg", "syscon"; reg = <0x42420000 0x1000>; @@ -496,6 +671,19 @@ status = "disabled"; }; + i3c2: i3c-master@42520000 { + compatible = "silvaco,i3c-master-v1"; + reg = <0x42520000 0x10000>; + interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; + #address-cells = <3>; + #size-cells = <0>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_I3C2_GATE>, + <&clk IMX93_CLK_I3C2_SLOW>; + clock-names = "pclk", "fast_clk", "slow_clk"; + status = "disabled"; + }; + lpi2c3: i2c@42530000 { compatible = "fsl,imx93-lpi2c", "fsl,imx7ulp-lpi2c"; reg = <0x42530000 0x10000>; @@ -550,6 +738,8 @@ interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART3_GATE>; clock-names = "ipg"; + dmas = <&edma2 18 0 1>, <&edma2 17 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -559,6 +749,8 @@ interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART4_GATE>; clock-names = "ipg"; + dmas = <&edma2 20 0 1>, <&edma2 19 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -568,6 +760,8 @@ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART5_GATE>; clock-names = "ipg"; + dmas = <&edma2 22 0 1>, <&edma2 21 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -577,6 +771,8 @@ interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART6_GATE>; clock-names = "ipg"; + dmas = <&edma2 24 0 1>, <&edma2 23 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -591,6 +787,7 @@ assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; assigned-clock-rates = <40000000>; fsl,clk-source = /bits/ 8 <0>; + fsl,stop-mode = <&wakeupmix_gpr 0x0c 2>; status = "disabled"; }; @@ -609,12 +806,59 @@ status = "disabled"; }; + sai2: sai@42650000 { + compatible = "fsl,imx93-sai"; + reg = <0x42650000 0x10000>; + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI2_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI2_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 59 0 1>, <&edma2 58 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + sai3: sai@42660000 { + compatible = "fsl,imx93-sai"; + reg = <0x42660000 0x10000>; + interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_SAI3_IPG>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_SAI3_GATE>, <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_DUMMY>; + clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; + dmas = <&edma2 61 0 1>, <&edma2 60 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + + xcvr: xcvr@42680000 { + compatible = "fsl,imx93-xcvr"; + reg = <0x42680000 0x800>, + <0x42680800 0x400>, + <0x42680c00 0x080>, + <0x42680e00 0x080>; + reg-names = "ram", "regs", "rxfifo", "txfifo"; + interrupts = <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clk IMX93_CLK_BUS_WAKEUP>, + <&clk IMX93_CLK_SPDIF_GATE>, + <&clk IMX93_CLK_DUMMY>, + <&clk IMX93_CLK_AUD_XCVR_GATE>; + clock-names = "ipg", "phy", "spba", "pll_ipg"; + dmas = <&edma2 65 0 1>, <&edma2 66 0 0>; + dma-names = "rx", "tx"; + status = "disabled"; + }; + lpuart7: serial@42690000 { compatible = "fsl,imx93-lpuart", "fsl,imx8ulp-lpuart", "fsl,imx7ulp-lpuart"; reg = <0x42690000 0x1000>; interrupts = <GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART7_GATE>; clock-names = "ipg"; + dmas = <&edma2 88 0 1>, <&edma2 87 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -624,6 +868,8 @@ interrupts = <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clk IMX93_CLK_LPUART8_GATE>; clock-names = "ipg"; + dmas = <&edma2 90 0 1>, <&edma2 89 0 0>; + dma-names = "rx", "tx"; status = "disabled"; }; @@ -741,7 +987,7 @@ <&clk IMX93_CLK_USDHC1_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <8>; - fsl,tuning-start-tap = <20>; + fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; status = "disabled"; }; @@ -755,7 +1001,7 @@ <&clk IMX93_CLK_USDHC2_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; - fsl,tuning-start-tap = <20>; + fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; status = "disabled"; }; @@ -818,18 +1064,19 @@ <&clk IMX93_CLK_USDHC3_GATE>; clock-names = "ipg", "ahb", "per"; bus-width = <4>; - fsl,tuning-start-tap = <20>; + fsl,tuning-start-tap = <1>; fsl,tuning-step = <2>; status = "disabled"; }; }; - gpio2: gpio@43810080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43810080 0x1000>, <0x43810040 0x40>; + gpio2: gpio@43810000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43810000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO2_GATE>, @@ -838,12 +1085,13 @@ gpio-ranges = <&iomuxc 0 4 30>; }; - gpio3: gpio@43820080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43820080 0x1000>, <0x43820040 0x40>; + gpio3: gpio@43820000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43820000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO3_GATE>, @@ -853,12 +1101,13 @@ <&iomuxc 26 34 2>, <&iomuxc 28 0 4>; }; - gpio4: gpio@43830080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x43830080 0x1000>, <0x43830040 0x40>; + gpio4: gpio@43830000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x43830000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO4_GATE>, @@ -867,12 +1116,13 @@ gpio-ranges = <&iomuxc 0 38 28>, <&iomuxc 28 36 2>; }; - gpio1: gpio@47400080 { - compatible = "fsl,imx93-gpio", "fsl,imx7ulp-gpio"; - reg = <0x47400080 0x1000>, <0x47400040 0x40>; + gpio1: gpio@47400000 { + compatible = "fsl,imx93-gpio", "fsl,imx8ulp-gpio"; + reg = <0x47400000 0x1000>; gpio-controller; #gpio-cells = <2>; - interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; + interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; interrupt-controller; #interrupt-cells = <2>; clocks = <&clk IMX93_CLK_GPIO1_GATE>, diff --git a/arch/arm64/boot/dts/freescale/mba8mx.dtsi b/arch/arm64/boot/dts/freescale/mba8mx.dtsi index 8a9fe5cdcc98..e2bc53b8d39a 100644 --- a/arch/arm64/boot/dts/freescale/mba8mx.dtsi +++ b/arch/arm64/boot/dts/freescale/mba8mx.dtsi @@ -8,6 +8,16 @@ /* TQ-Systems GmbH MBa8Mx baseboard */ / { + backlight_lvds: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm3 0 5000000 0>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + power-supply = <®_12v>; + enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; + status = "disabled"; + }; + beeper { compatible = "pwm-beeper"; pwms = <&pwm4 0 250000 0>; @@ -65,12 +75,45 @@ }; }; + gpio_delays: gpio-delays { + compatible = "gpio-delay"; + #gpio-cells = <3>; + gpio-controller; + gpios = <&expander0 6 GPIO_ACTIVE_HIGH>; + gpio-line-names = "LVDS_BRIDGE_EN_1V8"; + }; + + panel: panel-lvds { + /* + * Display is not fixed, so compatible has to be added from + * DT overlay + */ + backlight = <&backlight_lvds>; + power-supply = <®_vcc_3v3>; + status = "disabled"; + + port { + panel_in_lvds: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&lvds_bridge_out>; + }; + }; + }; + pcie0_refclk: pcie0-refclk { compatible = "fixed-clock"; #clock-cells = <0>; clock-frequency = <100000000>; }; + reg_12v: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "MBA8MX_12V"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-always-on; + }; + reg_hub_vbus: regulator-hub-vbus { compatible = "regulator-fixed"; regulator-name = "MBA8MX_HUB_VBUS"; @@ -157,6 +200,10 @@ interrupts = <9 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; + gpio-line-names = "", "", "", "", + "", "", "LVDS_BRIDGE_EN", "", + "", "", "", "", + "", "", "", ""; sd-mux-oe-hog { gpio-hog; @@ -227,6 +274,52 @@ scl-gpios = <&gpio5 18 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; sda-gpios = <&gpio5 19 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; status = "okay"; + + dsi_lvds_bridge: bridge@2d { + compatible = "ti,sn65dsi84"; + reg = <0x2d>; + enable-gpios = <&gpio_delays 0 130000 0>; + vcc-supply = <®_sn65dsi83_1v8>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + lvds_bridge_in: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&mipi_dsi_out>; + }; + }; + + port@2 { + reg = <2>; + + lvds_bridge_out: endpoint { + remote-endpoint = <&panel_in_lvds>; + }; + }; + }; + }; +}; + +&mipi_dsi { + samsung,burst-clock-frequency = <891000000>; + samsung,esc-clock-frequency = <20000000>; + + ports { + port@1 { + reg = <1>; + + mipi_dsi_out: endpoint { + data-lanes = <1 2 3 4>; + remote-endpoint = <&lvds_bridge_in>; + }; + }; + }; }; &pwm3 { diff --git a/arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi b/arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi new file mode 100644 index 000000000000..4c38dd541143 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/tqmls104xa-mbls10xxa-fman.dtsi @@ -0,0 +1,104 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2019,2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + * Device Tree Include file for MBLS10xxA from TQ (FMAN related sections) + */ + +#include <dt-bindings/net/ti-dp83867.h> + +&enet0 { + status = "disabled"; +}; + +&enet1 { + status = "disabled"; +}; + +&enet2 { + phy-handle = <&rgmii_phy1>; + phy-connection-type = "rgmii"; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enet3 { + phy-handle = <&rgmii_phy2>; + phy-connection-type = "rgmii"; + phy-mode = "rgmii-id"; + status = "okay"; +}; + +&enet4 { + status = "disabled"; +}; + +&enet5 { + status = "disabled"; +}; + +&enet6 { + status = "disabled"; +}; + +&mdio0 { + status = "okay"; + + qsgmii2_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + }; + + qsgmii2_phy2: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x01>; + }; + + qsgmii2_phy3: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x02>; + }; + + qsgmii2_phy4: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x03>; + }; + + rgmii_phy2: ethernet-phy@c { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0c>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; + + rgmii_phy1: ethernet-phy@e { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0e>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; + + qsgmii1_phy1: ethernet-phy@1c { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1c>; + }; + + qsgmii1_phy2: ethernet-phy@1d { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1d>; + }; + + qsgmii1_phy3: ethernet-phy@1e { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1e>; + }; + + qsgmii1_phy4: ethernet-phy@1f { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1f>; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi b/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi new file mode 100644 index 000000000000..2471bb109e8e --- /dev/null +++ b/arch/arm64/boot/dts/freescale/tqmls1088a-mbls10xxa-mc.dtsi @@ -0,0 +1,146 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + * Device Tree Include file for MBLS10xxA from TQ (MC related sections) + */ + +#include <dt-bindings/net/ti-dp83867.h> + +/ { + sfp1: sfp1 { + compatible = "sff,sfp"; + i2c-bus = <&sfp1_i2c>; + mod-def0-gpios = <&gpioexp2 2 GPIO_ACTIVE_LOW>; + los-gpios = <&gpioexp2 3 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&gpioexp2 0 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpioexp2 1 GPIO_ACTIVE_HIGH>; + }; + + sfp2: sfp2 { + compatible = "sff,sfp"; + i2c-bus = <&sfp2_i2c>; + mod-def0-gpios = <&gpioexp2 10 GPIO_ACTIVE_LOW>; + los-gpios = <&gpioexp2 11 GPIO_ACTIVE_HIGH>; + tx-fault-gpios = <&gpioexp2 8 GPIO_ACTIVE_HIGH>; + tx-disable-gpios = <&gpioexp2 9 GPIO_ACTIVE_HIGH>; + }; +}; + +&dpmac1 { + pcs-handle = <&pcs1>; +}; + +&dpmac2 { + pcs-handle = <&pcs2>; +}; + +&dpmac3 { + pcs-handle = <&pcs3_0>; +}; + +&dpmac4 { + pcs-handle = <&pcs3_1>; +}; + +&dpmac5 { + pcs-handle = <&pcs3_2>; +}; + +&dpmac6 { + pcs-handle = <&pcs3_3>; +}; + +&dpmac7 { + pcs-handle = <&pcs7_0>; +}; + +&dpmac8 { + pcs-handle = <&pcs7_1>; +}; + +&dpmac9 { + pcs-handle = <&pcs7_2>; +}; + +&dpmac10 { + pcs-handle = <&pcs7_3>; +}; + +&emdio1 { + status = "okay"; + + qsgmii2_phy1: ethernet-phy@0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x00>; + }; + + qsgmii2_phy2: ethernet-phy@1 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x01>; + }; + + qsgmii2_phy3: ethernet-phy@2 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x02>; + }; + + qsgmii2_phy4: ethernet-phy@3 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x03>; + }; + + rgmii_phy2: ethernet-phy@c { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0c>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; + + rgmii_phy1: ethernet-phy@e { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x0e>; + ti,rx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,tx-internal-delay = <DP83867_RGMIIDCTL_1_50_NS>; + ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_8_B_NIB>; + }; + + qsgmii1_phy1: ethernet-phy@1c { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1c>; + }; + + qsgmii1_phy2: ethernet-phy@1d { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1d>; + }; + + qsgmii1_phy3: ethernet-phy@1e { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1e>; + }; + + qsgmii1_phy4: ethernet-phy@1f { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0x1f>; + }; +}; + +&pcs_mdio1 { + status = "okay"; +}; + +&pcs_mdio2 { + status = "okay"; +}; + +&pcs_mdio3 { + status = "okay"; +}; + +&pcs_mdio7 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi b/arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi new file mode 100644 index 000000000000..65b4ed28a3d4 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/tqmls10xxa-mbls10xxa.dtsi @@ -0,0 +1,136 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + * Device Tree Include file for MBLS10xxA from TQ + */ + +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +/ { + gpio-keys-polled { + compatible = "gpio-keys-polled"; + poll-interval = <100>; + autorepeat; + + button-0 { + label = "button0"; + gpios = <&gpioexp3 5 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F1>; + }; + + button-1 { + label = "button1"; + gpios = <&gpioexp3 6 GPIO_ACTIVE_LOW>; + linux,code = <KEY_F2>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-user { + gpios = <&gpioexp3 13 GPIO_ACTIVE_LOW>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_HEARTBEAT; + linux,default-trigger = "heartbeat"; + }; + }; + + reg_3v3: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "V_3V3_MB"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&duart0 { + status = "okay"; +}; + +&duart1 { + status = "okay"; +}; + +&esdhc { + status = "okay"; +}; + +&i2c3 { + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9544"; + reg = <0x70>; + #address-cells = <1>; + #size-cells = <0>; + + i2c@0 { + reg = <0x0>; + #address-cells = <1>; + #size-cells = <0>; + + gpioexp1: gpio@20 { + compatible = "nxp,pca9555"; + reg = <0x20>; + vcc-supply = <®_3v3>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioexp2: gpio@21 { + compatible = "nxp,pca9555"; + reg = <0x21>; + vcc-supply = <®_3v3>; + gpio-controller; + #gpio-cells = <2>; + }; + + gpioexp3: gpio@22 { + compatible = "nxp,pca9555"; + reg = <0x22>; + vcc-supply = <®_3v3>; + gpio-controller; + #gpio-cells = <2>; + }; + }; + + sfp1_i2c: i2c@1 { + reg = <0x1>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + sfp2_i2c: i2c@2 { + reg = <0x2>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@3 { + reg = <0x3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&sata { + status = "okay"; +}; + +&usb0 { + status = "okay"; +}; + +&usb1 { + dr_mode = "otg"; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi b/arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi new file mode 100644 index 000000000000..138f8778afde --- /dev/null +++ b/arch/arm64/boot/dts/freescale/tqmls10xxa.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) +/* + * Copyright (c) 2018-2023 TQ-Systems GmbH <linux@ew.tq-group.com>, + * D-82229 Seefeld, Germany. + * Author: Gregor Herburger, Timo Herbrecher + * + * Device Tree Include file for TQMLs10xxA SoM of TQ + */ + +/ { + reg_vcc3v3: regulator-vcc3v3 { + compatible = "regulator-fixed"; + regulator-name = "VCC3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&i2c0 { + status = "okay"; + + temperature-sensor@18 { + compatible = "nxp,se97b", "jedec,jc-42.4-temp"; + reg = <0x18>; + }; + + eeprom@50 { + compatible = "nxp,se97b", "atmel,24c02"; + reg = <0x50>; + pagesize = <16>; + vcc-supply = <®_vcc3v3>; + read-only; + }; + + rtc@51 { + compatible = "nxp,pcf85063a"; + reg = <0x51>; + }; + + eeprom@57 { + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + vcc-supply = <®_vcc3v3>; + }; +}; + +&esdhc { + /* eSDHC or eMMC: set by bootloader */ + non-removable; + disable-wp; + mmc-hs200-1_8v; + sd-uhs-sdr104; + sd-uhs-sdr50; + sd-uhs-sdr25; + sd-uhs-sdr12; +}; |