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Diffstat (limited to 'arch/arm/boot/dts/uniphier-pro5.dtsi')
-rw-r--r--arch/arm/boot/dts/uniphier-pro5.dtsi36
1 files changed, 18 insertions, 18 deletions
diff --git a/arch/arm/boot/dts/uniphier-pro5.dtsi b/arch/arm/boot/dts/uniphier-pro5.dtsi
index 100edd7438d8..2af4fa19bf14 100644
--- a/arch/arm/boot/dts/uniphier-pro5.dtsi
+++ b/arch/arm/boot/dts/uniphier-pro5.dtsi
@@ -341,39 +341,39 @@
reg = <0x59801000 0x400>;
};
- sdctrl@59810000 {
+ syscon@59810000 {
compatible = "socionext,uniphier-pro5-sdctrl",
"simple-mfd", "syscon";
reg = <0x59810000 0x400>;
- sd_clk: clock {
+ sd_clk: clock-controller {
compatible = "socionext,uniphier-pro5-sd-clock";
#clock-cells = <1>;
};
- sd_rst: reset {
+ sd_rst: reset-controller {
compatible = "socionext,uniphier-pro5-sd-reset";
#reset-cells = <1>;
};
};
- perictrl@59820000 {
+ syscon@59820000 {
compatible = "socionext,uniphier-pro5-perictrl",
"simple-mfd", "syscon";
reg = <0x59820000 0x200>;
- peri_clk: clock {
+ peri_clk: clock-controller {
compatible = "socionext,uniphier-pro5-peri-clock";
#clock-cells = <1>;
};
- peri_rst: reset {
+ peri_rst: reset-controller {
compatible = "socionext,uniphier-pro5-peri-reset";
#reset-cells = <1>;
};
};
- soc-glue@5f800000 {
+ syscon@5f800000 {
compatible = "socionext,uniphier-pro5-soc-glue",
"simple-mfd", "syscon";
reg = <0x5f800000 0x2000>;
@@ -383,7 +383,7 @@
};
};
- soc-glue@5f900000 {
+ syscon@5f900000 {
compatible = "socionext,uniphier-pro5-soc-glue-debug",
"simple-mfd";
#address-cells = <1>;
@@ -455,17 +455,17 @@
interrupt-controller;
};
- sysctrl@61840000 {
+ syscon@61840000 {
compatible = "socionext,uniphier-pro5-sysctrl",
"simple-mfd", "syscon";
reg = <0x61840000 0x10000>;
- sys_clk: clock {
+ sys_clk: clock-controller {
compatible = "socionext,uniphier-pro5-clock";
#clock-cells = <1>;
};
- sys_rst: reset {
+ sys_rst: reset-controller {
compatible = "socionext,uniphier-pro5-reset";
#reset-cells = <1>;
};
@@ -493,7 +493,7 @@
#size-cells = <1>;
ranges = <0 0x65b00000 0x400>;
- usb0_rst: reset@0 {
+ usb0_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -512,7 +512,7 @@
resets = <&sys_rst 12>, <&sys_rst 14>;
};
- usb0_hsphy0: hs-phy@280 {
+ usb0_hsphy0: phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
@@ -523,7 +523,7 @@
vbus-supply = <&usb0_vbus0>;
};
- usb0_ssphy0: ss-phy@380 {
+ usb0_ssphy0: phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;
@@ -557,7 +557,7 @@
#size-cells = <1>;
ranges = <0 0x65d00000 0x400>;
- usb1_rst: reset@0 {
+ usb1_rst: reset-controller@0 {
compatible = "socionext,uniphier-pro5-usb3-reset";
reg = <0x0 0x4>;
#reset-cells = <1>;
@@ -585,7 +585,7 @@
resets = <&sys_rst 12>, <&sys_rst 15>;
};
- usb1_hsphy0: hs-phy@280 {
+ usb1_hsphy0: phy@280 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x280 0x10>;
#phy-cells = <0>;
@@ -596,7 +596,7 @@
vbus-supply = <&usb1_vbus0>;
};
- usb1_hsphy1: hs-phy@290 {
+ usb1_hsphy1: phy@290 {
compatible = "socionext,uniphier-pro5-usb3-hsphy";
reg = <0x290 0x10>;
#phy-cells = <0>;
@@ -607,7 +607,7 @@
vbus-supply = <&usb1_vbus1>;
};
- usb1_ssphy0: ss-phy@380 {
+ usb1_ssphy0: phy@380 {
compatible = "socionext,uniphier-pro5-usb3-ssphy";
reg = <0x380 0x10>;
#phy-cells = <0>;