diff options
| -rw-r--r-- | drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/core/dc.c | 3 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc.h | 10 | ||||
| -rw-r--r-- | drivers/gpu/drm/amd/display/dc/dc_types.h | 2 |
4 files changed, 16 insertions, 1 deletions
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 081d28a92bbe..917bd5ad3932 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1564,6 +1564,8 @@ static int amdgpu_dm_init(struct amdgpu_device *adev) init_data.flags.enable_mipi_converter_optimization = true; + init_data.dcn_reg_offsets = adev->reg_offset[DCE_HWIP][0]; + INIT_LIST_HEAD(&adev->dm.da_list); retrieve_dmi_info(&adev->dm); diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index 03bf4be81ea3..6039b3487d4f 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -862,6 +862,7 @@ static bool dc_construct_ctx(struct dc *dc, dc_ctx->dc_sink_id_count = 0; dc_ctx->dc_stream_id_count = 0; dc_ctx->dce_environment = init_params->dce_environment; + dc_ctx->dcn_reg_offsets = init_params->dcn_reg_offsets; /* Create logger */ @@ -1241,6 +1242,8 @@ struct dc *dc_create(const struct dc_init_data *init_params) dc->versions.dmcu_version = dc->res_pool->dmcu->dmcu_version; } + dc->dcn_reg_offsets = init_params->dcn_reg_offsets; + /* Populate versioning information */ dc->versions.dc_ver = DC_VER; diff --git a/drivers/gpu/drm/amd/display/dc/dc.h b/drivers/gpu/drm/amd/display/dc/dc.h index 1dca016b5782..faa22580852b 100644 --- a/drivers/gpu/drm/amd/display/dc/dc.h +++ b/drivers/gpu/drm/amd/display/dc/dc.h @@ -808,6 +808,8 @@ struct dc { const char *build_id; struct vm_helper *vm_helper; + + uint32_t *dcn_reg_offsets; }; enum frame_buffer_mode { @@ -847,6 +849,14 @@ struct dc_init_data { struct dpcd_vendor_signature vendor_signature; bool force_smu_not_present; + /* + * IP offset for run time initializaion of register addresses + * + * DCN3.5+ will fail dc_create() if these fields are null for them. They are + * applicable starting with DCN32/321 and are not used for ASICs upstreamed + * before them. + */ + uint32_t *dcn_reg_offsets; }; struct dc_callback_init { diff --git a/drivers/gpu/drm/amd/display/dc/dc_types.h b/drivers/gpu/drm/amd/display/dc/dc_types.h index 7e595310a4b8..077a93e81561 100644 --- a/drivers/gpu/drm/amd/display/dc/dc_types.h +++ b/drivers/gpu/drm/amd/display/dc/dc_types.h @@ -876,7 +876,7 @@ struct dc_context { #ifdef CONFIG_DRM_AMD_DC_HDCP struct cp_psp cp_psp; #endif - + uint32_t *dcn_reg_offsets; }; /* DSC DPCD capabilities */ |