diff options
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 16 | ||||
-rw-r--r-- | arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 16 |
2 files changed, 16 insertions, 16 deletions
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi index d8680ebef137..8ce4b6aae79d 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi @@ -880,7 +880,7 @@ }; }; - cluster1_core0_watchdog: wdt@c000000 { + cluster1_core0_watchdog: watchdog@c000000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -890,7 +890,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster1_core1_watchdog: wdt@c010000 { + cluster1_core1_watchdog: watchdog@c010000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -900,7 +900,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster1_core2_watchdog: wdt@c020000 { + cluster1_core2_watchdog: watchdog@c020000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc020000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -910,7 +910,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster1_core3_watchdog: wdt@c030000 { + cluster1_core3_watchdog: watchdog@c030000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc030000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -920,7 +920,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core0_watchdog: wdt@c100000 { + cluster2_core0_watchdog: watchdog@c100000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -930,7 +930,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core1_watchdog: wdt@c110000 { + cluster2_core1_watchdog: watchdog@c110000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -940,7 +940,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core2_watchdog: wdt@c120000 { + cluster2_core2_watchdog: watchdog@c120000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc120000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -950,7 +950,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core3_watchdog: wdt@c130000 { + cluster2_core3_watchdog: watchdog@c130000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc130000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi index 5695b43fba58..bde89de2576e 100644 --- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi +++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi @@ -389,7 +389,7 @@ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; }; - cluster1_core0_watchdog: wdt@c000000 { + cluster1_core0_watchdog: watchdog@c000000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -399,7 +399,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster1_core1_watchdog: wdt@c010000 { + cluster1_core1_watchdog: watchdog@c010000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc010000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -409,7 +409,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core0_watchdog: wdt@c100000 { + cluster2_core0_watchdog: watchdog@c100000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc100000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -419,7 +419,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster2_core1_watchdog: wdt@c110000 { + cluster2_core1_watchdog: watchdog@c110000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc110000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -429,7 +429,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster3_core0_watchdog: wdt@c200000 { + cluster3_core0_watchdog: watchdog@c200000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc200000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -439,7 +439,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster3_core1_watchdog: wdt@c210000 { + cluster3_core1_watchdog: watchdog@c210000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc210000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -449,7 +449,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster4_core0_watchdog: wdt@c300000 { + cluster4_core0_watchdog: watchdog@c300000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc300000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL @@ -459,7 +459,7 @@ clock-names = "wdog_clk", "apb_pclk"; }; - cluster4_core1_watchdog: wdt@c310000 { + cluster4_core1_watchdog: watchdog@c310000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc310000 0x0 0x1000>; clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL |