diff options
67 files changed, 4198 insertions, 267 deletions
diff --git a/Documentation/devicetree/bindings/arm/airoha.yaml b/Documentation/devicetree/bindings/arm/airoha.yaml index 3292c669ee11..7c38c08dbf3f 100644 --- a/Documentation/devicetree/bindings/arm/airoha.yaml +++ b/Documentation/devicetree/bindings/arm/airoha.yaml @@ -22,6 +22,10 @@ properties: - enum: - airoha,en7523-evb - const: airoha,en7523 + - items: + - enum: + - airoha,en7581-evb + - const: airoha,en7581 additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 09f9ffd3ff7b..1d4bb50fcd8d 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -85,12 +85,15 @@ properties: - const: mediatek,mt7629 - items: - enum: + - cudy,wr3000-v1 + - openwrt,one - xiaomi,ax3000t - const: mediatek,mt7981b - items: - enum: - acelink,ew-7886cax - bananapi,bpi-r3 + - bananapi,bpi-r3mini - mediatek,mt7986a-rfb - const: mediatek,mt7986a - items: @@ -293,6 +296,13 @@ properties: - const: google,tentacruel-sku327683 - const: google,tentacruel - const: mediatek,mt8186 + - description: Google Voltorb (Acer Chromebook 311 C723/C732T) + items: + - enum: + - google,voltorb-sku589824 + - google,voltorb-sku589825 + - const: google,voltorb + - const: mediatek,mt8186 - items: - enum: - mediatek,mt8186-evb @@ -342,6 +352,14 @@ properties: - const: google,tomato-rev3 - const: google,tomato - const: mediatek,mt8195 + - description: HP Dojo sku1, 3, 5, 7 (HP Chromebook x360 13b-ca0002sa) + items: + - const: google,dojo-sku7 + - const: google,dojo-sku5 + - const: google,dojo-sku3 + - const: google,dojo-sku1 + - const: google,dojo + - const: mediatek,mt8195 - items: - enum: - mediatek,mt8195-demo @@ -353,6 +371,12 @@ properties: - const: mediatek,mt8365 - items: - enum: + - mediatek,mt8390-evk + - const: mediatek,mt8390 + - const: mediatek,mt8188 + - items: + - enum: + - kontron,3-5-sbc-i1200 - mediatek,mt8395-evk - radxa,nio-12l - const: mediatek,mt8395 diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml index ba2014a8725c..a10326a9683d 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,mutex.yaml @@ -33,6 +33,7 @@ properties: - mediatek,mt8186-disp-mutex - mediatek,mt8186-mdp3-mutex - mediatek,mt8188-disp-mutex + - mediatek,mt8188-vpp-mutex - mediatek,mt8192-disp-mutex - mediatek,mt8195-disp-mutex - mediatek,mt8195-vpp-mutex diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index fbf47f0bacf1..eabc353b8512 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -338,6 +338,8 @@ patternProperties: description: Czech Technical University in Prague "^cubietech,.*": description: Cubietech, Ltd. + "^cudy,.*": + description: Shenzhen Cudy Technology Co., Ltd. "^cui,.*": description: CUI Devices "^cypress,.*": @@ -1082,6 +1084,8 @@ patternProperties: description: OpenPandora GmbH "^openrisc,.*": description: OpenRISC.io + "^openwrt,.*": + description: OpenWrt "^option,.*": description: Option NV "^oranth,.*": diff --git a/arch/arm64/boot/dts/Makefile b/arch/arm64/boot/dts/Makefile index 30dd6347a929..21cd3a87f385 100644 --- a/arch/arm64/boot/dts/Makefile +++ b/arch/arm64/boot/dts/Makefile @@ -1,5 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 subdir-y += actions +subdir-y += airoha subdir-y += allwinner subdir-y += altera subdir-y += amazon diff --git a/arch/arm64/boot/dts/airoha/Makefile b/arch/arm64/boot/dts/airoha/Makefile new file mode 100644 index 000000000000..ebea112ce1d7 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/Makefile @@ -0,0 +1,2 @@ +# SPDX-License-Identifier: GPL-2.0-only +dtb-$(CONFIG_ARCH_AIROHA) += en7581-evb.dtb diff --git a/arch/arm64/boot/dts/airoha/en7581-evb.dts b/arch/arm64/boot/dts/airoha/en7581-evb.dts new file mode 100644 index 000000000000..cf58e43dd5b2 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/en7581-evb.dts @@ -0,0 +1,26 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +/dts-v1/; + +/* Bootloader installs ATF here */ +/memreserve/ 0x80000000 0x200000; + +#include "en7581.dtsi" + +/ { + model = "Airoha EN7581 Evaluation Board"; + compatible = "airoha,en7581-evb", "airoha,en7581"; + + aliases { + serial0 = &uart1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + linux,usable-memory-range = <0x0 0x80200000 0x0 0x1fe00000>; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x2 0x00000000>; + }; +}; diff --git a/arch/arm64/boot/dts/airoha/en7581.dtsi b/arch/arm64/boot/dts/airoha/en7581.dtsi new file mode 100644 index 000000000000..55eb1762fb11 --- /dev/null +++ b/arch/arm64/boot/dts/airoha/en7581.dtsi @@ -0,0 +1,154 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) + +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + npu-binary@84000000 { + no-map; + reg = <0x0 0x84000000 0x0 0xa00000>; + }; + + npu-flag@84b0000 { + no-map; + reg = <0x0 0x84b00000 0x0 0x100000>; + }; + + npu-pkt@85000000 { + no-map; + reg = <0x0 0x85000000 0x0 0x1a00000>; + }; + + npu-phyaddr@86b00000 { + no-map; + reg = <0x0 0x86b00000 0x0 0x100000>; + }; + + npu-rxdesc@86d00000 { + no-map; + reg = <0x0 0x86d00000 0x0 0x100000>; + }; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + + core1 { + cpu = <&cpu1>; + }; + + core2 { + cpu = <&cpu2>; + }; + + core3 { + cpu = <&cpu3>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x0>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x1>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x2>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x3>; + enable-method = "psci"; + clock-frequency = <80000000>; + next-level-cache = <&l2>; + }; + + l2: l2-cache { + compatible = "cache"; + cache-size = <0x80000>; + cache-line-size = <64>; + cache-level = <2>; + cache-unified; + }; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&gic>; + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, + <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + + gic: interrupt-controller@9000000 { + compatible = "arm,gic-v3"; + interrupt-controller; + #interrupt-cells = <3>; + #address-cells = <1>; + #size-cells = <1>; + reg = <0x0 0x09000000 0x0 0x20000>, + <0x0 0x09080000 0x0 0x80000>, + <0x0 0x09400000 0x0 0x2000>, + <0x0 0x09500000 0x0 0x2000>, + <0x0 0x09600000 0x0 0x20000>; + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; + }; + + uart1: serial@1fbf0000 { + compatible = "ns16550"; + reg = <0x0 0x1fbf0000 0x0 0x30>; + reg-io-width = <4>; + reg-shift = <2>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <1843200>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index 37b4ca3a87c9..8fd7b2bb7a15 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -8,9 +8,12 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt6797-x20-dev.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-rfb1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7622-bananapi-bpi-r64.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-cudy-wr3000-v1.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-openwrt-one.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7981b-xiaomi-ax3000t.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-acelink-ew-7886cax.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-mini.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-emmc.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nand.dtbo dtb-$(CONFIG_ARCH_MEDIATEK) += mt7986a-bananapi-bpi-r3-nor.dtbo @@ -62,6 +65,8 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327681.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacool-sku327683.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262144.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-tentacruel-sku262148.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589824.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-corsola-voltorb-sku589825.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8186-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8188-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r1.dtb @@ -69,6 +74,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-hayato-r5-sku2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r0.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-asurada-spherion-r4.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-dojo-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r1.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r2.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-cherry-tomato-r3.dtb @@ -76,5 +82,11 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb + +# Device tree overlays support +DTC_FLAGS_mt7986a-bananapi-bpi-r3 := -@ +DTC_FLAGS_mt7986a-bananapi-bpi-r3-mini := -@ diff --git a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts index 234e3b23d7a8..c84c47c1352f 100644 --- a/arch/arm64/boot/dts/mediatek/mt2712-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt2712-evb.dts @@ -137,7 +137,7 @@ <MT2712_PIN_74_GBE_TXD0__FUNC_GBE_TXD0>, <MT2712_PIN_75_GBE_TXC__FUNC_GBE_TXC>, <MT2712_PIN_76_GBE_TXEN__FUNC_GBE_TXEN>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; }; rx_pins { pinmux = <MT2712_PIN_78_GBE_RXD3__FUNC_GBE_RXD3>, @@ -151,7 +151,7 @@ mdio_pins { pinmux = <MT2712_PIN_85_GBE_MDC__FUNC_GBE_MDC>, <MT2712_PIN_86_GBE_MDIO__FUNC_GBE_MDIO>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; input-enable; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts index 7364c7278276..91de920c2245 100644 --- a/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts +++ b/arch/arm64/boot/dts/mediatek/mt6795-sony-xperia-m5.dts @@ -288,25 +288,25 @@ <PINMUX_GPIO161__FUNC_MSDC0_DAT7>, <PINMUX_GPIO162__FUNC_MSDC0_CMD>; input-enable; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; pins-clk { pinmux = <PINMUX_GPIO163__FUNC_MSDC0_CLK>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; pins-rst { pinmux = <PINMUX_GPIO165__FUNC_MSDC0_RSTB>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; pins-ds { pinmux = <PINMUX_GPIO164__FUNC_MSDC0_DSL>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts index 224bb289660c..d12eac9b3eeb 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-bananapi-bpi-r64.dts @@ -149,9 +149,9 @@ #address-cells = <1>; #size-cells = <0>; - switch@0 { + switch@1f { compatible = "mediatek,mt7531"; - reg = <0>; + reg = <0x1f>; interrupt-controller; #interrupt-cells = <1>; interrupts-extended = <&pio 53 IRQ_TYPE_LEVEL_HIGH>; @@ -329,8 +329,8 @@ /* eMMC is shared pin with parallel NAND */ emmc_pins_default: emmc-pins-default { mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; + function = "emmc"; + groups = "emmc", "emmc_rst"; }; /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", diff --git a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts index 41629769bdc8..8c3e2e2578bc 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts +++ b/arch/arm64/boot/dts/mediatek/mt7622-rfb1.dts @@ -268,8 +268,8 @@ /* eMMC is shared pin with parallel NAND */ emmc_pins_default: emmc-pins-default { mux { - function = "emmc", "emmc_rst"; - groups = "emmc"; + function = "emmc"; + groups = "emmc", "emmc_rst"; }; /* "NDL0","NDL1","NDL2","NDL3","NDL4","NDL5","NDL6","NDL7", diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts b/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts new file mode 100644 index 000000000000..54101cc08a25 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7981b-cudy-wr3000-v1.dts @@ -0,0 +1,74 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; +#include <dt-bindings/input/input.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/leds/common.h> + +#include "mt7981b.dtsi" + +/ { + compatible = "cudy,wr3000-v1", "mediatek,mt7981b"; + model = "Cudy WR3000 V1"; + + memory@40000000 { + reg = <0 0x40000000 0 0x10000000>; + device_type = "memory"; + }; + + keys { + compatible = "gpio-keys"; + + key-wps { + label = "WPS"; + gpios = <&pio 0 GPIO_ACTIVE_LOW>; + linux,code = <KEY_WPS_BUTTON>; + }; + + key-reset { + label = "RESET"; + gpios = <&pio 1 GPIO_ACTIVE_LOW>; + linux,code = <KEY_RESTART>; + }; + }; + + leds { + compatible = "gpio-leds"; + + led-0 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_WAN; + gpios = <&pio 5 GPIO_ACTIVE_LOW>; + }; + + led-1 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_WLAN_2GHZ; + gpios = <&pio 6 GPIO_ACTIVE_LOW>; + }; + + led-2 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_WLAN_5GHZ; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + + led-3 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_LAN; + gpios = <&pio 9 GPIO_ACTIVE_LOW>; + }; + + led-4 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_STATUS; + gpios = <&pio 10 GPIO_ACTIVE_LOW>; + }; + + led-5 { + color = <LED_COLOR_ID_BLUE>; + function = LED_FUNCTION_WAN_ONLINE; + gpios = <&pio 11 GPIO_ACTIVE_LOW>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts new file mode 100644 index 000000000000..4f6cbb491287 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7981b-openwrt-one.dts @@ -0,0 +1,15 @@ +// SPDX-License-Identifier: GPL-2.0-only OR MIT + +/dts-v1/; + +#include "mt7981b.dtsi" + +/ { + compatible = "openwrt,one", "mediatek,mt7981b"; + model = "OpenWrt One"; + + memory@40000000 { + reg = <0 0x40000000 0 0x40000000>; + device_type = "memory"; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi index 4feff3d1c5f4..64aeeb24efac 100644 --- a/arch/arm64/boot/dts/mediatek/mt7981b.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7981b.dtsi @@ -2,6 +2,7 @@ #include <dt-bindings/clock/mediatek,mt7981-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/reset/mt7986-resets.h> / { compatible = "mediatek,mt7981b"; @@ -62,12 +63,19 @@ #clock-cells = <1>; }; - clock-controller@1001b000 { + topckgen: clock-controller@1001b000 { compatible = "mediatek,mt7981-topckgen", "syscon"; reg = <0 0x1001b000 0 0x1000>; #clock-cells = <1>; }; + watchdog: watchdog@1001c000 { + compatible = "mediatek,mt7986-wdt"; + reg = <0 0x1001c000 0 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + #reset-cells = <1>; + }; + clock-controller@1001e000 { compatible = "mediatek,mt7981-apmixedsys"; reg = <0 0x1001e000 0 0x1000>; @@ -78,20 +86,80 @@ compatible = "mediatek,mt7981-pwm"; reg = <0 0x10048000 0 0x1000>; clocks = <&infracfg CLK_INFRA_PWM_STA>, - <&infracfg CLK_INFRA_PWM_HCK>, - <&infracfg CLK_INFRA_PWM1_CK>, - <&infracfg CLK_INFRA_PWM2_CK>, - <&infracfg CLK_INFRA_PWM3_CK>; + <&infracfg CLK_INFRA_PWM_HCK>, + <&infracfg CLK_INFRA_PWM1_CK>, + <&infracfg CLK_INFRA_PWM2_CK>, + <&infracfg CLK_INFRA_PWM3_CK>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3"; #pwm-cells = <2>; }; + i2c@11007000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11007000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_I2C0_CK>, + <&infracfg CLK_INFRA_AP_DMA_CK>, + <&infracfg CLK_INFRA_I2C_MCK_CK>, + <&infracfg CLK_INFRA_I2C_PCK_CK>; + clock-names = "main", "dma", "arb", "pmic"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + pio: pinctrl@11d00000 { + compatible = "mediatek,mt7981-pinctrl"; + reg = <0 0x11d00000 0 0x1000>, + <0 0x11c00000 0 0x1000>, + <0 0x11c10000 0 0x1000>, + <0 0x11d20000 0 0x1000>, + <0 0x11e00000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11f00000 0 0x1000>, + <0 0x11f10000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rt", "iocfg_rm", "iocfg_rb", "iocfg_lb", + "iocfg_bl", "iocfg_tm", "iocfg_tl", "eint"; + interrupt-controller; + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + interrupt-parent = <&gic>; + gpio-ranges = <&pio 0 0 56>; + gpio-controller; + #gpio-cells = <2>; + #interrupt-cells = <2>; + }; + + efuse@11f20000 { + compatible = "mediatek,mt7981-efuse", "mediatek,efuse"; + reg = <0 0x11f20000 0 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + }; + clock-controller@15000000 { compatible = "mediatek,mt7981-ethsys", "syscon"; reg = <0 0x15000000 0 0x1000>; #clock-cells = <1>; #reset-cells = <1>; }; + + wifi@18000000 { + compatible = "mediatek,mt7981-wmac"; + reg = <0 0x18000000 0 0x1000000>, + <0 0x10003000 0 0x1000>, + <0 0x11d10000 0 0x1000>; + interrupts = <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 215 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_NETSYS_MCU_SEL>, + <&topckgen CLK_TOP_AP2CNN_HOST_SEL>; + clock-names = "mcu", "ap2conn"; + resets = <&watchdog MT7986_TOPRGU_CONSYS_SW_RST>; + reset-names = "consys"; + }; }; timer { diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso index 779dc6782bb1..047a8388811e 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-emmc.dtso @@ -9,21 +9,17 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <8>; - max-frequency = <200000000>; - cap-mmc-highspeed; - mmc-hs200-1_8v; - mmc-hs400-1_8v; - hs400-ds-delay = <0x14014>; - non-removable; - no-sd; - no-sdio; - status = "okay"; - }; - }; }; +&{/soc/mmc@11230000} { + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + hs400-ds-delay = <0x14014>; + non-removable; + no-sd; + no-sdio; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts new file mode 100644 index 000000000000..e2a2fea7adf0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-mini.dts @@ -0,0 +1,493 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2021 MediaTek Inc. + * Authors: Frank Wunderlich <[email protected]> + * Eric Woudstra <[email protected]> + * Tianling Shen <[email protected]> + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/mt65xx.h> + +#include "mt7986a.dtsi" + +/ { + model = "Bananapi BPI-R3 Mini"; + chassis-type = "embedded"; + compatible = "bananapi,bpi-r3mini", "mediatek,mt7986a"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + dcin: regulator-12v { + compatible = "regulator-fixed"; + regulator-name = "12vd"; + regulator-min-microvolt = <12000000>; + regulator-max-microvolt = <12000000>; + regulator-boot-on; + regulator-always-on; + }; + + fan: pwm-fan { + compatible = "pwm-fan"; + #cooling-cells = <2>; + /* + * The signal is inverted on this board and the PWM driver + * does not support polarity inversion. + */ + /* cooling level (0, 1, 2) */ + cooling-levels = <255 96 0>; + pwms = <&pwm 0 10000>; + }; + + reg_1p8v: regulator-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1.8vd"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + reg_3p3v: regulator-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3.3vd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + vin-supply = <&dcin>; + }; + + usb_vbus: regulator-5v { + compatible = "regulator-fixed"; + regulator-name = "usb_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpios = <&pio 20 GPIO_ACTIVE_LOW>; + regulator-boot-on; + }; + + en8811_a: regulator-phy1 { + compatible = "regulator-fixed"; + regulator-name = "phy1"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 16 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + en8811_b: regulator-phy2 { + compatible = "regulator-fixed"; + regulator-name = "phy2"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 17 GPIO_ACTIVE_LOW>; + regulator-always-on; + }; + + leds { + compatible = "gpio-leds"; + + green_led: led-0 { + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_POWER; + gpios = <&pio 19 GPIO_ACTIVE_HIGH>; + default-state = "on"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + + reset-key { + label = "reset"; + linux,code = <KEY_RESTART>; + gpios = <&pio 7 GPIO_ACTIVE_LOW>; + }; + }; + +}; + +&cpu_thermal { + cooling-maps { + map0 { + /* active: set fan to cooling level 2 */ + cooling-device = <&fan 2 2>; + trip = <&cpu_trip_active_high>; + }; + + map1 { + /* active: set fan to cooling level 1 */ + cooling-device = <&fan 1 1>; + trip = <&cpu_trip_active_med>; + }; + + map2 { + /* active: set fan to cooling level 0 */ + cooling-device = <&fan 0 0>; + trip = <&cpu_trip_active_low>; + }; + }; +}; + +&crypto { + status = "okay"; +}; + +ð { + status = "okay"; + + gmac0: mac@0 { + compatible = "mediatek,eth-mac"; + reg = <0>; + phy-mode = "2500base-x"; + phy-handle = <&phy0>; + }; + + gmac1: mac@1 { + compatible = "mediatek,eth-mac"; + reg = <1>; + phy-mode = "2500base-x"; + phy-handle = <&phy1>; + }; + + mdio: mdio-bus { + #address-cells = <1>; + #size-cells = <0>; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-1 = <&mmc0_pins_uhs>; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; +}; + + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c_pins>; + status = "okay"; + + /* MAC Address EEPROM */ + eeprom@50 { + compatible = "atmel,24c02"; + reg = <0x50>; + + address-width = <8>; + pagesize = <8>; + size = <256>; + }; +}; + +&mdio { + phy0: ethernet-phy@14 { + reg = <14>; + interrupts-extended = <&pio 48 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 49 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + full-duplex; + pause; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { /* en8811_a_gpio5 */ + reg = <0>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_LAN; + function-enumerator = <1>; + default-state = "keep"; + }; + led@1 { /* en8811_a_gpio4 */ + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_LAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; + }; + + phy1: ethernet-phy@15 { + reg = <15>; + interrupts-extended = <&pio 46 IRQ_TYPE_EDGE_FALLING>; + reset-gpios = <&pio 47 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <20000>; + phy-mode = "2500base-x"; + full-duplex; + pause; + airoha,pnswap-rx; + + leds { + #address-cells = <1>; + #size-cells = <0>; + + led@0 { /* en8811_b_gpio5 */ + reg = <0>; + color = <LED_COLOR_ID_YELLOW>; + function = LED_FUNCTION_WAN; + function-enumerator = <1>; + default-state = "keep"; + }; + led@1 { /* en8811_b_gpio4 */ + reg = <1>; + color = <LED_COLOR_ID_GREEN>; + function = LED_FUNCTION_WAN; + function-enumerator = <2>; + default-state = "keep"; + }; + }; + }; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins>; + status = "okay"; +}; + +&pcie_phy { + status = "okay"; +}; + +&pio { + i2c_pins: i2c-pins { + mux { + function = "i2c"; + groups = "i2c"; + }; + }; + + mmc0_pins_default: mmc0-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + mmc0_pins_uhs: mmc0-uhs-pins { + mux { + function = "emmc"; + groups = "emmc_51"; + }; + conf-cmd-dat { + pins = "EMMC_DATA_0", "EMMC_DATA_1", "EMMC_DATA_2", + "EMMC_DATA_3", "EMMC_DATA_4", "EMMC_DATA_5", + "EMMC_DATA_6", "EMMC_DATA_7", "EMMC_CMD"; + input-enable; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + conf-clk { + pins = "EMMC_CK"; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-ds { + pins = "EMMC_DSL"; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; /* pull-down 50K */ + }; + conf-rst { + pins = "EMMC_RSTB"; + drive-strength = <4>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; /* pull-up 10K */ + }; + }; + + pcie_pins: pcie-pins { + mux { + function = "pcie"; + groups = "pcie_clk", "pcie_wake", "pcie_pereset"; + }; + }; + + pwm_pins: pwm-pins { + mux { + function = "pwm"; + groups = "pwm0"; + }; + }; + + spi_flash_pins: spi-flash-pins { + mux { + function = "spi"; + groups = "spi0", "spi0_wp_hold"; + }; + }; + + usb_ngff_pins: usb-ngff-pins { + ngff-gnss-off-conf { + pins = "GPIO_6"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-pe-rst-conf { + pins = "GPIO_7"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-wwan-off-conf { + pins = "GPIO_8"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-pwr-off-conf { + pins = "GPIO_9"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-rst-conf { + pins = "GPIO_10"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + ngff-coex-conf { + pins = "SPI1_CS"; + drive-strength = <8>; + mediatek,pull-up-adv = <1>; + }; + }; + + wf_2g_5g_pins: wf-2g-5g-pins { + mux { + function = "wifi"; + groups = "wf_2g", "wf_5g"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_dbdc_pins: wf-dbdc-pins { + mux { + function = "wifi"; + groups = "wf_dbdc"; + }; + conf { + pins = "WF0_HB1", "WF0_HB2", "WF0_HB3", "WF0_HB4", + "WF0_HB0", "WF0_HB0_B", "WF0_HB5", "WF0_HB6", + "WF0_HB7", "WF0_HB8", "WF0_HB9", "WF0_HB10", + "WF0_TOP_CLK", "WF0_TOP_DATA", "WF1_HB1", + "WF1_HB2", "WF1_HB3", "WF1_HB4", "WF1_HB0", + "WF1_HB5", "WF1_HB6", "WF1_HB7", "WF1_HB8", + "WF1_TOP_CLK", "WF1_TOP_DATA"; + drive-strength = <4>; + }; + }; + + wf_led_pins: wf-led-pins { + mux { + function = "led"; + groups = "wifi_led"; + }; + }; +}; + +&pwm { + pinctrl-names = "default"; + pinctrl-0 = <&pwm_pins>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi_flash_pins>; + status = "okay"; + + flash@0 { + compatible = "spi-nand"; + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + + spi-max-frequency = <20000000>; + spi-tx-bus-width = <4>; + spi-rx-bus-width = <4>; + }; +}; + +&ssusb { + pinctrl-names = "default"; + pinctrl-0 = <&usb_ngff_pins>; + vusb33-supply = <®_3p3v>; + vbus-supply = <&usb_vbus>; + status = "okay"; +}; + +&trng { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&usb_phy { + status = "okay"; +}; + +&watchdog { + status = "okay"; +}; + +&wifi { + status = "okay"; + pinctrl-names = "default", "dbdc"; + pinctrl-0 = <&wf_2g_5g_pins>, <&wf_led_pins>; + pinctrl-1 = <&wf_dbdc_pins>, <&wf_led_pins>; + + led { + led-active-low; + }; +}; + diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso index 7b97c5c91bd0..24398f8a7da4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nand.dtso @@ -9,46 +9,44 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; +}; + +&{/soc/spi@1100a000} { + #address-cells = <1>; + #size-cells = <0>; + + spi_nand: flash@0 { + compatible = "spi-nand"; + reg = <0>; + spi-max-frequency = <10000000>; + spi-tx-buswidth = <4>; + spi-rx-buswidth = <4>; - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; - #size-cells = <0>; - spi_nand: flash@0 { - compatible = "spi-nand"; - reg = <0>; - spi-max-frequency = <10000000>; - spi-tx-buswidth = <4>; - spi-rx-buswidth = <4>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x100000>; - read-only; - }; - - partition@100000 { - label = "reserved"; - reg = <0x100000 0x280000>; - }; - - partition@380000 { - label = "fip"; - reg = <0x380000 0x200000>; - read-only; - }; - - partition@580000 { - label = "ubi"; - reg = <0x580000 0x7a80000>; - }; - }; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x100000>; + read-only; + }; + + partition@100000 { + label = "reserved"; + reg = <0x100000 0x280000>; + }; + + partition@380000 { + label = "fip"; + reg = <0x380000 0x200000>; + read-only; + }; + + partition@580000 { + label = "ubi"; + reg = <0x580000 0x7a80000>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso index e48881be4ed6..6a0d529b54ac 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-nor.dtso @@ -9,54 +9,52 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; +}; + +&{/soc/spi@1100a000} { + #address-cells = <1>; + #size-cells = <0>; - fragment@0 { - target-path = "/soc/spi@1100a000"; - __overlay__ { + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <10000000>; + + partitions { + compatible = "fixed-partitions"; #address-cells = <1>; - #size-cells = <0>; - flash@0 { - compatible = "jedec,spi-nor"; - reg = <0>; - spi-max-frequency = <10000000>; - - partitions { - compatible = "fixed-partitions"; - #address-cells = <1>; - #size-cells = <1>; - - partition@0 { - label = "bl2"; - reg = <0x0 0x40000>; - read-only; - }; - - partition@40000 { - label = "u-boot-env"; - reg = <0x40000 0x40000>; - }; - - partition@80000 { - label = "reserved2"; - reg = <0x80000 0x80000>; - }; - - partition@100000 { - label = "fip"; - reg = <0x100000 0x80000>; - read-only; - }; - - partition@180000 { - label = "recovery"; - reg = <0x180000 0xa80000>; - }; - - partition@c00000 { - label = "fit"; - reg = <0xc00000 0x1400000>; - }; - }; + #size-cells = <1>; + + partition@0 { + label = "bl2"; + reg = <0x0 0x40000>; + read-only; + }; + + partition@40000 { + label = "u-boot-env"; + reg = <0x40000 0x40000>; + }; + + partition@80000 { + label = "reserved2"; + reg = <0x80000 0x80000>; + }; + + partition@100000 { + label = "fip"; + reg = <0x100000 0x80000>; + read-only; + }; + + partition@180000 { + label = "recovery"; + reg = <0x180000 0xa80000>; + }; + + partition@c00000 { + label = "fit"; + reg = <0xc00000 0x1400000>; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso index f623bce075ce..d9e01967acc4 100644 --- a/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso +++ b/arch/arm64/boot/dts/mediatek/mt7986a-bananapi-bpi-r3-sd.dtso @@ -9,15 +9,11 @@ / { compatible = "bananapi,bpi-r3", "mediatek,mt7986a"; - - fragment@0 { - target-path = "/soc/mmc@11230000"; - __overlay__ { - bus-width = <4>; - max-frequency = <52000000>; - cap-sd-highspeed; - status = "okay"; - }; - }; }; +&{/soc/mmc@11230000} { + bus-width = <4>; + max-frequency = <52000000>; + cap-sd-highspeed; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi index bba97de4fb44..aa728331e876 100644 --- a/arch/arm64/boot/dts/mediatek/mt7988a.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7988a.dtsi @@ -1,6 +1,8 @@ // SPDX-License-Identifier: GPL-2.0-only OR MIT +#include <dt-bindings/clock/mediatek,mt7988-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> / { compatible = "mediatek,mt7988a"; @@ -78,7 +80,7 @@ #interrupt-cells = <3>; }; - clock-controller@10001000 { + infracfg: clock-controller@10001000 { compatible = "mediatek,mt7988-infracfg", "syscon"; reg = <0 0x10001000 0 0x1000>; #clock-cells = <1>; @@ -103,6 +105,92 @@ #clock-cells = <1>; }; + pwm@10048000 { + compatible = "mediatek,mt7988-pwm"; + reg = <0 0x10048000 0 0x1000>; + clocks = <&infracfg CLK_INFRA_66M_PWM_BCK>, + <&infracfg CLK_INFRA_66M_PWM_HCK>, + <&infracfg CLK_INFRA_66M_PWM_CK1>, + <&infracfg CLK_INFRA_66M_PWM_CK2>, + <&infracfg CLK_INFRA_66M_PWM_CK3>, + <&infracfg CLK_INFRA_66M_PWM_CK4>, + <&infracfg CLK_INFRA_66M_PWM_CK5>, + <&infracfg CLK_INFRA_66M_PWM_CK6>, + <&infracfg CLK_INFRA_66M_PWM_CK7>, + <&infracfg CLK_INFRA_66M_PWM_CK8>; + clock-names = "top", "main", "pwm1", "pwm2", "pwm3", + "pwm4", "pwm5", "pwm6", "pwm7", "pwm8"; + #pwm-cells = <2>; + status = "disabled"; + }; + + i2c@11003000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11003000 0 0x1000>, + <0 0x10217080 0 0x80>; + interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@11004000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11004000 0 0x1000>, + <0 0x10217100 0 0x80>; + interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c@11005000 { + compatible = "mediatek,mt7981-i2c"; + reg = <0 0x11005000 0 0x1000>, + <0 0x10217180 0 0x80>; + interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_I2C_BCK>, + <&infracfg CLK_INFRA_66M_AP_DMA_BCK>; + clock-names = "main", "dma"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + usb@11190000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11190000 0 0x2e00>, + <0 0x11193e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_USB_SYS>, + <&infracfg CLK_INFRA_USB_REF>, + <&infracfg CLK_INFRA_66M_USB_HCK>, + <&infracfg CLK_INFRA_133M_USB_HCK>, + <&infracfg CLK_INFRA_USB_XHCI>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + }; + + usb@11200000 { + compatible = "mediatek,mt7988-xhci", "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x2e00>, + <0 0x11203e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&infracfg CLK_INFRA_USB_SYS_CK_P1>, + <&infracfg CLK_INFRA_USB_CK_P1>, + <&infracfg CLK_INFRA_66M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_133M_USB_HCK_CK_P1>, + <&infracfg CLK_INFRA_USB_XHCI_CK_P1>; + clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck", "xhci_ck"; + }; + clock-controller@11f40000 { compatible = "mediatek,mt7988-xfi-pll"; reg = <0 0x11f40000 0 0x1000>; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi index 90cbbc18a483..8d1cbc92bce3 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm-hana.dtsi @@ -27,6 +27,15 @@ hid-descr-addr = <0x0020>; interrupts-extended = <&pio 88 IRQ_TYPE_LEVEL_LOW>; }; + + /* Lenovo Ideapad C330 uses G2Touch touchscreen as a 2nd source touchscreen */ + touchscreen@40 { + compatible = "hid-over-i2c"; + reg = <0x40>; + hid-descr-addr = <0x0001>; + interrupt-parent = <&pio>; + interrupts = <88 IRQ_TYPE_LEVEL_LOW>; + }; }; &i2c4 { diff --git a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi index 6d962d437e02..b4d85147b77b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173-elm.dtsi @@ -1134,12 +1134,6 @@ rtc: mt6397rtc { compatible = "mediatek,mt6397-rtc"; }; - - syscfg_pctl_pmic: syscon@c000 { - compatible = "mediatek,mt6397-pctl-pmic-syscfg", - "syscon"; - reg = <0 0x0000c000 0 0x0108>; - }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts index 3fab21f59d18..bb4671c18e3b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8173-evb.dts @@ -213,14 +213,14 @@ <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; input-enable; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; pins_clk { pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; bias-pull-down; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; }; pins_insert { @@ -241,13 +241,13 @@ <MT8173_PIN_64_MSDC0_DAT7__FUNC_MSDC0_DAT7>, <MT8173_PIN_66_MSDC0_CMD__FUNC_MSDC0_CMD>; input-enable; - drive-strength = <MTK_DRIVE_2mA>; + drive-strength = <2>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; pins_clk { pinmux = <MT8173_PIN_65_MSDC0_CLK__FUNC_MSDC0_CLK>; - drive-strength = <MTK_DRIVE_2mA>; + drive-strength = <2>; bias-pull-down = <MTK_PUPD_SET_R1R0_01>; }; @@ -265,13 +265,13 @@ <MT8173_PIN_76_MSDC1_DAT3__FUNC_MSDC1_DAT3>, <MT8173_PIN_78_MSDC1_CMD__FUNC_MSDC1_CMD>; input-enable; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-up = <MTK_PUPD_SET_R1R0_10>; }; pins_clk { pinmux = <MT8173_PIN_77_MSDC1_CLK__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_4mA>; + drive-strength = <4>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts index 681deddffc2a..f04baea5d6cb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-evb.dts @@ -160,7 +160,6 @@ pinmux = <PINMUX_GPIO82__FUNC_SDA0>, <PINMUX_GPIO83__FUNC_SCL0>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -169,7 +168,6 @@ pinmux = <PINMUX_GPIO81__FUNC_SDA1>, <PINMUX_GPIO84__FUNC_SCL1>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -178,7 +176,6 @@ pinmux = <PINMUX_GPIO103__FUNC_SCL2>, <PINMUX_GPIO104__FUNC_SDA2>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -187,7 +184,6 @@ pinmux = <PINMUX_GPIO50__FUNC_SCL3>, <PINMUX_GPIO51__FUNC_SDA3>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -196,7 +192,6 @@ pinmux = <PINMUX_GPIO105__FUNC_SCL4>, <PINMUX_GPIO106__FUNC_SDA4>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -205,7 +200,6 @@ pinmux = <PINMUX_GPIO48__FUNC_SCL5>, <PINMUX_GPIO49__FUNC_SDA5>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi index 8b57706ac814..586eee79c73c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-audio-da7219.dtsi @@ -27,7 +27,7 @@ dlg,btn-cfg = <50>; dlg,mic-det-thr = <500>; dlg,jack-ins-deb = <20>; - dlg,jack-det-rate = "32ms_64ms"; + dlg,jack-det-rate = "32_64"; dlg,jack-rem-deb = <1>; dlg,a-d-btn-thr = <0xa>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts index 072133fb0f01..f34964afe39b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-cozmo.dts @@ -9,6 +9,7 @@ / { model = "Google cozmo board"; + chassis-type = "laptop"; compatible = "google,cozmo", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts index b595622e7bee..72852b760038 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku1.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku1 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku1", "google,fennel", "mediatek,mt8183"; pwmleds { diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts index 5a1c39318a6c..757d0afd14fb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku6.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku6 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku6", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts index 3ea4fdb40118..6641b087e7c5 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel-sku7.dts @@ -9,6 +9,7 @@ / { model = "Google fennel sku7 board"; + chassis-type = "convertible"; compatible = "google,fennel-sku7", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts index 3fc5a6181d7e..877256eab262 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14-sku2.dts @@ -9,6 +9,7 @@ / { model = "Google fennel14 sku2 board"; + chassis-type = "laptop"; compatible = "google,fennel-sku2", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts index 23ad0b91e977..b981dd31a430 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-fennel14.dts @@ -9,6 +9,7 @@ / { model = "Google fennel14 sku0 board"; + chassis-type = "laptop"; compatible = "google,fennel-sku0", "google,fennel", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts index e5bd9191e426..f3ac9c074226 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kappa.dts @@ -9,6 +9,7 @@ / { model = "Google kappa board"; + chassis-type = "laptop"; compatible = "google,kappa", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts index 8fa89db03e63..e8241587949b 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-kenzo.dts @@ -9,5 +9,6 @@ / { model = "Google kenzo sku17 board"; + chassis-type = "laptop"; compatible = "google,juniper-sku17", "google,juniper", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts index 4eb2a0d571af..ddb993521bbf 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku0.dts @@ -19,6 +19,6 @@ &mmc1_pins_uhs { pins-clk { - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts index 6a733361e8ae..10c4f920a7d8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-makomo-sku1.dts @@ -19,6 +19,6 @@ &mmc1_pins_uhs { pins-clk { - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts index 6a7ae616512d..cce326aec1aa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-pico6.dts @@ -17,7 +17,7 @@ pinctrl-names = "default"; pinctrl-0 = <&bt_pins_wakeup>; - wobt { + event-wobt { label = "Wake on BT"; gpios = <&pio 42 GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; @@ -47,10 +47,8 @@ }; }; -&wifi_wakeup { - wowlan { - gpios = <&pio 113 GPIO_ACTIVE_LOW>; - }; +&wifi_wakeup_event { + gpios = <&pio 113 GPIO_ACTIVE_LOW>; }; &wifi_pwrseq { @@ -68,16 +66,16 @@ &mmc1_pins_default { pins-cmd-dat { - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; }; pins-clk { - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; }; }; &mmc1_pins_uhs { pins-clk { - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts index 89208b843b27..928b205a616a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku0.dts @@ -9,6 +9,7 @@ / { model = "Google willow board sku0"; + chassis-type = "laptop"; compatible = "google,willow-sku0", "google,willow", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts index c7b20441d053..71307a8052d6 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi-willow-sku1.dts @@ -9,5 +9,6 @@ / { model = "Google willow board sku1"; + chassis-type = "laptop"; compatible = "google,willow-sku1", "google,willow", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi index 7592e3b86037..fa4ab4d2899f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-jacuzzi.dtsi @@ -155,21 +155,24 @@ vdd18-supply = <&pp1800_mipibrdg>; vdd33-supply = <&vddio_mipibrdg>; - #address-cells = <1>; - #size-cells = <0>; - port@0 { - reg = <0>; + ports { + #address-cells = <1>; + #size-cells = <0>; - anx7625_in: endpoint { - remote-endpoint = <&dsi_out>; + port@0 { + reg = <0>; + + anx7625_in: endpoint { + remote-endpoint = <&dsi_out>; + }; }; - }; - port@1 { - reg = <1>; + port@1 { + reg = <1>; - anx7625_out: endpoint { - remote-endpoint = <&panel_in>; + anx7625_out: endpoint { + remote-endpoint = <&panel_in>; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts index 7739358008ee..5a416143b4a0 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui-kodama-sku32.dts @@ -12,6 +12,7 @@ / { model = "MediaTek kodama sku32 board"; + chassis-type = "tablet"; compatible = "google,kodama-sku32", "google,kodama", "mediatek,mt8183"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi index 100191c6453b..6345e969efae 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183-kukui.dtsi @@ -152,7 +152,7 @@ pinctrl-names = "default"; pinctrl-0 = <&wifi_pins_wakeup>; - button-wowlan { + wifi_wakeup_event: event-wowlan { label = "Wake on WiFi"; gpios = <&pio 113 GPIO_ACTIVE_HIGH>; linux,code = <KEY_WAKEUP>; @@ -488,7 +488,7 @@ <PINMUX_GPIO172__FUNC_TDM_DATA1_2ND>, <PINMUX_GPIO173__FUNC_TDM_DATA2_2ND>, <PINMUX_GPIO10__FUNC_TDM_DATA3>; /*8ch-i2s to it6505*/ - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; }; }; @@ -502,7 +502,7 @@ <PINMUX_GPIO10__FUNC_GPIO10>; input-enable; bias-pull-down; - drive-strength = <MTK_DRIVE_2mA>; + drive-strength = <2>; }; }; @@ -533,7 +533,6 @@ pinmux = <PINMUX_GPIO82__FUNC_SDA0>, <PINMUX_GPIO83__FUNC_SCL0>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -542,7 +541,6 @@ pinmux = <PINMUX_GPIO81__FUNC_SDA1>, <PINMUX_GPIO84__FUNC_SCL1>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -551,7 +549,6 @@ pinmux = <PINMUX_GPIO103__FUNC_SCL2>, <PINMUX_GPIO104__FUNC_SDA2>; bias-disable; - mediatek,drive-strength-adv = <00>; }; }; @@ -560,7 +557,6 @@ pinmux = <PINMUX_GPIO50__FUNC_SCL3>, <PINMUX_GPIO51__FUNC_SDA3>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -569,7 +565,6 @@ pinmux = <PINMUX_GPIO105__FUNC_SCL4>, <PINMUX_GPIO106__FUNC_SDA4>; bias-disable; - mediatek,drive-strength-adv = <00>; }; }; @@ -578,7 +573,6 @@ pinmux = <PINMUX_GPIO48__FUNC_SCL5>, <PINMUX_GPIO49__FUNC_SDA5>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -679,14 +673,14 @@ <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; input-enable; mediatek,pull-up-adv = <10>; }; pins-clk { pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; mediatek,pull-down-adv = <10>; input-enable; }; @@ -803,7 +797,6 @@ }; pins-rts { pinmux = <PINMUX_GPIO47__FUNC_URTS1>; - output-enable; }; pins-cts { pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; @@ -822,7 +815,6 @@ }; pins-rts { pinmux = <PINMUX_GPIO47__FUNC_URTS1>; - output-enable; }; pins-cts { pinmux = <PINMUX_GPIO46__FUNC_UCTS1>; diff --git a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts index 333c516af490..1aa668c3ccf9 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts +++ b/arch/arm64/boot/dts/mediatek/mt8183-pumpkin.dts @@ -197,7 +197,6 @@ pinmux = <PINMUX_GPIO82__FUNC_SDA0>, <PINMUX_GPIO83__FUNC_SCL0>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -206,7 +205,6 @@ pinmux = <PINMUX_GPIO81__FUNC_SDA1>, <PINMUX_GPIO84__FUNC_SCL1>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -215,7 +213,6 @@ pinmux = <PINMUX_GPIO103__FUNC_SCL2>, <PINMUX_GPIO104__FUNC_SDA2>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -224,7 +221,6 @@ pinmux = <PINMUX_GPIO50__FUNC_SCL3>, <PINMUX_GPIO51__FUNC_SDA3>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -233,7 +229,6 @@ pinmux = <PINMUX_GPIO105__FUNC_SCL4>, <PINMUX_GPIO106__FUNC_SDA4>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -242,7 +237,6 @@ pinmux = <PINMUX_GPIO48__FUNC_SCL5>, <PINMUX_GPIO49__FUNC_SDA5>; mediatek,pull-up-adv = <3>; - mediatek,drive-strength-adv = <00>; }; }; @@ -356,14 +350,14 @@ <PINMUX_GPIO34__FUNC_MSDC1_DAT1>, <PINMUX_GPIO33__FUNC_MSDC1_DAT2>, <PINMUX_GPIO30__FUNC_MSDC1_DAT3>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; input-enable; mediatek,pull-up-adv = <10>; }; pins_clk { pinmux = <PINMUX_GPIO29__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; mediatek,pull-down-adv = <10>; input-enable; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index 774ae5d9143f..fbf145639b8c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1183,7 +1183,7 @@ status = "disabled"; }; - thermal: thermal@1100b000 { + thermal: thermal-sensor@1100b000 { #thermal-sensor-cells = <1>; compatible = "mediatek,mt8183-thermal"; reg = <0 0x1100b000 0 0xc00>; @@ -2090,61 +2090,129 @@ }; }; - /* The tzts1 ~ tzts6 don't need to polling */ - /* The tzts1 ~ tzts6 don't need to thermal throttle */ - - tzts1: tzts1 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts1: soc-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 1>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + trips { + soc_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + soc_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts2: tzts2 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts2: gpu-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 2>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + gpu_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + gpu_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts3: tzts3 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts3: md1-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 3>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + md1_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + md1_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts4: tzts4 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts4: cpu-little-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 4>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + cpul_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpul_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tzts5: tzts5 { - polling-delay-passive = <0>; - polling-delay = <0>; + tzts5: cpu-big-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 5>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + cpub_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + cpub_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; - tztsABB: tztsABB { - polling-delay-passive = <0>; - polling-delay = <0>; + tztsABB: tsabb-thermal { + polling-delay = <1000>; + polling-delay-passive = <250>; thermal-sensors = <&thermal 6>; sustainable-power = <5000>; - trips {}; - cooling-maps {}; + + trips { + tsabb_alert: trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + tsabb_crit: trip-crit { + temperature = <100000>; + hysteresis = <2000>; + type = "critical"; + }; + }; }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts new file mode 100644 index 000000000000..d16834eec87a --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589824.dts @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-voltorb.dtsi" + +/ { + model = "Google Voltorb sku589824 board"; + compatible = "google,voltorb-sku589824", "google,voltorb", + "mediatek,mt8186"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts new file mode 100644 index 000000000000..45e57f7706cc --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb-sku589825.dts @@ -0,0 +1,25 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +/dts-v1/; +#include "mt8186-corsola-voltorb.dtsi" + +/ { + model = "Google Voltorb sku589825 board"; + compatible = "google,voltorb-sku589825", "google,voltorb", + "mediatek,mt8186"; +}; + +&i2c1 { + touchscreen@10 { + compatible = "elan,ekth6915"; + reg = <0x10>; + interrupts-extended = <&pio 12 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + reset-gpios = <&pio 60 GPIO_ACTIVE_LOW>; + vcc33-supply = <&pp3300_s3>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi new file mode 100644 index 000000000000..52ec58128d56 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola-voltorb.dtsi @@ -0,0 +1,103 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright 2022 Google LLC + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/spmi/spmi.h> + +#include "mt8186-corsola-steelix.dtsi" + +/ { + chassis-type = "laptop"; + + max98360a: max98360a { + compatible = "maxim,max98360a"; + sdmode-gpios = <&pio 150 GPIO_ACTIVE_HIGH>; + #sound-dai-cells = <0>; + }; +}; + +&cpu6 { + proc-supply = <&mt6319_buck1>; +}; + +&cpu7 { + proc-supply = <&mt6319_buck1>; +}; + +&gpio_keys { + status = "disabled"; +}; + +&keyboard_controller { + linux,keymap = < + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_MUTE) + MATRIX_KEY(0x01, 0x09, KEY_VOLUMEDOWN) + MATRIX_KEY(0x00, 0x04, KEY_VOLUMEUP) + CROS_STD_MAIN_KEYMAP + >; +}; + +&mt6366_vproc11_reg { + status = "disabled"; +}; + +&cluster1_opp_14 { + opp-hz = /bits/ 64 <2050000000>; + opp-microvolt = <1118750>; +}; + +&cluster1_opp_15 { + opp-hz = /bits/ 64 <2200000000>; +}; + +&rt1019p{ + status = "disabled"; +}; + +&sound { + compatible = "mediatek,mt8186-mt6366-rt5682s-max98360-sound"; + status = "okay"; + + spk-hdmi-playback-dai-link { + codec { + sound-dai = <&it6505dptx>, <&max98360a>; + }; + }; +}; + +&spmi { + pinctrl-names = "default"; + pinctrl-0 = <&spmi_pins>; + #address-cells = <2>; + #size-cells = <0>; + status = "okay"; + + pmic@6 { + compatible = "mediatek,mt6319-regulator", "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6319_buck1: vbuck1 { + regulator-name = "ppvar_dvdd_proc_bc_mt6319"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +&touchscreen { + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi index 1807e9d6cb0e..afdab5724eaa 100644 --- a/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8186-corsola.dtsi @@ -42,7 +42,7 @@ default-brightness-level = <576>; }; - bt-sco-codec { + bt-sco { compatible = "linux,bt-sco"; #sound-dai-cells = <0>; }; @@ -223,12 +223,44 @@ mediatek,adsp = <&adsp>; mediatek,platform = <&afe>; - playback-codecs { - sound-dai = <&it6505dptx>, <&rt1019p>; + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Speakers", "Speaker", + "HDMI1", "TX"; + + hs-playback-dai-link { + link-name = "I2S0"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&rt5682s 0>; + }; + }; + + hs-capture-dai-link { + link-name = "I2S1"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&rt5682s 0>; + }; }; - headset-codec { - sound-dai = <&rt5682s 0>; + spk-share-dai-link { + link-name = "I2S2"; + mediatek,clk-provider = "cpu"; + }; + + spk-hdmi-playback-dai-link { + link-name = "I2S3"; + dai-format = "i2s"; + mediatek,clk-provider = "cpu"; + /* RT1019P and IT6505 connected to the same I2S line */ + codec { + sound-dai = <&it6505dptx>, <&rt1019p>; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8188.dtsi b/arch/arm64/boot/dts/mediatek/mt8188.dtsi index b4315c9214dc..29d012d28edb 100644 --- a/arch/arm64/boot/dts/mediatek/mt8188.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8188.dtsi @@ -8,6 +8,7 @@ #include <dt-bindings/clock/mediatek,mt8188-clk.h> #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/mailbox/mediatek,mt8188-gce.h> #include <dt-bindings/phy/phy.h> #include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> #include <dt-bindings/power/mediatek,mt8188-power.h> @@ -293,6 +294,112 @@ clock-output-names = "clk32k"; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + opp-shared; + + opp-390000000 { + opp-hz = /bits/ 64 <390000000>; + opp-microvolt = <575000>; + opp-supported-hw = <0xff>; + }; + opp-431000000 { + opp-hz = /bits/ 64 <431000000>; + opp-microvolt = <587500>; + opp-supported-hw = <0xff>; + }; + opp-473000000 { + opp-hz = /bits/ 64 <473000000>; + opp-microvolt = <600000>; + opp-supported-hw = <0xff>; + }; + opp-515000000 { + opp-hz = /bits/ 64 <515000000>; + opp-microvolt = <612500>; + opp-supported-hw = <0xff>; + }; + opp-556000000 { + opp-hz = /bits/ 64 <556000000>; + opp-microvolt = <625000>; + opp-supported-hw = <0xff>; + }; + opp-598000000 { + opp-hz = /bits/ 64 <598000000>; + opp-microvolt = <637500>; + opp-supported-hw = <0xff>; + }; + opp-640000000 { + opp-hz = /bits/ 64 <640000000>; + opp-microvolt = <650000>; + opp-supported-hw = <0xff>; + }; + opp-670000000 { + opp-hz = /bits/ 64 <670000000>; + opp-microvolt = <662500>; + opp-supported-hw = <0xff>; + }; + opp-700000000 { + opp-hz = /bits/ 64 <700000000>; + opp-microvolt = <675000>; + opp-supported-hw = <0xff>; + }; + opp-730000000 { + opp-hz = /bits/ 64 <730000000>; + opp-microvolt = <687500>; + opp-supported-hw = <0xff>; + }; + opp-760000000 { + opp-hz = /bits/ 64 <760000000>; + opp-microvolt = <700000>; + opp-supported-hw = <0xff>; + }; + opp-790000000 { + opp-hz = /bits/ 64 <790000000>; + opp-microvolt = <712500>; + opp-supported-hw = <0xff>; + }; + opp-835000000 { + opp-hz = /bits/ 64 <835000000>; + opp-microvolt = <731250>; + opp-supported-hw = <0xff>; + }; + opp-880000000 { + opp-hz = /bits/ 64 <880000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0xff>; + }; + opp-915000000 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <775000>; + opp-supported-hw = <0x8f>; + }; + opp-915000000-5 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <762500>; + opp-supported-hw = <0x30>; + }; + opp-915000000-6 { + opp-hz = /bits/ 64 <915000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0x70>; + }; + opp-950000000 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <800000>; + opp-supported-hw = <0x8f>; + }; + opp-950000000-5 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <775000>; + opp-supported-hw = <0x30>; + }; + opp-950000000-6 { + opp-hz = /bits/ 64 <950000000>; + opp-microvolt = <750000>; + opp-supported-hw = <0x70>; + }; + }; + pmu-a55 { compatible = "arm,cortex-a55-pmu"; interrupt-parent = <&gic>; @@ -383,6 +490,329 @@ #interrupt-cells = <2>; }; + scpsys: syscon@10006000 { + compatible = "mediatek,mt8188-scpsys", "syscon", "simple-mfd"; + reg = <0 0x10006000 0 0x1000>; + + /* System Power Manager */ + spm: power-controller { + compatible = "mediatek,mt8188-power-controller"; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + /* power domain of the SoC */ + mfg0: power-domain@MT8188_POWER_DOMAIN_MFG0 { + reg = <MT8188_POWER_DOMAIN_MFG0>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_MFG1 { + reg = <MT8188_POWER_DOMAIN_MFG1>; + clocks = <&topckgen CLK_APMIXED_MFGPLL>, + <&topckgen CLK_TOP_MFG_CORE_TMP>; + clock-names = "mfg", "alt"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_MFG2 { + reg = <MT8188_POWER_DOMAIN_MFG2>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_MFG3 { + reg = <MT8188_POWER_DOMAIN_MFG3>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_MFG4 { + reg = <MT8188_POWER_DOMAIN_MFG4>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VPPSYS0 { + reg = <MT8188_POWER_DOMAIN_VPPSYS0>; + clocks = <&topckgen CLK_TOP_VPP>, + <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_IMG>, + <&topckgen CLK_TOP_VENC>, + <&topckgen CLK_TOP_VDEC>, + <&topckgen CLK_TOP_WPE_VPP>, + <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP0>, + <&topckgen CLK_TOP_CFGREG_F26M_VPP0>, + <&vppsys0 CLK_VPP0_SMI_COMMON_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_INFRA_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_CAMSYS_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5_MMSRAM>, + <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6_MMSRAM>, + <&vppsys0 CLK_VPP0_SMI_REORDER_MMSRAM>, + <&vppsys0 CLK_VPP0_SMI_IOMMU>, + <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>, + <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>, + <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>, + <&vppsys0 CLK_VPP0_SMI_RSI>, + <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>, + <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>, + <&vppsys0 CLK_VPP0_GALS_VPP1_WPESYS>, + <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>; + clock-names = "top", "cam", "ccu", "img", "venc", + "vdec", "wpe", "cfgck", "cfgxo", + "ss-sram-cmn", "ss-sram-v0l0", "ss-sram-v0l1", + "ss-sram-ve0", "ss-sram-ve1", "ss-sram-ifa", + "ss-sram-cam", "ss-sram-v1l5", "ss-sram-v1l6", + "ss-sram-rdr", "ss-iommu", "ss-imgcam", + "ss-emi", "ss-subcmn-rdr", "ss-rsi", + "ss-cmn-l4", "ss-vdec1", "ss-wpe", + "ss-cvdo-ve1"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_VDOSYS0 { + reg = <MT8188_POWER_DOMAIN_VDOSYS0>; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO0>, + <&topckgen CLK_TOP_CFGREG_F26M_VDO0>, + <&vdosys0 CLK_VDO0_SMI_GALS>, + <&vdosys0 CLK_VDO0_SMI_COMMON>, + <&vdosys0 CLK_VDO0_SMI_EMI>, + <&vdosys0 CLK_VDO0_SMI_IOMMU>, + <&vdosys0 CLK_VDO0_SMI_LARB>, + <&vdosys0 CLK_VDO0_SMI_RSI>, + <&vdosys0 CLK_VDO0_APB_BUS>; + clock-names = "cfgck", "cfgxo", "ss-gals", + "ss-cmn", "ss-emi", "ss-iommu", + "ss-larb", "ss-rsi", "ss-bus"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_VPPSYS1 { + reg = <MT8188_POWER_DOMAIN_VPPSYS1>; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VPP1>, + <&topckgen CLK_TOP_CFGREG_F26M_VPP1>, + <&vppsys1 CLK_VPP1_GALS5>, + <&vppsys1 CLK_VPP1_GALS6>, + <&vppsys1 CLK_VPP1_LARB5>, + <&vppsys1 CLK_VPP1_LARB6>; + clock-names = "cfgck", "cfgxo", + "ss-vpp1-g5", "ss-vpp1-g6", + "ss-vpp1-l5", "ss-vpp1-l6"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_VDEC1 { + reg = <MT8188_POWER_DOMAIN_VDEC1>; + clocks = <&vdecsys CLK_VDEC2_LARB1>; + clock-names = "ss-vdec"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_VDEC0 { + reg = <MT8188_POWER_DOMAIN_VDEC0>; + clocks = <&vdecsys_soc CLK_VDEC1_SOC_LARB1>; + clock-names = "ss-vdec"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + cam_vcore: power-domain@MT8188_POWER_DOMAIN_CAM_VCORE { + reg = <MT8188_POWER_DOMAIN_CAM_VCORE>; + clocks = <&topckgen CLK_TOP_CAM>, + <&topckgen CLK_TOP_CCU>, + <&topckgen CLK_TOP_CCU_AHB>, + <&topckgen CLK_TOP_CFGREG_CLOCK_ISP_AXI_GALS>; + clock-names = "cam", "ccu", "bus", "cfgck"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_CAM_MAIN { + reg = <MT8188_POWER_DOMAIN_CAM_MAIN>; + clocks = <&camsys CLK_CAM_MAIN_LARB13>, + <&camsys CLK_CAM_MAIN_LARB14>, + <&camsys CLK_CAM_MAIN_CAM2MM0_GALS>, + <&camsys CLK_CAM_MAIN_CAM2MM1_GALS>, + <&camsys CLK_CAM_MAIN_CAM2SYS_GALS>; + clock-names= "ss-cam-l13", "ss-cam-l14", + "ss-cam-mm0", "ss-cam-mm1", + "ss-camsys"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_CAM_SUBB { + reg = <MT8188_POWER_DOMAIN_CAM_SUBB>; + clocks = <&camsys CLK_CAM_MAIN_CAM_SUBB>, + <&camsys_rawb CLK_CAM_RAWB_LARBX>, + <&camsys_yuvb CLK_CAM_YUVB_LARBX>; + clock-names = "ss-camb-sub", + "ss-camb-raw", + "ss-camb-yuv"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_CAM_SUBA { + reg =<MT8188_POWER_DOMAIN_CAM_SUBA>; + clocks = <&camsys CLK_CAM_MAIN_CAM_SUBA>, + <&camsys_rawa CLK_CAM_RAWA_LARBX>, + <&camsys_yuva CLK_CAM_YUVA_LARBX>; + clock-names = "ss-cama-sub", + "ss-cama-raw", + "ss-cama-yuv"; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VDOSYS1 { + reg = <MT8188_POWER_DOMAIN_VDOSYS1>; + clocks = <&topckgen CLK_TOP_CFGREG_CLOCK_EN_VDO1>, + <&topckgen CLK_TOP_CFGREG_F26M_VDO1>, + <&vdosys1 CLK_VDO1_SMI_LARB2>, + <&vdosys1 CLK_VDO1_SMI_LARB3>, + <&vdosys1 CLK_VDO1_GALS>; + clock-names = "cfgck", "cfgxo", "ss-larb2", + "ss-larb3", "ss-gals"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_HDMI_TX { + reg = <MT8188_POWER_DOMAIN_HDMI_TX>; + clocks = <&topckgen CLK_TOP_HDMI_APB>, + <&topckgen CLK_TOP_HDCP_24M>; + clock-names = "bus", "hdcp"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_DP_TX { + reg = <MT8188_POWER_DOMAIN_DP_TX>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_EDP_TX { + reg = <MT8188_POWER_DOMAIN_EDP_TX>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_VENC { + reg = <MT8188_POWER_DOMAIN_VENC>; + clocks = <&vencsys CLK_VENC1_LARB>, + <&vencsys CLK_VENC1_VENC>, + <&vencsys CLK_VENC1_GALS>, + <&vencsys CLK_VENC1_GALS_SRAM>; + clock-names = "ss-ve1-larb", "ss-ve1-core", + "ss-ve1-gals", "ss-ve1-sram"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_WPE { + reg = <MT8188_POWER_DOMAIN_WPE>; + clocks = <&wpesys CLK_WPE_TOP_SMI_LARB7>, + <&wpesys CLK_WPE_TOP_SMI_LARB7_PCLK_EN>; + clock-names = "ss-wpe-l7", "ss-wpe-l7pce"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_PEXTP_MAC_P0 { + reg = <MT8188_POWER_DOMAIN_PEXTP_MAC_P0>; + mediatek,infracfg = <&infracfg_ao>; + clocks = <&pericfg_ao CLK_PERI_AO_PCIE_P0_FMEM>; + clock-names = "ss-pextp-fmem"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_CSIRX_TOP { + reg = <MT8188_POWER_DOMAIN_CSIRX_TOP>; + clocks = <&topckgen CLK_TOP_SENINF>, + <&topckgen CLK_TOP_SENINF1>; + clock-names = "seninf0", "seninf1"; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_PEXTP_PHY_TOP { + reg = <MT8188_POWER_DOMAIN_PEXTP_PHY_TOP>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_ADSP_AO { + reg = <MT8188_POWER_DOMAIN_ADSP_AO>; + clocks = <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>, + <&topckgen CLK_TOP_ADSP>; + clock-names = "bus", "main"; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_ADSP_INFRA { + reg = <MT8188_POWER_DOMAIN_ADSP_INFRA>; + mediatek,infracfg = <&infracfg_ao>; + #address-cells = <1>; + #size-cells = <0>; + #power-domain-cells = <1>; + + power-domain@MT8188_POWER_DOMAIN_AUDIO_ASRC { + reg = <MT8188_POWER_DOMAIN_AUDIO_ASRC>; + clocks = <&topckgen CLK_TOP_ASM_H>; + clock-names = "asm"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_AUDIO { + reg = <MT8188_POWER_DOMAIN_AUDIO>; + clocks = <&topckgen CLK_TOP_A1SYS_HP>, + <&topckgen CLK_TOP_AUD_INTBUS>, + <&adsp_audio26m CLK_AUDIODSP_AUDIO26M>; + clock-names = "a1sys", "intbus", "adspck"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + + power-domain@MT8188_POWER_DOMAIN_ADSP { + reg = <MT8188_POWER_DOMAIN_ADSP>; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + + power-domain@MT8188_POWER_DOMAIN_ETHER { + reg = <MT8188_POWER_DOMAIN_ETHER>; + clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>; + clock-names = "ethermac"; + mediatek,infracfg = <&infracfg_ao>; + #power-domain-cells = <0>; + }; + }; + }; + watchdog: watchdog@10007000 { compatible = "mediatek,mt8188-wdt"; reg = <0 0x10007000 0 0x100>; @@ -413,6 +843,22 @@ clock-names = "spi", "wrap"; }; + gce0: mailbox@10320000 { + compatible = "mediatek,mt8188-gce"; + reg = <0 0x10320000 0 0x4000>; + interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>; + }; + + gce1: mailbox@10330000 { + compatible = "mediatek,mt8188-gce"; + reg = <0 0x10330000 0 0x4000>; + interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>; + #mbox-cells = <2>; + clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>; + }; + scp: scp@10500000 { compatible = "mediatek,mt8188-scp"; reg = <0 0x10500000 0 0x100000>, @@ -827,6 +1273,23 @@ #clock-cells = <1>; }; + gpu: gpu@13000000 { + compatible = "mediatek,mt8188-mali", "arm,mali-valhall-jm"; + reg = <0 0x13000000 0 0x4000>; + + clocks = <&mfgcfg CLK_MFGCFG_BG3D>; + interrupts = <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH 0>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH 0>; + interrupt-names = "job", "mmu", "gpu"; + operating-points-v2 = <&gpu_opp_table>; + power-domains = <&spm MT8188_POWER_DOMAIN_MFG2>, + <&spm MT8188_POWER_DOMAIN_MFG3>, + <&spm MT8188_POWER_DOMAIN_MFG4>; + power-domain-names = "core0", "core1", "core2"; + status = "disabled"; + }; + mfgcfg: clock-controller@13fbf000 { compatible = "mediatek,mt8188-mfgcfg"; reg = <0 0x13fbf000 0 0x1000>; @@ -952,5 +1415,22 @@ reg = <0 0x1a000000 0 0x1000>; #clock-cells = <1>; }; + + vdosys0: syscon@1c01d000 { + compatible = "mediatek,mt8188-vdosys0", "syscon"; + reg = <0 0x1c01d000 0 0x1000>; + #clock-cells = <1>; + mboxes = <&gce0 0 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0xd000 0x1000>; + }; + + vdosys1: syscon@1c100000 { + compatible = "mediatek,mt8188-vdosys1", "syscon"; + reg = <0 0x1c100000 0 0x1000>; + #clock-cells = <1>; + #reset-cells = <1>; + mboxes = <&gce0 1 CMDQ_THR_PRIO_4>; + mediatek,gce-client-reg = <&gce0 SUBSYS_1c10XXXX 0 0x1000>; + }; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts index fd2cb8765a15..ac2673e56fb8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r1.dts @@ -7,6 +7,7 @@ / { model = "Google Hayato rev1"; + chassis-type = "convertible"; compatible = "google,hayato-rev1", "google,hayato", "mediatek,mt8192"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts index 3127ee5f6172..cd86ad9ba28a 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-hayato-r5-sku2.dts @@ -7,6 +7,7 @@ / { model = "Google Hayato rev5"; + chassis-type = "convertible"; compatible = "google,hayato-rev5-sku2", "google,hayato-sku2", "google,hayato", "mediatek,mt8192"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts index bc88866ab2f5..29aa87e93888 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r0.dts @@ -8,6 +8,7 @@ / { model = "Google Spherion (rev0 - 3)"; + chassis-type = "laptop"; compatible = "google,spherion-rev3", "google,spherion-rev2", "google,spherion-rev1", "google,spherion-rev0", "google,spherion", "mediatek,mt8192"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts index 0039158c9e60..5e9e598bab90 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada-spherion-r4.dts @@ -8,6 +8,7 @@ / { model = "Google Spherion (rev4)"; + chassis-type = "laptop"; compatible = "google,spherion-rev4", "google,spherion", "mediatek,mt8192"; diff --git a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi index 7a704246678f..08d71ddf3668 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192-asurada.dtsi @@ -147,6 +147,7 @@ regulator-boot-on; gpio = <&pio 127 GPIO_ACTIVE_HIGH>; vin-supply = <&pp3300_g>; + off-on-delay-us = <500000>; }; /* separately switched 3.3V power rail */ diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi index 84cbdf6e9eb0..47dea10dd3b8 100644 --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi @@ -2234,7 +2234,7 @@ }; }; - gpu0-thermal { + gpu-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8192_AP_GPU0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts new file mode 100644 index 000000000000..88123842c818 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry-dojo-r1.dts @@ -0,0 +1,114 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2022 MediaTek Inc. + */ +/dts-v1/; +#include "mt8195-cherry.dtsi" + +/ { + model = "HP Dojo (sku 1, 3, 5, 7) board"; + chassis-type = "convertible"; + compatible = "google,dojo-sku7", "google,dojo-sku5", + "google,dojo-sku3", "google,dojo-sku1", + "google,dojo", "mediatek,mt8195"; +}; + +&audio_codec { + compatible = "realtek,rt5682s"; + realtek,amic-delay-ms = <250>; +}; + +&i2c2 { + spk_r_amp: amplifier@38 { + compatible = "maxim,max98390"; + reg = <0x38>; + reset-gpios = <&pio 100 GPIO_ACTIVE_LOW>; + sound-name-prefix = "Right"; + #sound-dai-cells = <0>; + }; + + spk_l_amp: amplifier@39 { + compatible = "maxim,max98390"; + reg = <0x39>; + sound-name-prefix = "Left"; + #sound-dai-cells = <0>; + }; +}; + +&i2c4 { + touchscreen@15 { + compatible = "hid-over-i2c"; + reg = <0x15>; + hid-descr-addr = <0x0001>; + interrupts-extended = <&pio 92 IRQ_TYPE_LEVEL_LOW>; + pinctrl-names = "default"; + pinctrl-0 = <&touchscreen_pins>; + post-power-on-delay-ms = <10>; + vdd-supply = <&pp3300_s3>; + }; +}; + +&keyboard_controller { + linux,keymap = < + CROS_STD_MAIN_KEYMAP + + MATRIX_KEY(0x00, 0x02, KEY_BACK) + MATRIX_KEY(0x03, 0x02, KEY_REFRESH) + MATRIX_KEY(0x02, 0x02, KEY_ZOOM) + MATRIX_KEY(0x01, 0x02, KEY_SCALE) + MATRIX_KEY(0x03, 0x04, KEY_SYSRQ) + MATRIX_KEY(0x02, 0x04, KEY_BRIGHTNESSDOWN) + MATRIX_KEY(0x01, 0x04, KEY_BRIGHTNESSUP) + MATRIX_KEY(0x02, 0x09, KEY_KBDILLUMTOGGLE) + MATRIX_KEY(0x01, 0x09, KEY_PLAYPAUSE) + MATRIX_KEY(0x00, 0x04, KEY_MICMUTE) + MATRIX_KEY(0x00, 0x01, KEY_MUTE) + MATRIX_KEY(0x01, 0x05, KEY_VOLUMEDOWN) + MATRIX_KEY(0x03, 0x05, KEY_VOLUMEUP) + >; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio_default { + pins-low-power-hdmi-disable { + pinmux = <PINMUX_GPIO31__FUNC_GPIO31>, + <PINMUX_GPIO32__FUNC_GPIO32>, + <PINMUX_GPIO33__FUNC_GPIO33>, + <PINMUX_GPIO34__FUNC_GPIO34>, + <PINMUX_GPIO35__FUNC_GPIO35>; + input-enable; + bias-pull-down; + }; +}; + +&sound { + compatible = "mediatek,mt8195_mt6359_max98390_rt5682"; + model = "m8195_m98390_5682s"; + + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Right Spk", "Right BE_OUT", + "Left Spk", "Left BE_OUT"; + + spk-playback-dai-link { + codec { + sound-dai = <&spk_r_amp>, <&spk_l_amp>; + }; + }; +}; + +&spk_amplifier { + /* Disable RT1019P, not present on Dojo */ + status = "disabled"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi index 4a11918da370..fe5400e17b0f 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195-cherry.dtsi @@ -240,6 +240,7 @@ spk_amplifier: rt1019p { compatible = "realtek,rt1019p"; label = "rt1019p"; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&rt1019p_pins_default>; sdb-gpios = <&pio 100 GPIO_ACTIVE_HIGH>; @@ -366,6 +367,7 @@ &dp_tx { status = "okay"; + #sound-dai-cells = <0>; pinctrl-names = "default"; pinctrl-0 = <&dptx_pin>; @@ -436,6 +438,7 @@ /* Realtek RT5682i or RT5682s, sharing the same configuration */ reg = <0x1a>; interrupts-extended = <&pio 89 IRQ_TYPE_EDGE_BOTH>; + #sound-dai-cells = <0>; realtek,jd-src = <1>; AVDD-supply = <&mt6359_vio18_ldo_reg>; @@ -1162,6 +1165,48 @@ "AFE_SOF_DL2", "AFE_SOF_DL3", "AFE_SOF_UL4", "AFE_SOF_UL5"; pinctrl-names = "default"; pinctrl-0 = <&aud_pins_default>; + + audio-routing = + "Headphone", "HPOL", + "Headphone", "HPOR", + "IN1P", "Headset Mic", + "Ext Spk", "Speaker"; + + mm-dai-link { + link-name = "ETDM1_IN_BE"; + mediatek,clk-provider = "cpu"; + }; + + hs-playback-dai-link { + link-name = "ETDM1_OUT_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&audio_codec>; + }; + }; + + hs-capture-dai-link { + link-name = "ETDM2_IN_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&audio_codec>; + }; + }; + + spk-playback-dai-link { + link-name = "ETDM2_OUT_BE"; + mediatek,clk-provider = "cpu"; + codec { + sound-dai = <&spk_amplifier>; + }; + }; + + displayport-dai-link { + link-name = "DPTX_BE"; + codec { + sound-dai = <&dp_tx>; + }; + }; }; &spi0 { @@ -1389,6 +1434,11 @@ MATRIX_KEY(0x02, 0x09, 0) /* T8 */ MATRIX_KEY(0x01, 0x09, 0) /* T9 */ MATRIX_KEY(0x00, 0x04, 0) /* T10 */ + + /* T11 to T13 are present only on Dojo */ + MATRIX_KEY(0x00, 0x01, 0) /* T11 */ + MATRIX_KEY(0x01, 0x05, 0) /* T12 */ + MATRIX_KEY(0x03, 0x05, 0) /* T13 */ >; linux,keymap = < diff --git a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts index b82f7176b4a1..31d424b8fc7c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-demo.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-demo.dts @@ -305,14 +305,14 @@ <PINMUX_GPIO78__FUNC_GBE_TXD2>, <PINMUX_GPIO79__FUNC_GBE_TXD1>, <PINMUX_GPIO80__FUNC_GBE_TXD0>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; }; pins-cc { pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, <PINMUX_GPIO88__FUNC_GBE_TXEN>, <PINMUX_GPIO87__FUNC_GBE_RXDV>, <PINMUX_GPIO86__FUNC_GBE_RXC>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; }; pins-rxd { pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, @@ -377,7 +377,7 @@ mmc0_default_pins: mmc0-default-pins { pins-clk { pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -392,13 +392,13 @@ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, <PINMUX_GPIO121__FUNC_MSDC0_CMD>; input-enable; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; pins-rst { pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; @@ -406,7 +406,7 @@ mmc0_uhs_pins: mmc0-uhs-pins { pins-clk { pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -421,19 +421,19 @@ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, <PINMUX_GPIO121__FUNC_MSDC0_CMD>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; pins-ds { pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; pins-rst { pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; @@ -441,7 +441,7 @@ mmc1_default_pins: mmc1-default-pins { pins-clk { pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -452,7 +452,7 @@ <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; @@ -465,7 +465,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { pins-clk { pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -476,7 +476,7 @@ <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts index 341b6e074139..83456d649ff7 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts +++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts @@ -74,7 +74,6 @@ pinmux = <PINMUX_GPIO8__FUNC_SDA0>, <PINMUX_GPIO9__FUNC_SCL0>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - mediatek,drive-strength-adv = <0>; drive-strength = <6>; }; }; @@ -84,7 +83,6 @@ pinmux = <PINMUX_GPIO10__FUNC_SDA1>, <PINMUX_GPIO11__FUNC_SCL1>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - mediatek,drive-strength-adv = <0>; drive-strength = <6>; }; }; @@ -94,7 +92,7 @@ pinmux = <PINMUX_GPIO16__FUNC_SDA4>, <PINMUX_GPIO17__FUNC_SCL4>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; - mediatek,drive-strength-adv = <7>; + drive-strength-microamp = <1000>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi index 5d8b68f86ce4..2ee45752583c 100644 --- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi @@ -3880,7 +3880,7 @@ }; }; - gpu0-thermal { + gpu-thermal { polling-delay = <1000>; polling-delay-passive = <250>; thermal-sensors = <&lvts_ap MT8195_AP_GPU0>; diff --git a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts index 50cbaefa1a99..4211a992dd9d 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8365-evk.dts @@ -308,7 +308,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { clk-pins { pinmux = <MT8365_PIN_88_MSDC1_CLK__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -319,7 +319,7 @@ <MT8365_PIN_92_MSDC1_DAT3__FUNC_MSDC1_DAT3>, <MT8365_PIN_87_MSDC1_CMD__FUNC_MSDC1_CMD>; input-enable; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8365.dtsi b/arch/arm64/boot/dts/mediatek/mt8365.dtsi index 24581f7410aa..eb449bfa8803 100644 --- a/arch/arm64/boot/dts/mediatek/mt8365.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8365.dtsi @@ -300,9 +300,8 @@ }; scpsys: syscon@10006000 { - compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd"; + compatible = "mediatek,mt8365-scpsys", "syscon", "simple-mfd"; reg = <0 0x10006000 0 0x1000>; - #power-domain-cells = <1>; /* System Power Manager */ spm: power-controller { diff --git a/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts new file mode 100644 index 000000000000..1474bef7e754 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-genio-700-evk.dts @@ -0,0 +1,880 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Author: Chris Chen <[email protected]> + * Pablo Sun <[email protected]> + * Macpaul Lin <[email protected]> + */ +/dts-v1/; + +#include "mt8188.dtsi" +#include "mt6359.dtsi" +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/pinctrl/mediatek,mt8188-pinfunc.h> +#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> +#include <dt-bindings/spmi/spmi.h> +#include <dt-bindings/usb/pd.h> + +/ { + model = "MediaTek Genio-700 EVK"; + compatible = "mediatek,mt8390-evk", "mediatek,mt8390", + "mediatek,mt8188"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x2 0x00000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + }; + + common_fixed_5v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "5v_en"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 10 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + edp_panel_fixed_3v3: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "edp_panel_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + gpio = <&pio 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&edp_panel_3v3_en_pins>; + }; + + gpio_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "gpio_3v3_en"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 9 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + sdio_fixed_1v8: regulator-3 { + compatible = "regulator-fixed"; + regulator-name = "sdio_io"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + enable-active-high; + regulator-always-on; + }; + + sdio_fixed_3v3: regulator-4 { + compatible = "regulator-fixed"; + regulator-name = "sdio_card"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 74 GPIO_ACTIVE_HIGH>; + enable-active-high; + regulator-always-on; + }; + + touch0_fixed_3v3: regulator-5 { + compatible = "regulator-fixed"; + regulator-name = "touch_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 119 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_hub_fixed_3v3: regulator-6 { + compatible = "regulator-fixed"; + regulator-name = "usb_hub_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&pio 112 GPIO_ACTIVE_HIGH>; /* HUB_3V3_EN */ + startup-delay-us = <10000>; + enable-active-high; + }; + + usb_hub_reset_1v8: regulator-7 { + compatible = "regulator-fixed"; + regulator-name = "usb_hub_reset"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + gpio = <&pio 7 GPIO_ACTIVE_HIGH>; /* HUB_RESET */ + vin-supply = <&usb_hub_fixed_3v3>; + }; + + usb_p0_vbus: regulator-8 { + compatible = "regulator-fixed"; + regulator-name = "usb_p0_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 84 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p1_vbus: regulator-9 { + compatible = "regulator-fixed"; + regulator-name = "usb_p1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + gpio = <&pio 87 GPIO_ACTIVE_HIGH>; + enable-active-high; + }; + + usb_p2_vbus: regulator-10 { + compatible = "regulator-fixed"; + regulator-name = "usb_p2_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; + + touchscreen@5d { + compatible = "goodix,gt9271"; + reg = <0x5d>; + interrupt-parent = <&pio>; + interrupts-extended = <&pio 6 IRQ_TYPE_EDGE_RISING>; + irq-gpios = <&pio 6 GPIO_ACTIVE_HIGH>; + reset-gpios = <&pio 5 GPIO_ACTIVE_HIGH>; + AVDD28-supply = <&touch0_fixed_3v3>; + VDDIO-supply = <&mt6359_vio18_ldo_reg>; + pinctrl-names = "default"; + pinctrl-0 = <&touch_pins>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c4_pins>; + pinctrl-1 = <&rt1715_int_pins>; + clock-frequency = <1000000>; + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x1481b>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mmc1 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>; + pinctrl-1 = <&mmc1_uhs_pins>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + no-sdio; + cd-gpios = <&pio 2 GPIO_ACTIVE_LOW>; + vmmc-supply = <&mt6359_vpa_buck_reg>; + vqmmc-supply = <&mt6359_vsim1_ldo_reg>; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-max-microvolt = <3100000>; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vufs_ldo_reg { + regulator-always-on; +}; + +&mt6359codec { + mediatek,mic-type-0 = <1>; /* ACC */ + mediatek,mic-type-1 = <3>; /* DCC */ +}; + +&pio { + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO101__FUNC_O_AUD_CLK_MOSI>, + <PINMUX_GPIO102__FUNC_O_AUD_SYNC_MOSI>, + <PINMUX_GPIO103__FUNC_O_AUD_DAT_MOSI0>, + <PINMUX_GPIO104__FUNC_O_AUD_DAT_MOSI1>, + <PINMUX_GPIO105__FUNC_I0_AUD_DAT_MISO0>, + <PINMUX_GPIO106__FUNC_I0_AUD_DAT_MISO1>, + <PINMUX_GPIO107__FUNC_B0_I2SIN_MCK>, + <PINMUX_GPIO108__FUNC_B0_I2SIN_BCK>, + <PINMUX_GPIO109__FUNC_B0_I2SIN_WS>, + <PINMUX_GPIO110__FUNC_I0_I2SIN_D0>, + <PINMUX_GPIO114__FUNC_O_I2SO2_MCK>, + <PINMUX_GPIO115__FUNC_B0_I2SO2_BCK>, + <PINMUX_GPIO116__FUNC_B0_I2SO2_WS>, + <PINMUX_GPIO117__FUNC_O_I2SO2_D0>, + <PINMUX_GPIO118__FUNC_O_I2SO2_D1>, + <PINMUX_GPIO121__FUNC_B0_PCM_CLK>, + <PINMUX_GPIO122__FUNC_B0_PCM_SYNC>, + <PINMUX_GPIO124__FUNC_I0_PCM_DI>, + <PINMUX_GPIO125__FUNC_O_DMIC1_CLK>, + <PINMUX_GPIO126__FUNC_I0_DMIC1_DAT>, + <PINMUX_GPIO128__FUNC_O_DMIC2_CLK>, + <PINMUX_GPIO129__FUNC_I0_DMIC2_DAT>; + }; + }; + + dptx_pins: dptx-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO46__FUNC_I0_DP_TX_HPD>; + bias-pull-up; + }; + }; + + edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { + pins1 { + pinmux = <PINMUX_GPIO15__FUNC_B_GPIO15>; + output-high; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>, + <PINMUX_GPIO140__FUNC_I0_GBE_RXC>, + <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>, + <PINMUX_GPIO142__FUNC_O_GBE_TXEN>; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>, + <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>; + drive-strength = <8>; + input-enable; + }; + + pins-power { + pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>, + <PINMUX_GPIO146__FUNC_B_GPIO146>; + output-high; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>, + <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>, + <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>, + <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>; + drive-strength = <8>; + }; + + pins-txd { + pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>, + <PINMUX_GPIO132__FUNC_O_GBE_TXD2>, + <PINMUX_GPIO133__FUNC_O_GBE_TXD1>, + <PINMUX_GPIO134__FUNC_O_GBE_TXD0>; + drive-strength = <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>, + <PINMUX_GPIO140__FUNC_B_GPIO140>, + <PINMUX_GPIO141__FUNC_B_GPIO141>, + <PINMUX_GPIO142__FUNC_B_GPIO142>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>, + <PINMUX_GPIO144__FUNC_B_GPIO144>; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>, + <PINMUX_GPIO136__FUNC_B_GPIO136>, + <PINMUX_GPIO137__FUNC_B_GPIO137>, + <PINMUX_GPIO138__FUNC_B_GPIO138>; + }; + + pins-txd { + pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>, + <PINMUX_GPIO132__FUNC_B_GPIO132>, + <PINMUX_GPIO133__FUNC_B_GPIO133>, + <PINMUX_GPIO134__FUNC_B_GPIO134>; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, + <PINMUX_GPIO55__FUNC_B1_SCL0>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>, + <PINMUX_GPIO57__FUNC_B1_SCL1>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, + <PINMUX_GPIO59__FUNC_B1_SCL2>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, + <PINMUX_GPIO61__FUNC_B1_SCL3>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux = <PINMUX_GPIO64__FUNC_B1_SDA4>, + <PINMUX_GPIO63__FUNC_B1_SCL4>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>, + <PINMUX_GPIO65__FUNC_B1_SCL5>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>, + <PINMUX_GPIO67__FUNC_B1_SCL6>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + gpio_key_pins: gpio-key-pins { + pins { + pinmux = <PINMUX_GPIO42__FUNC_B1_KPCOL0>, + <PINMUX_GPIO43__FUNC_B1_KPCOL1>, + <PINMUX_GPIO44__FUNC_B1_KPROW0>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, + <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, + <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, + <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, + <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-insert { + pinmux = <PINMUX_GPIO2__FUNC_B_GPIO2>; + bias-pull-up; + }; + }; + + mmc1_uhs_pins: mmc1-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO164__FUNC_B1_MSDC1_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO163__FUNC_B1_MSDC1_CMD>, + <PINMUX_GPIO165__FUNC_B1_MSDC1_DAT0>, + <PINMUX_GPIO166__FUNC_B1_MSDC1_DAT1>, + <PINMUX_GPIO167__FUNC_B1_MSDC1_DAT2>, + <PINMUX_GPIO168__FUNC_B1_MSDC1_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc2_default_pins: mmc2-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; + drive-strength = <4>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, + <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, + <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, + <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, + <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-pcm { + pinmux = <PINMUX_GPIO123__FUNC_O_PCM_DO>; + }; + }; + + mmc2_uhs_pins: mmc2-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO170__FUNC_B1_MSDC2_CLK>; + drive-strength = <4>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO169__FUNC_B1_MSDC2_CMD>, + <PINMUX_GPIO171__FUNC_B1_MSDC2_DAT0>, + <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>, + <PINMUX_GPIO173__FUNC_B1_MSDC2_DAT2>, + <PINMUX_GPIO174__FUNC_B1_MSDC2_DAT3>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc2_eint_pins: mmc2-eint-pins { + pins-dat1 { + pinmux = <PINMUX_GPIO172__FUNC_B_GPIO172>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc2_dat1_pins: mmc2-dat1-pins { + pins-dat1 { + pinmux = <PINMUX_GPIO172__FUNC_B1_MSDC2_DAT1>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + panel_default_pins: panel-default-pins { + pins-dcdc { + pinmux = <PINMUX_GPIO45__FUNC_B_GPIO45>; + output-low; + }; + + pins-en { + pinmux = <PINMUX_GPIO111__FUNC_B_GPIO111>; + output-low; + }; + + pins-rst { + pinmux = <PINMUX_GPIO25__FUNC_B_GPIO25>; + output-high; + }; + }; + + rt1715_int_pins: rt1715-int-pins { + pins_cmd0_dat { + pinmux = <PINMUX_GPIO12__FUNC_B_GPIO12>; + bias-pull-up; + input-enable; + }; + }; + + spi0_pins: spi0-pins { + pins-spi { + pinmux = <PINMUX_GPIO69__FUNC_O_SPIM0_CSB>, + <PINMUX_GPIO70__FUNC_O_SPIM0_CLK>, + <PINMUX_GPIO71__FUNC_B0_SPIM0_MOSI>, + <PINMUX_GPIO72__FUNC_B0_SPIM0_MISO>; + bias-disable; + }; + }; + + spi1_pins: spi1-pins { + pins-spi { + pinmux = <PINMUX_GPIO75__FUNC_O_SPIM1_CSB>, + <PINMUX_GPIO76__FUNC_O_SPIM1_CLK>, + <PINMUX_GPIO77__FUNC_B0_SPIM1_MOSI>, + <PINMUX_GPIO78__FUNC_B0_SPIM1_MISO>; + bias-disable; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>, + <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>, + <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>, + <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>; + bias-disable; + }; + }; + + touch_pins: touch-pins { + pins-irq { + pinmux = <PINMUX_GPIO6__FUNC_B_GPIO6>; + input-enable; + bias-disable; + }; + + pins-reset { + pinmux = <PINMUX_GPIO5__FUNC_B_GPIO5>; + output-high; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, + <PINMUX_GPIO32__FUNC_I1_URXD0>; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = <PINMUX_GPIO33__FUNC_O_UTXD1>, + <PINMUX_GPIO34__FUNC_I1_URXD1>; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>, + <PINMUX_GPIO36__FUNC_I1_URXD2>; + bias-pull-up; + }; + }; + + usb_default_pins: usb-default-pins { + pins-iddig { + pinmux = <PINMUX_GPIO83__FUNC_B_GPIO83>; + input-enable; + bias-pull-up; + }; + + pins-valid { + pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>; + input-enable; + }; + + pins-vbus { + pinmux = <PINMUX_GPIO84__FUNC_O_USB_DRVVBUS>; + output-high; + }; + + }; + + usb1_default_pins: usb1-default-pins { + pins-valid { + pinmux = <PINMUX_GPIO88__FUNC_I0_VBUSVALID_1P>; + input-enable; + }; + + pins-usb-hub-3v3-en { + pinmux = <PINMUX_GPIO112__FUNC_B_GPIO112>; + output-high; + }; + }; + + wifi_pwrseq_pins: wifi-pwrseq-pins { + pins-wifi-enable { + pinmux = <PINMUX_GPIO127__FUNC_B_GPIO127>; + output-low; + }; + }; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&xhci0 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; +}; + +&xhci1 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + vbus-supply = <&usb_hub_reset_1v8>; +}; + +&xhci2 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts index 1558649f633c..a06610fff8ad 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-genio-1200-evk.dts @@ -475,7 +475,7 @@ <PINMUX_GPIO86__FUNC_GBE_RXC>, <PINMUX_GPIO87__FUNC_GBE_RXDV>, <PINMUX_GPIO88__FUNC_GBE_TXEN>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; }; pins-mdio { @@ -502,7 +502,7 @@ <PINMUX_GPIO78__FUNC_GBE_TXD2>, <PINMUX_GPIO79__FUNC_GBE_TXD1>, <PINMUX_GPIO80__FUNC_GBE_TXD0>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; }; }; @@ -567,7 +567,7 @@ pinmux = <PINMUX_GPIO12__FUNC_SDA2>, <PINMUX_GPIO13__FUNC_SCL2>; bias-pull-up = <MTK_PULL_SET_RSEL_111>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; }; }; @@ -582,7 +582,7 @@ mmc0_default_pins: mmc0-default-pins { pins-clk { pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -597,13 +597,13 @@ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, <PINMUX_GPIO121__FUNC_MSDC0_CMD>; input-enable; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; pins-rst { pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; - drive-strength = <MTK_DRIVE_6mA>; + drive-strength = <6>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; @@ -611,7 +611,7 @@ mmc0_uhs_pins: mmc0-uhs-pins { pins-clk { pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -626,19 +626,19 @@ <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, <PINMUX_GPIO121__FUNC_MSDC0_CMD>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; pins-ds { pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; pins-rst { pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; @@ -646,7 +646,7 @@ mmc1_default_pins: mmc1-default-pins { pins-clk { pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -657,7 +657,7 @@ <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; @@ -665,7 +665,7 @@ mmc1_uhs_pins: mmc1-uhs-pins { pins-clk { pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-down = <MTK_PUPD_SET_R1R0_10>; }; @@ -676,7 +676,7 @@ <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; input-enable; - drive-strength = <MTK_DRIVE_8mA>; + drive-strength = <8>; bias-pull-up = <MTK_PUPD_SET_R1R0_01>; }; }; @@ -854,6 +854,10 @@ &u3phy1 { status = "okay"; + + u3port1: usb-phy@700 { + mediatek,force-mode; + }; }; &u3phy2 { @@ -900,6 +904,8 @@ }; &xhci1 { + phys = <&u2port1 PHY_TYPE_USB2>, + <&u3port1 PHY_TYPE_USB3>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts new file mode 100644 index 000000000000..e4b2af9489a8 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8395-kontron-3-5-sbc-i1200.dts @@ -0,0 +1,1127 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Kontron Europe GmbH + * + * Author: Michael Walle <[email protected]> + */ +/dts-v1/; + +#include "mt8195.dtsi" +#include "mt6359.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h> +#include <dt-bindings/leds/common.h> +#include <dt-bindings/pinctrl/mt8195-pinfunc.h> +#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> +#include <dt-bindings/spmi/spmi.h> + +/ { + model = "Kontron 3.5\"-SBC-i1200"; + compatible = "kontron,3-5-sbc-i1200", "mediatek,mt8395", "mediatek,mt8195"; + + aliases { + mmc0 = &mmc0; + mmc1 = &mmc1; + serial0 = &uart1; + serial1 = &uart2; + serial2 = &uart3; + serial3 = &uart4; + serial4 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + gpio-keys { + compatible = "gpio-keys"; + pinctrl-names = "default"; + pinctrl-0 = <&gpio_keys_pins>; + + key-0 { + gpios = <&pio 106 GPIO_ACTIVE_LOW>; + label = "volume_up"; + linux,code = <KEY_VOLUMEUP>; + wakeup-source; + debounce-interval = <15>; + }; + }; + + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&led_pins>; + + led-0 { + gpios = <&pio 107 GPIO_ACTIVE_HIGH>; + default-state = "keep"; + function = LED_FUNCTION_POWER; + color = <LED_COLOR_ID_GREEN>; + }; + }; + + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 0x0 0x80000000>; + }; + + vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + vpu_mem: memory@53000000 { + compatible = "shared-dma-pool"; + reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_mem: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + snd_dma_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0x1100000>; + no-map; + }; + + apu_mem: memory@62000000 { + compatible = "shared-dma-pool"; + reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ + }; + }; + + thermal_sensor0: thermal-sensor-0 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 0>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; + + thermal_sensor1: thermal-sensor-1 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 1>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; + + thermal_sensor2: thermal-sensor-2 { + compatible = "generic-adc-thermal"; + #thermal-sensor-cells = <0>; + io-channels = <&auxadc 2>; + io-channel-names = "sensor-channel"; + temperature-lookup-table = <(-25000) 1474 + (-20000) 1374 + (-15000) 1260 + (-10000) 1134 + (-5000) 1004 + 0 874 + 5000 750 + 10000 635 + 15000 532 + 20000 443 + 25000 367 + 30000 303 + 35000 250 + 40000 206 + 45000 170 + 50000 141 + 55000 117 + 60000 97 + 65000 81 + 70000 68 + 75000 57 + 80000 48 + 85000 41 + 90000 35 + 95000 30 + 100000 25 + 105000 22 + 110000 19 + 115000 16 + 120000 14 + 125000 12 + 130000 10 + 135000 9 + 140000 8 + 145000 7 + 150000 6>; + }; +}; + +&auxadc { + status = "okay"; +}; + +ð { + phy-mode ="rgmii-id"; + phy-handle = <ðernet_phy0>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + status = "okay"; + + mdio { + ethernet_phy0: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <0x1>; + interrupts-extended = <&pio 94 IRQ_TYPE_LEVEL_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + reset-gpios = <&pio 93 GPIO_ACTIVE_HIGH>; + }; + }; +}; + +&gpu { + status = "okay"; + mali-supply = <&mt6315_7_vbuck1>; +}; + +/* CSI1/CSI2 connector */ +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* CSI3 connector */ +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; + + /* LVDS bridge @f */ +}; + +/* Touch panel connector */ +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <100000>; + status = "okay"; +}; + +/* B2B connector */ +&i2c4 { + clock-frequency = <100000>; + pinctrl-0 = <&i2c4_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&i2c6 { + clock-frequency = <400000>; + pinctrl-0 = <&i2c6_pins>; + pinctrl-names = "default"; + status = "okay"; + + mt6360: pmic@34 { + compatible = "mediatek,mt6360"; + reg = <0x34>; + interrupt-controller; + interrupts-extended = <&pio 101 IRQ_TYPE_EDGE_FALLING>; + interrupt-names = "IRQB"; + #interrupt-cells = <1>; + + regulator { + compatible = "mediatek,mt6360-regulator"; + LDO_VIN1-supply = <&vsys>; + LDO_VIN2-supply = <&vsys>; + LDO_VIN3-supply = <&vsys>; + + mt6360_buck1: BUCK1 { + regulator-name = "emi_vdd2"; + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP + MT6360_OPMODE_ULP>; + regulator-always-on; + }; + + mt6360_buck2: BUCK2 { + regulator-name = "emi_vddq"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP + MT6360_OPMODE_ULP>; + regulator-always-on; + }; + + mt6360_ldo1: LDO1 { + regulator-name = "mt6360_ldo1"; /* Test point */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <3600000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo2: LDO2 { + regulator-name = "panel1_p1v8"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo3: LDO3 { + regulator-name = "vmc_pmu"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo5: LDO5 { + regulator-name = "vmch_pmu"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo6: LDO6 { + regulator-name = "mt6360_ldo6"; /* Test point */ + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <2100000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + }; + + mt6360_ldo7: LDO7 { + regulator-name = "emi_vmddr_en"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-allowed-modes = <MT6360_OPMODE_NORMAL + MT6360_OPMODE_LP>; + regulator-always-on; + }; + }; + }; +}; + +&mmc0 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + hs400-ds-delay = <0x14c11>; + cap-mmc-highspeed; + cap-mmc-hw-reset; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + no-sdio; + no-sd; + non-removable; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + status = "okay"; +}; + +&mmc1 { + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc1_default_pins>, <&mmc1_detect_pins>; + pinctrl-1 = <&mmc1_default_pins>; + cd-gpios = <&pio 129 GPIO_ACTIVE_LOW>; + bus-width = <4>; + max-frequency = <200000000>; + cap-sd-highspeed; + sd-uhs-sdr50; + sd-uhs-sdr104; + no-mmc; + vmmc-supply = <&mt6360_ldo5>; + vqmmc-supply = <&mt6360_ldo3>; + status = "okay"; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc1_buck_reg { + regulator-always-on; +}; + +&mt6359_vproc2_buck_reg { + regulator-always-on; +}; + +&mt6359_vpu_buck_reg { + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_md_ldo_reg { + regulator-always-on; +}; + +&mt6359_vsram_others_ldo_reg { + regulator-always-on; +}; + +&nor_flash { + pinctrl-names = "default"; + pinctrl-0 = <&nor_pins_default>; + status = "okay"; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <52000000>; + spi-rx-bus-width = <2>; + spi-tx-bus-width = <2>; + }; +}; + +&pcie0 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins_default>; + status = "okay"; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&pio { + eth_default_pins: eth-default-pins { + pins-txd { + pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, + <PINMUX_GPIO78__FUNC_GBE_TXD2>, + <PINMUX_GPIO79__FUNC_GBE_TXD1>, + <PINMUX_GPIO80__FUNC_GBE_TXD0>; + drive-strength = <8>; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, + <PINMUX_GPIO82__FUNC_GBE_RXD2>, + <PINMUX_GPIO83__FUNC_GBE_RXD1>, + <PINMUX_GPIO84__FUNC_GBE_RXD0>; + }; + + pins-cc { + pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, + <PINMUX_GPIO86__FUNC_GBE_RXC>, + <PINMUX_GPIO87__FUNC_GBE_RXDV>, + <PINMUX_GPIO88__FUNC_GBE_TXEN>; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, + <PINMUX_GPIO90__FUNC_GBE_MDIO>; + input-enable; + }; + + pins-power { + pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, + <PINMUX_GPIO92__FUNC_GPIO92>; + output-high; + }; + + pins-reset { + pinmux = <PINMUX_GPIO93__FUNC_GPIO93>; + output-high; + }; + + pins-interrupt { + pinmux = <PINMUX_GPIO94__FUNC_GPIO94>; + input-enable; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-txd { + pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, + <PINMUX_GPIO78__FUNC_GPIO78>, + <PINMUX_GPIO79__FUNC_GPIO79>, + <PINMUX_GPIO80__FUNC_GPIO80>; + }; + + pins-cc { + pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, + <PINMUX_GPIO88__FUNC_GPIO88>, + <PINMUX_GPIO87__FUNC_GPIO87>, + <PINMUX_GPIO86__FUNC_GPIO86>; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, + <PINMUX_GPIO82__FUNC_GPIO82>, + <PINMUX_GPIO83__FUNC_GPIO83>, + <PINMUX_GPIO84__FUNC_GPIO84>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, + <PINMUX_GPIO90__FUNC_GPIO90>; + input-disable; + bias-disable; + }; + }; + + gpio_keys_pins: gpio-keys-pins { + pins { + pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; + input-enable; + }; + }; + + i2c0_pins: i2c0-pins { + pins { + pinmux = <PINMUX_GPIO8__FUNC_SDA0>, + <PINMUX_GPIO9__FUNC_SCL0>; + bias-pull-up = <MTK_PULL_SET_RSEL_111>; + drive-strength-microamp = <1000>; + }; + }; + + i2c1_pins: i2c1-pins { + pins { + pinmux = <PINMUX_GPIO10__FUNC_SDA1>, + <PINMUX_GPIO11__FUNC_SCL1>; + bias-pull-up = <MTK_PULL_SET_RSEL_111>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO12__FUNC_SDA2>, + <PINMUX_GPIO13__FUNC_SCL2>; + bias-pull-up = <MTK_PULL_SET_RSEL_111>; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = <PINMUX_GPIO14__FUNC_SDA3>, + <PINMUX_GPIO15__FUNC_SCL3>; + bias-pull-up = <MTK_PULL_SET_RSEL_111>; + drive-strength-microamp = <1000>; + }; + }; + + i2c4_pins: i2c4-pins { + pins { + pinmux = <PINMUX_GPIO16__FUNC_SDA4>, + <PINMUX_GPIO17__FUNC_SCL4>; + bias-pull-up = <MTK_PULL_SET_RSEL_111>; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = <PINMUX_GPIO25__FUNC_SDA6>, + <PINMUX_GPIO26__FUNC_SCL6>; + bias-pull-up; + drive-strength-microamp = <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO121__FUNC_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_default_pins: mmc1-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, + <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, + <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, + <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, + <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc1_detect_pins: mmc1-detect-pins { + pins-insert { + pinmux = <PINMUX_GPIO129__FUNC_GPIO129>; + bias-pull-up; + }; + }; + + nor_pins_default: nor-default-pins { + pins-ck-io { + pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>, + <PINMUX_GPIO141__FUNC_SPINOR_CK>, + <PINMUX_GPIO143__FUNC_SPINOR_IO1>; + drive-strength = <6>; + bias-pull-down; + }; + + pins-cs { + pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>; + drive-strength = <6>; + bias-pull-up; + }; + }; + + pcie0_pins_default: pcie0-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, + <PINMUX_GPIO20__FUNC_PERSTN>, + <PINMUX_GPIO21__FUNC_CLKREQN>; + bias-pull-up; + }; + }; + + pcie1_pins_default: pcie1-default-pins { + pins-bus { + pinmux = <PINMUX_GPIO0__FUNC_PERSTN_1>, + <PINMUX_GPIO1__FUNC_CLKREQN_1>, + <PINMUX_GPIO2__FUNC_WAKEN_1>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + led_pins: led-pins { + pins-power-en { + pinmux = <PINMUX_GPIO107__FUNC_GPIO107>; + output-high; + }; + }; + + spi0_pins: spi0-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO132__FUNC_SPIM0_CSB>, + <PINMUX_GPIO134__FUNC_SPIM0_MO>, + <PINMUX_GPIO133__FUNC_SPIM0_CLK>; + bias-disable; + }; + + pins-miso { + pinmux = <PINMUX_GPIO135__FUNC_SPIM0_MI>; + bias-pull-down; + }; + }; + + spi1_pins: spi1-default-pins { + pins-cs-mosi-clk { + pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, + <PINMUX_GPIO138__FUNC_SPIM1_MO>, + <PINMUX_GPIO137__FUNC_SPIM1_CLK>; + bias-disable; + }; + + pins-miso { + pinmux = <PINMUX_GPIO139__FUNC_SPIM1_MI>; + bias-pull-down; + }; + }; + + uart0_pins: uart0-pins { + pins-rx { + pinmux = <PINMUX_GPIO99__FUNC_URXD0>; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = <PINMUX_GPIO98__FUNC_UTXD0>; + }; + }; + + uart1_pins: uart1-pins { + pins-rx { + pinmux = <PINMUX_GPIO103__FUNC_URXD1>; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = <PINMUX_GPIO102__FUNC_UTXD1>; + }; + + pins-rts { + pinmux = <PINMUX_GPIO100__FUNC_URTS1>; + }; + + pins-cts { + pinmux = <PINMUX_GPIO101__FUNC_UCTS1>; + input-enable; + }; + }; + + uart2_pins: uart2-pins { + pins-rx { + pinmux = <PINMUX_GPIO68__FUNC_URXD2>; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = <PINMUX_GPIO67__FUNC_UTXD2>; + }; + + pins-rts { + pinmux = <PINMUX_GPIO66__FUNC_URTS2>; + }; + + pins-cts { + pinmux = <PINMUX_GPIO65__FUNC_UCTS2>; + input-enable; + }; + }; + + uart3_pins: uart3-pins { + pins-rx { + pinmux = <PINMUX_GPIO5__FUNC_URXD3>; + input-enable; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-tx { + pinmux = <PINMUX_GPIO4__FUNC_UTXD3>; + }; + }; + + uart4_pins: uart4-pins { + pins-rx { + pinmux = <PINMUX_GPIO7__FUNC_URXD4>; + input-enable; + bias-pull-up; + }; + + pins-tx { + pinmux = <PINMUX_GPIO6__FUNC_UTXD4>; + }; + }; +}; + +&pmic { + interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; +}; + +&scp { + memory-region = <&scp_mem>; + firmware-name = "mediatek/mt8195/scp.img"; + status = "okay"; +}; + +&spmi { + #address-cells = <2>; + #size-cells = <0>; + + mt6315@6 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x6 SPMI_USID>; + + regulators { + mt6315_6_vbuck1: vbuck1 { + regulator-name = "Vbcpu"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; + + mt6315@7 { + compatible = "mediatek,mt6315-regulator"; + reg = <0x7 SPMI_USID>; + + regulators { + mt6315_7_vbuck1: vbuck1 { + regulator-name = "Vgpu"; + regulator-min-microvolt = <625000>; + regulator-max-microvolt = <1193750>; + regulator-enable-ramp-delay = <256>; + regulator-ramp-delay = <6250>; + regulator-allowed-modes = <0 1 2>; + regulator-always-on; + }; + }; + }; +}; + +/* USB3.2 front port */ +&ssusb0 { + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +/* USB2.0 M.2 Key-E */ +&ssusb2 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +/* USB2.0 to on-board usb hub */ +&ssusb3 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + status = "okay"; +}; + +&spi0 { + pinctrl-names = "default"; + pinctrl-0 = <&spi0_pins>; + mediatek,pad-select = <0>; + status = "okay"; + + tpm: tpm@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <18500000>; + }; +}; + +/* B2B connector */ +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins>; + mediatek,pad-select = <0>; + status = "okay"; +}; + +&thermal_zones { + cpu-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor0>; + + trips { + trip-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pcb-top-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor1>; + + trips { + trip-alert { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; + + pcb-bottom-thermal { + polling-delay = <1000>; /* milliseconds */ + polling-delay-passive = <0>; /* milliseconds */ + thermal-sensors = <&thermal_sensor2>; + + trips { + trip-alert { + temperature = <75000>; + hysteresis = <2000>; + type = "passive"; + }; + + trip-crit { + temperature = <85000>; + hysteresis = <2000>; + type = "critical"; + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_pins>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&uart1_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&uart2_pins>; + uart-has-rtscts; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&uart3_pins>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins>; + status = "okay"; +}; + +/* USB3 */ +&u3phy0 { + status = "okay"; +}; + +/* PCIe1/USB2 */ +&u3phy1 { + status = "okay"; +}; + +/* USB2 */ +&u3phy2 { + status = "okay"; +}; + +/* USB2 */ +&u3phy3 { + status = "okay"; +}; + +/* USB3.2 front port */ +&xhci0 { + status = "okay"; +}; + +/* USB2.0 M.2 Key-B */ +&xhci1 { + vusb33-supply = <&mt6359_vusb_ldo_reg>; + mediatek,u3p-dis-msk = <0x01>; + status = "okay"; +}; + +/* USB2.0 M.2 Key-E */ +&xhci2 { + status = "okay"; +}; + +/* USB2.0 to on-board usb hub */ +&xhci3 { + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts index e5d9b671a405..4b5f6cf16f70 100644 --- a/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts +++ b/arch/arm64/boot/dts/mediatek/mt8395-radxa-nio-12l.dts @@ -140,6 +140,38 @@ }; }; +&cpu0 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu1 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu2 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu3 { + cpu-supply = <&mt6359_vcore_buck_reg>; +}; + +&cpu4 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu5 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu6 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + +&cpu7 { + cpu-supply = <&mt6315_6_vbuck1>; +}; + ð { phy-mode = "rgmii-rxid"; phy-handle = <&rgmii_phy>; @@ -343,6 +375,14 @@ }; }; +&mfg0 { + domain-supply = <&mt6315_7_vbuck1>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + /* MMC0 Controller: eMMC (HS400). Power lines are shared with UFS! */ &mmc0 { pinctrl-names = "default", "state_uhs"; @@ -434,6 +474,8 @@ }; &pio { + mediatek,rsel-resistance-in-si-unit; + eth_default_pins: eth-default-pins { pins-cc { pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, @@ -509,7 +551,7 @@ pins-bus { pinmux = <PINMUX_GPIO12__FUNC_SDA2>, <PINMUX_GPIO13__FUNC_SCL2>; - bias-pull-up = <MTK_PULL_SET_RSEL_111>; + bias-pull-up = <1000>; drive-strength = <6>; drive-strength-microamp = <1000>; }; @@ -519,7 +561,7 @@ pins-bus { pinmux = <PINMUX_GPIO16__FUNC_SDA4>, <PINMUX_GPIO17__FUNC_SCL4>; - bias-pull-up = <MTK_PULL_SET_RSEL_111>; + bias-pull-up = <1000>; drive-strength-microamp = <1000>; }; }; @@ -528,7 +570,7 @@ pins { pinmux = <PINMUX_GPIO25__FUNC_SDA6>, <PINMUX_GPIO26__FUNC_SCL6>; - bias-pull-up = <MTK_PULL_SET_RSEL_111>; + bias-disable; }; }; @@ -683,6 +725,26 @@ }; }; + usb3_port0_pins: usb3p0-default-pins { + pins-vbus { + pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>; + input-enable; + }; + }; + + usb2_port0_pins: usb2p0-default-pins { + pins-iddig { + pinmux = <PINMUX_GPIO130__FUNC_IDDIG_1P>; + input-enable; + bias-pull-up; + }; + + pins-vbus { + pinmux = <PINMUX_GPIO131__FUNC_USB_DRVVBUS_1P>; + output-low; + }; + }; + wifi_vreg_pins: wifi-vreg-pins { pins-wifi-pmu-en { pinmux = <PINMUX_GPIO65__FUNC_GPIO65>; @@ -707,6 +769,10 @@ status = "okay"; }; +&pciephy { + status = "okay"; +}; + &pmic { interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; }; @@ -774,6 +840,18 @@ }; }; +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + &uart0 { /* Exposed at 40 pin connector */ pinctrl-0 = <&uart0_pins>; @@ -789,6 +867,8 @@ }; &ssusb0 { + pinctrl-names = "default"; + pinctrl-0 = <&usb3_port0_pins>; role-switch-default-mode = "host"; usb-role-switch; vusb33-supply = <&mt6359_vusb_ldo_reg>; @@ -802,6 +882,8 @@ }; &ssusb2 { + pinctrl-names = "default"; + pinctrl-0 = <&usb2_port0_pins>; vusb33-supply = <&mt6359_vusb_ldo_reg>; status = "okay"; }; |