diff options
| -rw-r--r-- | Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp | 41 | ||||
| -rw-r--r-- | Documentation/devicetree/bindings/arm/marvell,berlin.txt | 16 | ||||
| -rw-r--r-- | arch/arm/boot/dts/berlin2.dtsi | 6 | ||||
| -rw-r--r-- | arch/arm/boot/dts/berlin2q-marvell-dmp.dts | 8 | ||||
| -rw-r--r-- | arch/arm/boot/dts/berlin2q.dtsi | 80 |
5 files changed, 151 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp new file mode 100644 index 000000000000..cd236b727e2a --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cpu-enable-method/marvell,berlin-smp @@ -0,0 +1,41 @@ +======================================================== +Secondary CPU enable-method "marvell,berlin-smp" binding +======================================================== + +This document describes the "marvell,berlin-smp" method for enabling secondary +CPUs. To apply to all CPUs, a single "marvell,berlin-smp" enable method should +be defined in the "cpus" node. + +Enable method name: "marvell,berlin-smp" +Compatible machines: "marvell,berlin2" and "marvell,berlin2q" +Compatible CPUs: "marvell,pj4b" and "arm,cortex-a9" +Related properties: (none) + +Note: +This enable method needs valid nodes compatible with "arm,cortex-a9-scu" and +"marvell,berlin-cpu-ctrl"[1]. + +Example: + + cpus { + #address-cells = <1>; + #size-cells = <0>; + enable-method = "marvell,berlin-smp"; + + cpu@0 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <0>; + }; + + cpu@1 { + compatible = "marvell,pj4b"; + device_type = "cpu"; + next-level-cache = <&l2>; + reg = <1>; + }; + }; + +-- +[1] arm/marvell,berlin.txt diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.txt b/Documentation/devicetree/bindings/arm/marvell,berlin.txt index 94013a9a8769..904de5781f44 100644 --- a/Documentation/devicetree/bindings/arm/marvell,berlin.txt +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.txt @@ -24,6 +24,22 @@ SoC and board used. Currently known SoC compatibles are: ... } +* Marvell Berlin CPU control bindings + +CPU control register allows various operations on CPUs, like resetting them +independently. + +Required properties: +- compatible: should be "marvell,berlin-cpu-ctrl" +- reg: address and length of the register set + +Example: + +cpu-ctrl@f7dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xf7dd0000 0x10000>; +}; + * Marvell Berlin2 chip control binding Marvell Berlin SoCs have a chip control register set providing several diff --git a/arch/arm/boot/dts/berlin2.dtsi b/arch/arm/boot/dts/berlin2.dtsi index 2477dac4d643..9d7c810ebd0b 100644 --- a/arch/arm/boot/dts/berlin2.dtsi +++ b/arch/arm/boot/dts/berlin2.dtsi @@ -22,6 +22,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,berlin-smp"; cpu@0 { compatible = "marvell,pj4b"; @@ -78,6 +79,11 @@ clocks = <&chip CLKID_TWD>; }; + cpu-ctrl@dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xdd0000 0x10000>; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; diff --git a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts index 995150f93795..a357ce02a64e 100644 --- a/arch/arm/boot/dts/berlin2q-marvell-dmp.dts +++ b/arch/arm/boot/dts/berlin2q-marvell-dmp.dts @@ -34,6 +34,14 @@ status = "okay"; }; +&i2c0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; +}; + &uart0 { status = "okay"; }; diff --git a/arch/arm/boot/dts/berlin2q.dtsi b/arch/arm/boot/dts/berlin2q.dtsi index 635a16a64cb4..400c40fceccc 100644 --- a/arch/arm/boot/dts/berlin2q.dtsi +++ b/arch/arm/boot/dts/berlin2q.dtsi @@ -18,6 +18,7 @@ cpus { #address-cells = <1>; #size-cells = <0>; + enable-method = "marvell,berlin-smp"; cpu@0 { compatible = "arm,cortex-a9"; @@ -90,6 +91,8 @@ compatible = "arm,pl310-cache"; reg = <0xac0000 0x1000>; cache-level = <2>; + arm,data-latency = <2 2 2>; + arm,tag-latency = <2 2 2>; }; scu: snoop-control-unit@ad0000 { @@ -111,6 +114,11 @@ #interrupt-cells = <3>; }; + cpu-ctrl@dd0000 { + compatible = "marvell,berlin-cpu-ctrl"; + reg = <0xdd0000 0x10000>; + }; + apb@e80000 { compatible = "simple-bus"; #address-cells = <1>; @@ -191,6 +199,32 @@ }; }; + i2c0: i2c@1400 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1400 0x100>; + interrupt-parent = <&aic>; + interrupts = <4>; + clocks = <&chip CLKID_CFG>; + pinctrl-0 = <&twsi0_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c1: i2c@1800 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x1800 0x100>; + interrupt-parent = <&aic>; + interrupts = <5>; + clocks = <&chip CLKID_CFG>; + pinctrl-0 = <&twsi1_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + timer0: timer@2c00 { compatible = "snps,dw-apb-timer"; reg = <0x2c00 0x14>; @@ -301,6 +335,16 @@ reg = <0xea0000 0x400>, <0xdd0170 0x10>; clocks = <&refclk>; clock-names = "refclk"; + + twsi0_pmux: twsi0-pmux { + groups = "G6"; + function = "twsi0"; + }; + + twsi1_pmux: twsi1-pmux { + groups = "G7"; + function = "twsi1"; + }; }; apb@fc0000 { @@ -311,6 +355,32 @@ ranges = <0 0xfc0000 0x10000>; interrupt-parent = <&sic>; + i2c2: i2c@7000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x7000 0x100>; + interrupt-parent = <&sic>; + interrupts = <6>; + clocks = <&refclk>; + pinctrl-0 = <&twsi2_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + + i2c3: i2c@8000 { + compatible = "snps,designware-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x8000 0x100>; + interrupt-parent = <&sic>; + interrupts = <7>; + clocks = <&refclk>; + pinctrl-0 = <&twsi3_pmux>; + pinctrl-names = "default"; + status = "disabled"; + }; + uart0: uart@9000 { compatible = "snps,dw-apb-uart"; reg = <0x9000 0x100>; @@ -348,6 +418,16 @@ groups = "GSM14"; function = "uart1"; }; + + twsi2_pmux: twsi2-pmux { + groups = "GSM13"; + function = "twsi2"; + }; + + twsi3_pmux: twsi3-pmux { + groups = "GSM14"; + function = "twsi3"; + }; }; sic: interrupt-controller@e000 { |