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-rw-r--r--arch/arm/boot/dts/dra7-l4.dtsi1
-rw-r--r--arch/arm/boot/dts/dra7.dtsi5
-rw-r--r--arch/arm/boot/dts/omap4-l4.dtsi4
-rw-r--r--arch/arm/boot/dts/omap4.dtsi8
-rw-r--r--arch/arm/boot/dts/omap5.dtsi4
-rw-r--r--arch/arm/mach-omap2/Kconfig3
-rw-r--r--arch/arm/mach-omap2/Makefile3
-rw-r--r--arch/arm/mach-omap2/common.h9
-rw-r--r--arch/arm/mach-omap2/io.c5
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.c8
-rw-r--r--arch/arm/mach-omap2/omap_hwmod.h1
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_44xx_data.c877
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_54xx_data.c467
-rw-r--r--arch/arm/mach-omap2/omap_hwmod_7xx_data.c719
14 files changed, 1 insertions, 2113 deletions
diff --git a/arch/arm/boot/dts/dra7-l4.dtsi b/arch/arm/boot/dts/dra7-l4.dtsi
index 1c50ae7b0e17..ceec18e0909f 100644
--- a/arch/arm/boot/dts/dra7-l4.dtsi
+++ b/arch/arm/boot/dts/dra7-l4.dtsi
@@ -576,7 +576,6 @@
target-module@40000 { /* 0x4a140000, ap 31 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "sata";
reg = <0x400fc 4>,
<0x41100 4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/dra7.dtsi b/arch/arm/boot/dts/dra7.dtsi
index c988f1d039cf..84d0b5102945 100644
--- a/arch/arm/boot/dts/dra7.dtsi
+++ b/arch/arm/boot/dts/dra7.dtsi
@@ -214,7 +214,6 @@
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <0>;
- ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
ti,syscon-lane-sel = <&scm_conf_pcie 0x18>;
@@ -242,7 +241,6 @@
num-lanes = <1>;
num-ib-windows = <4>;
num-ob-windows = <16>;
- ti,hwmods = "pcie1";
phys = <&pcie1_phy>;
phy-names = "pcie-phy0";
ti,syscon-unaligned-access = <&scm_conf1 0x14 1>;
@@ -287,7 +285,6 @@
#interrupt-cells = <1>;
num-lanes = <1>;
linux,pci-domain = <1>;
- ti,hwmods = "pcie2";
phys = <&pcie2_phy>;
phy-names = "pcie-phy0";
interrupt-map-mask = <0 0 0 7>;
@@ -468,7 +465,6 @@
target-module@4e000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dmm";
reg = <0x4e000000 0x4>,
<0x4e000010 0x4>;
reg-names = "rev", "sysc";
@@ -772,7 +768,6 @@
target-module@4b300000 {
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "qspi";
reg = <0x4b300000 0x4>,
<0x4b300010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap4-l4.dtsi b/arch/arm/boot/dts/omap4-l4.dtsi
index c83849dfde24..99721673d7af 100644
--- a/arch/arm/boot/dts/omap4-l4.dtsi
+++ b/arch/arm/boot/dts/omap4-l4.dtsi
@@ -46,7 +46,6 @@
target-module@2000 { /* 0x4a002000, ap 3 06.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "ctrl_module_core";
reg = <0x2000 0x4>,
<0x2010 0x4>;
reg-names = "rev", "sysc";
@@ -656,7 +655,6 @@
target-module@0 { /* 0x4a100000, ap 21 2a.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "ctrl_module_pad_core";
reg = <0x0 0x4>,
<0x10 0x4>;
reg-names = "rev", "sysc";
@@ -1047,7 +1045,6 @@
target-module@c000 { /* 0x4a30c000, ap 19 2c.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "ctrl_module_wkup";
reg = <0xc000 0x4>,
<0xc010 0x4>;
reg-names = "rev", "sysc";
@@ -1208,7 +1205,6 @@
target-module@e000 { /* 0x4a31e000, ap 21 30.0 */
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "ctrl_module_pad_wkup";
reg = <0xe000 0x4>,
<0xe010 0x4>;
reg-names = "rev", "sysc";
diff --git a/arch/arm/boot/dts/omap4.dtsi b/arch/arm/boot/dts/omap4.dtsi
index fc0be942dbeb..2bbff9032be3 100644
--- a/arch/arm/boot/dts/omap4.dtsi
+++ b/arch/arm/boot/dts/omap4.dtsi
@@ -107,7 +107,7 @@
* hierarchy.
*/
ocp {
- compatible = "simple-bus";
+ compatible = "simple-pm-bus";
power-domains = <&prm_l4per>;
clocks = <&l3_1_clkctrl OMAP4_L3_MAIN_1_CLKCTRL 0>,
<&l3_2_clkctrl OMAP4_L3_MAIN_2_CLKCTRL 0>,
@@ -115,7 +115,6 @@
#address-cells = <1>;
#size-cells = <1>;
ranges;
- ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
l3-noc@44000000 {
compatible = "ti,omap4-l3-noc";
@@ -192,7 +191,6 @@
target-module@52000000 {
compatible = "ti,sysc-omap4", "ti,sysc";
- ti,hwmods = "iss";
reg = <0x52000000 0x4>,
<0x52000010 0x4>;
reg-names = "rev", "sysc";
@@ -224,7 +222,6 @@
*/
target-module@54000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "debugss";
power-domains = <&prm_emu>;
clocks = <&emu_sys_clkctrl OMAP4_DEBUGSS_CLKCTRL 0>;
clock-names = "fck";
@@ -288,7 +285,6 @@
target-module@4e000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dmm";
reg = <0x4e000000 0x4>,
<0x4e000010 0x4>;
reg-names = "rev", "sysc";
@@ -308,7 +304,6 @@
target-module@4c000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "emif1";
reg = <0x4c000000 0x4>;
reg-names = "rev";
clocks = <&l3_emif_clkctrl OMAP4_EMIF1_CLKCTRL 0>;
@@ -331,7 +326,6 @@
target-module@4d000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "emif2";
reg = <0x4d000000 0x4>;
reg-names = "rev";
clocks = <&l3_emif_clkctrl OMAP4_EMIF2_CLKCTRL 0>;
diff --git a/arch/arm/boot/dts/omap5.dtsi b/arch/arm/boot/dts/omap5.dtsi
index 681fee379b88..bac6fa838793 100644
--- a/arch/arm/boot/dts/omap5.dtsi
+++ b/arch/arm/boot/dts/omap5.dtsi
@@ -151,7 +151,6 @@
#size-cells = <1>;
ranges = <0 0 0 0xc0000000>;
dma-ranges = <0x80000000 0x0 0x80000000 0x80000000>;
- ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3";
l3-noc@44000000 {
compatible = "ti,omap5-l3-noc";
@@ -279,7 +278,6 @@
target-module@4e000000 {
compatible = "ti,sysc-omap2", "ti,sysc";
- ti,hwmods = "dmm";
reg = <0x4e000000 0x4>,
<0x4e000010 0x4>;
reg-names = "rev", "sysc";
@@ -299,7 +297,6 @@
target-module@4c000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "emif1";
reg = <0x4c000000 0x4>;
reg-names = "rev";
clocks = <&emif_clkctrl OMAP5_EMIF1_CLKCTRL 0>;
@@ -322,7 +319,6 @@
target-module@4d000000 {
compatible = "ti,sysc-omap4-simple", "ti,sysc";
- ti,hwmods = "emif2";
reg = <0x4d000000 0x4>;
reg-names = "rev";
clocks = <&emif_clkctrl OMAP5_EMIF2_CLKCTRL 0>;
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 4178c0ee46eb..7df8f5276ddf 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -34,7 +34,6 @@ config ARCH_OMAP4
select ARM_GIC
select HAVE_ARM_SCU if SMP
select HAVE_ARM_TWD if SMP
- select OMAP_HWMOD
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PL310_ERRATA_588369 if CACHE_L2X0
@@ -54,7 +53,6 @@ config SOC_OMAP5
select HAVE_ARM_SCU if SMP
select HAVE_ARM_ARCH_TIMER
select ARM_ERRATA_798181 if SMP
- select OMAP_HWMOD
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PM_OPP
@@ -90,7 +88,6 @@ config SOC_DRA7XX
select HAVE_ARM_ARCH_TIMER
select IRQ_CROSSBAR
select ARM_ERRATA_798181 if SMP
- select OMAP_HWMOD
select OMAP_INTERCONNECT
select OMAP_INTERCONNECT_BARRIER
select PM_OPP
diff --git a/arch/arm/mach-omap2/Makefile b/arch/arm/mach-omap2/Makefile
index 9bcfb34a2206..d03646e2f81f 100644
--- a/arch/arm/mach-omap2/Makefile
+++ b/arch/arm/mach-omap2/Makefile
@@ -207,9 +207,6 @@ obj-$(CONFIG_SOC_OMAP2430) += omap_hwmod_2430_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_2xxx_3xxx_ipblock_data.o
obj-$(CONFIG_ARCH_OMAP3) += omap_hwmod_3xxx_data.o
obj-$(CONFIG_SOC_TI81XX) += omap_hwmod_81xx_data.o
-obj-$(CONFIG_ARCH_OMAP4) += omap_hwmod_44xx_data.o
-obj-$(CONFIG_SOC_OMAP5) += omap_hwmod_54xx_data.o
-obj-$(CONFIG_SOC_DRA7XX) += omap_hwmod_7xx_data.o
# OMAP2420 MSDI controller integration support ("MMC")
obj-$(CONFIG_SOC_OMAP2420) += msdi.o
diff --git a/arch/arm/mach-omap2/common.h b/arch/arm/mach-omap2/common.h
index 49926eced5f1..db446f271f5d 100644
--- a/arch/arm/mach-omap2/common.h
+++ b/arch/arm/mach-omap2/common.h
@@ -343,15 +343,6 @@ static inline void omap5_secondary_hyp_startup(void)
}
#endif
-#ifdef CONFIG_SOC_DRA7XX
-extern int dra7xx_pciess_reset(struct omap_hwmod *oh);
-#else
-static inline int dra7xx_pciess_reset(struct omap_hwmod *oh)
-{
- return 0;
-}
-#endif
-
struct omap_system_dma_plat_info;
void pdata_quirks_init(const struct of_device_id *);
diff --git a/arch/arm/mach-omap2/io.c b/arch/arm/mach-omap2/io.c
index 060ba6957b7c..92648f8a3b4c 100644
--- a/arch/arm/mach-omap2/io.c
+++ b/arch/arm/mach-omap2/io.c
@@ -615,7 +615,6 @@ void __init omap4430_init_early(void)
omap44xx_voltagedomains_init();
omap44xx_powerdomains_init();
omap44xx_clockdomains_init();
- omap44xx_hwmod_init();
omap_hwmod_init_postsetup();
omap_l2_cache_init();
omap_clk_soc_init = omap4xxx_dt_clk_init;
@@ -643,8 +642,6 @@ void __init omap5_init_early(void)
omap54xx_voltagedomains_init();
omap54xx_powerdomains_init();
omap54xx_clockdomains_init();
- omap54xx_hwmod_init();
- omap_hwmod_init_postsetup();
omap_clk_soc_init = omap5xxx_dt_clk_init;
omap_secure_init();
}
@@ -667,8 +664,6 @@ void __init dra7xx_init_early(void)
dra7xxx_check_revision();
dra7xx_powerdomains_init();
dra7xx_clockdomains_init();
- dra7xx_hwmod_init();
- omap_hwmod_init_postsetup();
omap_clk_soc_init = dra7xx_dt_clk_init;
omap_secure_init();
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.c b/arch/arm/mach-omap2/omap_hwmod.c
index 2310cd56e99b..f61783ca5268 100644
--- a/arch/arm/mach-omap2/omap_hwmod.c
+++ b/arch/arm/mach-omap2/omap_hwmod.c
@@ -3495,10 +3495,6 @@ static const struct omap_hwmod_reset omap24xx_reset_quirks[] = {
{ .match = "msdi", .len = 4, .reset = omap_msdi_reset, },
};
-static const struct omap_hwmod_reset dra7_reset_quirks[] = {
- { .match = "pcie", .len = 4, .reset = dra7xx_pciess_reset, },
-};
-
static const struct omap_hwmod_reset omap_reset_quirks[] = {
{ .match = "dss_core", .len = 8, .reset = omap_dss_reset, },
{ .match = "hdq1w", .len = 5, .reset = omap_hdq1w_reset, },
@@ -3534,10 +3530,6 @@ omap_hwmod_init_reset_quirks(struct device *dev, struct omap_hwmod *oh,
omap24xx_reset_quirks,
ARRAY_SIZE(omap24xx_reset_quirks));
- if (soc_is_dra7xx())
- omap_hwmod_init_reset_quirk(dev, oh, data, dra7_reset_quirks,
- ARRAY_SIZE(dra7_reset_quirks));
-
omap_hwmod_init_reset_quirk(dev, oh, data, omap_reset_quirks,
ARRAY_SIZE(omap_reset_quirks));
}
diff --git a/arch/arm/mach-omap2/omap_hwmod.h b/arch/arm/mach-omap2/omap_hwmod.h
index eebf2fdf434c..a0835ab8452b 100644
--- a/arch/arm/mach-omap2/omap_hwmod.h
+++ b/arch/arm/mach-omap2/omap_hwmod.h
@@ -671,7 +671,6 @@ extern int omap2420_hwmod_init(void);
extern int omap2430_hwmod_init(void);
extern int omap3xxx_hwmod_init(void);
extern int omap44xx_hwmod_init(void);
-extern int omap54xx_hwmod_init(void);
extern int am33xx_hwmod_init(void);
extern int dm814x_hwmod_init(void);
extern int dm816x_hwmod_init(void);
diff --git a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c b/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
deleted file mode 100644
index 6aa3b8e81a0c..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_44xx_data.c
+++ /dev/null
@@ -1,877 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware modules present on the OMAP44xx chips
- *
- * Copyright (C) 2009-2012 Texas Instruments, Inc.
- * Copyright (C) 2009-2010 Nokia Corporation
- *
- * Paul Walmsley
- * Benoit Cousson
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- * Note that this file is currently not in sync with autogeneration scripts.
- * The above note to be removed, once it is synced up.
- */
-
-#include <linux/io.h>
-
-#include "omap_hwmod.h"
-#include "omap_hwmod_common_data.h"
-#include "cm1_44xx.h"
-#include "cm2_44xx.h"
-#include "prm44xx.h"
-#include "prm-regbits-44xx.h"
-
-/* Base offset for all OMAP4 interrupts external to MPUSS */
-#define OMAP44XX_IRQ_GIC_START 32
-
-/*
- * IP blocks
- */
-
-/*
- * 'dmm' class
- * instance(s): dmm
- */
-static struct omap_hwmod_class omap44xx_dmm_hwmod_class = {
- .name = "dmm",
-};
-
-/* dmm */
-static struct omap_hwmod omap44xx_dmm_hwmod = {
- .name = "dmm",
- .class = &omap44xx_dmm_hwmod_class,
- .clkdm_name = "l3_emif_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'l3' class
- * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
- */
-static struct omap_hwmod_class omap44xx_l3_hwmod_class = {
- .name = "l3",
-};
-
-/* l3_instr */
-static struct omap_hwmod omap44xx_l3_instr_hwmod = {
- .name = "l3_instr",
- .class = &omap44xx_l3_hwmod_class,
- .clkdm_name = "l3_instr_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* l3_main_1 */
-static struct omap_hwmod omap44xx_l3_main_1_hwmod = {
- .name = "l3_main_1",
- .class = &omap44xx_l3_hwmod_class,
- .clkdm_name = "l3_1_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l3_main_2 */
-static struct omap_hwmod omap44xx_l3_main_2_hwmod = {
- .name = "l3_main_2",
- .class = &omap44xx_l3_hwmod_class,
- .clkdm_name = "l3_2_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l3_main_3 */
-static struct omap_hwmod omap44xx_l3_main_3_hwmod = {
- .name = "l3_main_3",
- .class = &omap44xx_l3_hwmod_class,
- .clkdm_name = "l3_instr_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'l4' class
- * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
- */
-static struct omap_hwmod_class omap44xx_l4_hwmod_class = {
- .name = "l4",
-};
-
-/* l4_cfg */
-static struct omap_hwmod omap44xx_l4_cfg_hwmod = {
- .name = "l4_cfg",
- .class = &omap44xx_l4_hwmod_class,
- .clkdm_name = "l4_cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l4_per */
-static struct omap_hwmod omap44xx_l4_per_hwmod = {
- .name = "l4_per",
- .class = &omap44xx_l4_hwmod_class,
- .clkdm_name = "l4_per_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l4_wkup */
-static struct omap_hwmod omap44xx_l4_wkup_hwmod = {
- .name = "l4_wkup",
- .class = &omap44xx_l4_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'mpu_bus' class
- * instance(s): mpu_private
- */
-static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = {
- .name = "mpu_bus",
-};
-
-/* mpu_private */
-static struct omap_hwmod omap44xx_mpu_private_hwmod = {
- .name = "mpu_private",
- .class = &omap44xx_mpu_bus_hwmod_class,
- .clkdm_name = "mpuss_clkdm",
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/*
- * 'ocp_wp_noc' class
- * instance(s): ocp_wp_noc
- */
-static struct omap_hwmod_class omap44xx_ocp_wp_noc_hwmod_class = {
- .name = "ocp_wp_noc",
-};
-
-/* ocp_wp_noc */
-static struct omap_hwmod omap44xx_ocp_wp_noc_hwmod = {
- .name = "ocp_wp_noc",
- .class = &omap44xx_ocp_wp_noc_hwmod_class,
- .clkdm_name = "l3_instr_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3INSTR_OCP_WP1_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3INSTR_OCP_WP1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * Modules omap_hwmod structures
- *
- * The following IPs are excluded for the moment because:
- * - They do not need an explicit SW control using omap_hwmod API.
- * - They still need to be validated with the driver
- * properly adapted to omap_hwmod / omap_device
- *
- * usim
- */
-
-/*
- * 'ctrl_module' class
- * attila core control module + core pad control module + wkup pad control
- * module + attila wkup control module
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_ctrl_module_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_ctrl_module_hwmod_class = {
- .name = "ctrl_module",
- .sysc = &omap44xx_ctrl_module_sysc,
-};
-
-/* ctrl_module_core */
-static struct omap_hwmod omap44xx_ctrl_module_core_hwmod = {
- .name = "ctrl_module_core",
- .class = &omap44xx_ctrl_module_hwmod_class,
- .clkdm_name = "l4_cfg_clkdm",
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* ctrl_module_pad_core */
-static struct omap_hwmod omap44xx_ctrl_module_pad_core_hwmod = {
- .name = "ctrl_module_pad_core",
- .class = &omap44xx_ctrl_module_hwmod_class,
- .clkdm_name = "l4_cfg_clkdm",
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* ctrl_module_wkup */
-static struct omap_hwmod omap44xx_ctrl_module_wkup_hwmod = {
- .name = "ctrl_module_wkup",
- .class = &omap44xx_ctrl_module_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* ctrl_module_pad_wkup */
-static struct omap_hwmod omap44xx_ctrl_module_pad_wkup_hwmod = {
- .name = "ctrl_module_pad_wkup",
- .class = &omap44xx_ctrl_module_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/*
- * 'debugss' class
- * debug and emulation sub system
- */
-
-static struct omap_hwmod_class omap44xx_debugss_hwmod_class = {
- .name = "debugss",
-};
-
-/* debugss */
-static struct omap_hwmod omap44xx_debugss_hwmod = {
- .name = "debugss",
- .class = &omap44xx_debugss_hwmod_class,
- .clkdm_name = "emu_sys_clkdm",
- .main_clk = "trace_clk_div_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_EMU_DEBUGSS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_EMU_DEBUGSS_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'emif' class
- * external memory interface no1
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = {
- .rev_offs = 0x0000,
-};
-
-static struct omap_hwmod_class omap44xx_emif_hwmod_class = {
- .name = "emif",
- .sysc = &omap44xx_emif_sysc,
-};
-
-/* emif1 */
-static struct omap_hwmod omap44xx_emif1_hwmod = {
- .name = "emif1",
- .class = &omap44xx_emif_hwmod_class,
- .clkdm_name = "l3_emif_clkdm",
- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "ddrphy_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* emif2 */
-static struct omap_hwmod omap44xx_emif2_hwmod = {
- .name = "emif2",
- .class = &omap44xx_emif_hwmod_class,
- .clkdm_name = "l3_emif_clkdm",
- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "ddrphy_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'iss' class
- * external images sensor pixel data processor
- */
-
-static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = {
- .rev_offs = 0x0000,
- .sysc_offs = 0x0010,
- /*
- * ISS needs 100 OCP clk cycles delay after a softreset before
- * accessing sysconfig again.
- * The lowest frequency at the moment for L3 bus is 100 MHz, so
- * 1usec delay is needed. Add an x2 margin to be safe (2 usecs).
- *
- * TODO: Indicate errata when available.
- */
- .srst_udelay = 2,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS |
- SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap44xx_iss_hwmod_class = {
- .name = "iss",
- .sysc = &omap44xx_iss_sysc,
-};
-
-/* iss */
-static struct omap_hwmod_opt_clk iss_opt_clks[] = {
- { .role = "ctrlclk", .clk = "iss_ctrlclk" },
-};
-
-static struct omap_hwmod omap44xx_iss_hwmod = {
- .name = "iss",
- .class = &omap44xx_iss_hwmod_class,
- .clkdm_name = "iss_clkdm",
- .main_clk = "ducati_clk_mux_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
- .opt_clks = iss_opt_clks,
- .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks),
-};
-
-/*
- * 'mpu' class
- * mpu sub-system
- */
-
-static struct omap_hwmod_class omap44xx_mpu_hwmod_class = {
- .name = "mpu",
-};
-
-/* mpu */
-static struct omap_hwmod omap44xx_mpu_hwmod = {
- .name = "mpu",
- .class = &omap44xx_mpu_hwmod_class,
- .clkdm_name = "mpuss_clkdm",
- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_mpu_m2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'ocmc_ram' class
- * top-level core on-chip ram
- */
-
-static struct omap_hwmod_class omap44xx_ocmc_ram_hwmod_class = {
- .name = "ocmc_ram",
-};
-
-/* ocmc_ram */
-static struct omap_hwmod omap44xx_ocmc_ram_hwmod = {
- .name = "ocmc_ram",
- .class = &omap44xx_ocmc_ram_hwmod_class,
- .clkdm_name = "l3_2_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_L3_2_OCMC_RAM_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_L3_2_OCMC_RAM_CONTEXT_OFFSET,
- },
- },
-};
-
-
-/*
- * 'prcm' class
- * power and reset manager (part of the prcm infrastructure) + clock manager 2
- * + clock manager 1 (in always on power domain) + local prm in mpu
- */
-
-static struct omap_hwmod_class omap44xx_prcm_hwmod_class = {
- .name = "prcm",
-};
-
-/* prcm_mpu */
-static struct omap_hwmod omap44xx_prcm_mpu_hwmod = {
- .name = "prcm_mpu",
- .class = &omap44xx_prcm_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .flags = HWMOD_NO_IDLEST,
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* cm_core_aon */
-static struct omap_hwmod omap44xx_cm_core_aon_hwmod = {
- .name = "cm_core_aon",
- .class = &omap44xx_prcm_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* cm_core */
-static struct omap_hwmod omap44xx_cm_core_hwmod = {
- .name = "cm_core",
- .class = &omap44xx_prcm_hwmod_class,
- .flags = HWMOD_NO_IDLEST,
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* prm */
-static struct omap_hwmod_rst_info omap44xx_prm_resets[] = {
- { .name = "rst_global_warm_sw", .rst_shift = 0 },
- { .name = "rst_global_cold_sw", .rst_shift = 1 },
-};
-
-static struct omap_hwmod omap44xx_prm_hwmod = {
- .name = "prm",
- .class = &omap44xx_prcm_hwmod_class,
- .rst_lines = omap44xx_prm_resets,
- .rst_lines_cnt = ARRAY_SIZE(omap44xx_prm_resets),
-};
-
-/*
- * 'scrm' class
- * system clock and reset manager
- */
-
-static struct omap_hwmod_class omap44xx_scrm_hwmod_class = {
- .name = "scrm",
-};
-
-/* scrm */
-static struct omap_hwmod omap44xx_scrm_hwmod = {
- .name = "scrm",
- .class = &omap44xx_scrm_hwmod_class,
- .clkdm_name = "l4_wkup_clkdm",
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/*
- * 'sl2if' class
- * shared level 2 memory interface
- */
-
-static struct omap_hwmod_class omap44xx_sl2if_hwmod_class = {
- .name = "sl2if",
-};
-
-/* sl2if */
-static struct omap_hwmod omap44xx_sl2if_hwmod = {
- .name = "sl2if",
- .class = &omap44xx_sl2if_hwmod_class,
- .clkdm_name = "ivahd_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP4_CM_IVAHD_SL2_CLKCTRL_OFFSET,
- .context_offs = OMAP4_RM_IVAHD_SL2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * interfaces
- */
-
-/* l3_main_1 -> dmm */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_dmm_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_SDMA,
-};
-
-/* mpu -> dmm */
-static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_dmm_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_3 -> l3_instr */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = {
- .master = &omap44xx_l3_main_3_hwmod,
- .slave = &omap44xx_l3_instr_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* ocp_wp_noc -> l3_instr */
-static struct omap_hwmod_ocp_if omap44xx_ocp_wp_noc__l3_instr = {
- .master = &omap44xx_ocp_wp_noc_hwmod,
- .slave = &omap44xx_l3_instr_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_l3_main_1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* debugss -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_debugss__l3_main_2 = {
- .master = &omap44xx_debugss_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "dbgclk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* iss -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = {
- .master = &omap44xx_iss_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l4_cfg -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_l3_main_2_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l3_main_3_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_l3_main_3_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_l3_main_3_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_cfg */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = {
- .master = &omap44xx_l3_main_1_hwmod,
- .slave = &omap44xx_l4_cfg_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> l4_per */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_l4_per_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l4_wkup */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_l4_wkup_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> mpu_private */
-static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_mpu_private_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> ocp_wp_noc */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ocp_wp_noc = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_ocp_wp_noc_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> ctrl_module_core */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_core = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_ctrl_module_core_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> ctrl_module_pad_core */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__ctrl_module_pad_core = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_ctrl_module_pad_core_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> ctrl_module_wkup */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_wkup = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_ctrl_module_wkup_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> ctrl_module_pad_wkup */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__ctrl_module_pad_wkup = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_ctrl_module_pad_wkup_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_instr -> debugss */
-static struct omap_hwmod_ocp_if omap44xx_l3_instr__debugss = {
- .master = &omap44xx_l3_instr_hwmod,
- .slave = &omap44xx_debugss_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> iss */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_iss_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> ocmc_ram */
-static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ocmc_ram = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_ocmc_ram_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu_private -> prcm_mpu */
-static struct omap_hwmod_ocp_if omap44xx_mpu_private__prcm_mpu = {
- .master = &omap44xx_mpu_private_hwmod,
- .slave = &omap44xx_prcm_mpu_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> cm_core_aon */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__cm_core_aon = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_cm_core_aon_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> cm_core */
-static struct omap_hwmod_ocp_if omap44xx_l4_cfg__cm_core = {
- .master = &omap44xx_l4_cfg_hwmod,
- .slave = &omap44xx_cm_core_hwmod,
- .clk = "l4_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> prm */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__prm = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_prm_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> scrm */
-static struct omap_hwmod_ocp_if omap44xx_l4_wkup__scrm = {
- .master = &omap44xx_l4_wkup_hwmod,
- .slave = &omap44xx_scrm_hwmod,
- .clk = "l4_wkup_clk_mux_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> sl2if */
-static struct omap_hwmod_ocp_if __maybe_unused omap44xx_l3_main_2__sl2if = {
- .master = &omap44xx_l3_main_2_hwmod,
- .slave = &omap44xx_sl2if_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> emif1 */
-static struct omap_hwmod_ocp_if omap44xx_mpu__emif1 = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_emif1_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> emif2 */
-static struct omap_hwmod_ocp_if omap44xx_mpu__emif2 = {
- .master = &omap44xx_mpu_hwmod,
- .slave = &omap44xx_emif2_hwmod,
- .clk = "l3_div_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = {
- &omap44xx_l3_main_1__dmm,
- &omap44xx_mpu__dmm,
- &omap44xx_l3_main_3__l3_instr,
- &omap44xx_ocp_wp_noc__l3_instr,
- &omap44xx_l3_main_2__l3_main_1,
- &omap44xx_l4_cfg__l3_main_1,
- &omap44xx_mpu__l3_main_1,
- &omap44xx_debugss__l3_main_2,
- &omap44xx_iss__l3_main_2,
- &omap44xx_l3_main_1__l3_main_2,
- &omap44xx_l4_cfg__l3_main_2,
- &omap44xx_l3_main_1__l3_main_3,
- &omap44xx_l3_main_2__l3_main_3,
- &omap44xx_l4_cfg__l3_main_3,
- &omap44xx_l3_main_1__l4_cfg,
- &omap44xx_l3_main_2__l4_per,
- &omap44xx_l4_cfg__l4_wkup,
- &omap44xx_mpu__mpu_private,
- &omap44xx_l4_cfg__ocp_wp_noc,
- &omap44xx_l4_cfg__ctrl_module_core,
- &omap44xx_l4_cfg__ctrl_module_pad_core,
- &omap44xx_l4_wkup__ctrl_module_wkup,
- &omap44xx_l4_wkup__ctrl_module_pad_wkup,
- &omap44xx_l3_instr__debugss,
- &omap44xx_l3_main_2__iss,
- &omap44xx_l3_main_2__ocmc_ram,
- &omap44xx_mpu_private__prcm_mpu,
- &omap44xx_l4_wkup__cm_core_aon,
- &omap44xx_l4_cfg__cm_core,
- &omap44xx_l4_wkup__prm,
- &omap44xx_l4_wkup__scrm,
- /* &omap44xx_l3_main_2__sl2if, */
- &omap44xx_mpu__emif1,
- &omap44xx_mpu__emif2,
- NULL,
-};
-
-int __init omap44xx_hwmod_init(void)
-{
- omap_hwmod_init();
- return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs);
-}
-
diff --git a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c b/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
deleted file mode 100644
index 85b9ab4756ed..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_54xx_data.c
+++ /dev/null
@@ -1,467 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware modules present on the OMAP54xx chips
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
- *
- * Paul Walmsley
- * Benoit Cousson
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- */
-
-#include <linux/io.h>
-#include <linux/power/smartreflex.h>
-
-#include "omap_hwmod.h"
-#include "omap_hwmod_common_data.h"
-#include "cm1_54xx.h"
-#include "cm2_54xx.h"
-#include "prm54xx.h"
-
-/* Base offset for all OMAP5 interrupts external to MPUSS */
-#define OMAP54XX_IRQ_GIC_START 32
-
-/*
- * IP blocks
- */
-
-/*
- * 'dmm' class
- * instance(s): dmm
- */
-static struct omap_hwmod_class omap54xx_dmm_hwmod_class = {
- .name = "dmm",
-};
-
-/* dmm */
-static struct omap_hwmod omap54xx_dmm_hwmod = {
- .name = "dmm",
- .class = &omap54xx_dmm_hwmod_class,
- .clkdm_name = "emif_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_EMIF_DMM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'l3' class
- * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3
- */
-static struct omap_hwmod_class omap54xx_l3_hwmod_class = {
- .name = "l3",
-};
-
-/* l3_instr */
-static struct omap_hwmod omap54xx_l3_instr_hwmod = {
- .name = "l3_instr",
- .class = &omap54xx_l3_hwmod_class,
- .clkdm_name = "l3instr_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* l3_main_1 */
-static struct omap_hwmod omap54xx_l3_main_1_hwmod = {
- .name = "l3_main_1",
- .class = &omap54xx_l3_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l3_main_2 */
-static struct omap_hwmod omap54xx_l3_main_2_hwmod = {
- .name = "l3_main_2",
- .class = &omap54xx_l3_hwmod_class,
- .clkdm_name = "l3main2_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3MAIN2_L3_MAIN_2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3MAIN2_L3_MAIN_2_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l3_main_3 */
-static struct omap_hwmod omap54xx_l3_main_3_hwmod = {
- .name = "l3_main_3",
- .class = &omap54xx_l3_hwmod_class,
- .clkdm_name = "l3instr_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INSTR_L3_MAIN_3_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INSTR_L3_MAIN_3_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'l4' class
- * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup
- */
-static struct omap_hwmod_class omap54xx_l4_hwmod_class = {
- .name = "l4",
-};
-
-/* l4_cfg */
-static struct omap_hwmod omap54xx_l4_cfg_hwmod = {
- .name = "l4_cfg",
- .class = &omap54xx_l4_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l4_per */
-static struct omap_hwmod omap54xx_l4_per_hwmod = {
- .name = "l4_per",
- .class = &omap54xx_l4_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L4PER_L4_PER_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L4PER_L4_PER_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l4_wkup */
-static struct omap_hwmod omap54xx_l4_wkup_hwmod = {
- .name = "l4_wkup",
- .class = &omap54xx_l4_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'mpu_bus' class
- * instance(s): mpu_private
- */
-static struct omap_hwmod_class omap54xx_mpu_bus_hwmod_class = {
- .name = "mpu_bus",
-};
-
-/* mpu_private */
-static struct omap_hwmod omap54xx_mpu_private_hwmod = {
- .name = "mpu_private",
- .class = &omap54xx_mpu_bus_hwmod_class,
- .clkdm_name = "mpu_clkdm",
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/*
- * 'emif' class
- * external memory interface no1 (wrapper)
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_emif_sysc = {
- .rev_offs = 0x0000,
-};
-
-static struct omap_hwmod_class omap54xx_emif_hwmod_class = {
- .name = "emif",
- .sysc = &omap54xx_emif_sysc,
-};
-
-/* emif1 */
-static struct omap_hwmod omap54xx_emif1_hwmod = {
- .name = "emif1",
- .class = &omap54xx_emif_hwmod_class,
- .clkdm_name = "emif_clkdm",
- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_core_h11x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF1_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_EMIF_EMIF1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* emif2 */
-static struct omap_hwmod omap54xx_emif2_hwmod = {
- .name = "emif2",
- .class = &omap54xx_emif_hwmod_class,
- .clkdm_name = "emif_clkdm",
- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_core_h11x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_EMIF_EMIF2_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_EMIF_EMIF2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-
-
-
-/*
- * 'mpu' class
- * mpu sub-system
- */
-
-static struct omap_hwmod_class omap54xx_mpu_hwmod_class = {
- .name = "mpu",
-};
-
-/* mpu */
-static struct omap_hwmod omap54xx_mpu_hwmod = {
- .name = "mpu",
- .class = &omap54xx_mpu_hwmod_class,
- .clkdm_name = "mpu_clkdm",
- .flags = HWMOD_INIT_NO_IDLE,
- .main_clk = "dpll_mpu_m2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_MPU_MPU_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_MPU_MPU_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'sata' class
- * sata: serial ata interface gen2 compliant ( 1 rx/ 1 tx)
- */
-
-static struct omap_hwmod_class_sysconfig omap54xx_sata_sysc = {
- .rev_offs = 0x00fc,
- .sysc_offs = 0x0000,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class omap54xx_sata_hwmod_class = {
- .name = "sata",
- .sysc = &omap54xx_sata_sysc,
-};
-
-/* sata */
-static struct omap_hwmod omap54xx_sata_hwmod = {
- .name = "sata",
- .class = &omap54xx_sata_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "func_48m_fclk",
- .mpu_rt_idx = 1,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = OMAP54XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
- .context_offs = OMAP54XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* l4_cfg -> sata */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__sata = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_sata_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/*
- * Interfaces
- */
-
-/* l3_main_1 -> dmm */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_1__dmm = {
- .master = &omap54xx_l3_main_1_hwmod,
- .slave = &omap54xx_dmm_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_SDMA,
-};
-
-/* l3_main_3 -> l3_instr */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_3__l3_instr = {
- .master = &omap54xx_l3_main_3_hwmod,
- .slave = &omap54xx_l3_instr_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_1 = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_l3_main_1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_1 = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_l3_main_1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l3_main_1 */
-static struct omap_hwmod_ocp_if omap54xx_mpu__l3_main_1 = {
- .master = &omap54xx_mpu_hwmod,
- .slave = &omap54xx_l3_main_1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_2 = {
- .master = &omap54xx_l3_main_1_hwmod,
- .slave = &omap54xx_l3_main_2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l4_cfg -> l3_main_2 */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_2 = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_l3_main_2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l3_main_3 = {
- .master = &omap54xx_l3_main_1_hwmod,
- .slave = &omap54xx_l3_main_3_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_2 -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l3_main_3 = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_l3_main_3_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_3 */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__l3_main_3 = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_l3_main_3_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_cfg */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_cfg = {
- .master = &omap54xx_l3_main_1_hwmod,
- .slave = &omap54xx_l4_cfg_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> l4_per */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_2__l4_per = {
- .master = &omap54xx_l3_main_2_hwmod,
- .slave = &omap54xx_l4_per_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_wkup */
-static struct omap_hwmod_ocp_if omap54xx_l3_main_1__l4_wkup = {
- .master = &omap54xx_l3_main_1_hwmod,
- .slave = &omap54xx_l4_wkup_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> mpu_private */
-static struct omap_hwmod_ocp_if omap54xx_mpu__mpu_private = {
- .master = &omap54xx_mpu_hwmod,
- .slave = &omap54xx_mpu_private_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> emif1 */
-static struct omap_hwmod_ocp_if omap54xx_mpu__emif1 = {
- .master = &omap54xx_mpu_hwmod,
- .slave = &omap54xx_emif1_hwmod,
- .clk = "dpll_core_h11x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> emif2 */
-static struct omap_hwmod_ocp_if omap54xx_mpu__emif2 = {
- .master = &omap54xx_mpu_hwmod,
- .slave = &omap54xx_emif2_hwmod,
- .clk = "dpll_core_h11x2_ck",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> mpu */
-static struct omap_hwmod_ocp_if omap54xx_l4_cfg__mpu = {
- .master = &omap54xx_l4_cfg_hwmod,
- .slave = &omap54xx_mpu_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *omap54xx_hwmod_ocp_ifs[] __initdata = {
- &omap54xx_l3_main_1__dmm,
- &omap54xx_l3_main_3__l3_instr,
- &omap54xx_l3_main_2__l3_main_1,
- &omap54xx_l4_cfg__l3_main_1,
- &omap54xx_mpu__l3_main_1,
- &omap54xx_l3_main_1__l3_main_2,
- &omap54xx_l4_cfg__l3_main_2,
- &omap54xx_l3_main_1__l3_main_3,
- &omap54xx_l3_main_2__l3_main_3,
- &omap54xx_l4_cfg__l3_main_3,
- &omap54xx_l3_main_1__l4_cfg,
- &omap54xx_l3_main_2__l4_per,
- &omap54xx_l3_main_1__l4_wkup,
- &omap54xx_mpu__mpu_private,
- &omap54xx_mpu__emif1,
- &omap54xx_mpu__emif2,
- &omap54xx_l4_cfg__mpu,
- &omap54xx_l4_cfg__sata,
- NULL,
-};
-
-int __init omap54xx_hwmod_init(void)
-{
- omap_hwmod_init();
- return omap_hwmod_register_links(omap54xx_hwmod_ocp_ifs);
-}
diff --git a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c b/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
deleted file mode 100644
index 48c2a808bd46..000000000000
--- a/arch/arm/mach-omap2/omap_hwmod_7xx_data.c
+++ /dev/null
@@ -1,719 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * Hardware modules present on the DRA7xx chips
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - https://www.ti.com
- *
- * Paul Walmsley
- * Benoit Cousson
- *
- * This file is automatically generated from the OMAP hardware databases.
- * We respectfully ask that any modifications to this file be coordinated
- * with the public linux-omap@vger.kernel.org mailing list and the
- * authors above to ensure that the autogeneration scripts are kept
- * up-to-date with the file contents.
- */
-
-#include <linux/io.h>
-
-#include "omap_hwmod.h"
-#include "omap_hwmod_common_data.h"
-#include "cm1_7xx.h"
-#include "cm2_7xx.h"
-#include "prm7xx.h"
-#include "soc.h"
-
-/* Base offset for all DRA7XX interrupts external to MPUSS */
-#define DRA7XX_IRQ_GIC_START 32
-
-/*
- * IP blocks
- */
-
-/*
- * 'dmm' class
- * instance(s): dmm
- */
-static struct omap_hwmod_class dra7xx_dmm_hwmod_class = {
- .name = "dmm",
-};
-
-/* dmm */
-static struct omap_hwmod dra7xx_dmm_hwmod = {
- .name = "dmm",
- .class = &dra7xx_dmm_hwmod_class,
- .clkdm_name = "emif_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_EMIF_DMM_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_EMIF_DMM_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'l3' class
- * instance(s): l3_instr, l3_main_1, l3_main_2
- */
-static struct omap_hwmod_class dra7xx_l3_hwmod_class = {
- .name = "l3",
-};
-
-/* l3_instr */
-static struct omap_hwmod dra7xx_l3_instr_hwmod = {
- .name = "l3_instr",
- .class = &dra7xx_l3_hwmod_class,
- .clkdm_name = "l3instr_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/* l3_main_1 */
-static struct omap_hwmod dra7xx_l3_main_1_hwmod = {
- .name = "l3_main_1",
- .class = &dra7xx_l3_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_L3_MAIN_1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_L3_MAIN_1_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l3_main_2 */
-static struct omap_hwmod dra7xx_l3_main_2_hwmod = {
- .name = "l3_main_2",
- .class = &dra7xx_l3_hwmod_class,
- .clkdm_name = "l3instr_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INSTR_L3_MAIN_2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INSTR_L3_MAIN_2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_HWCTRL,
- },
- },
-};
-
-/*
- * 'l4' class
- * instance(s): l4_cfg, l4_per1, l4_per2, l4_per3, l4_wkup
- */
-static struct omap_hwmod_class dra7xx_l4_hwmod_class = {
- .name = "l4",
-};
-
-/* l4_cfg */
-static struct omap_hwmod dra7xx_l4_cfg_hwmod = {
- .name = "l4_cfg",
- .class = &dra7xx_l4_hwmod_class,
- .clkdm_name = "l4cfg_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4CFG_L4_CFG_CONTEXT_OFFSET,
- },
- },
-};
-
-/* l4_per1 */
-static struct omap_hwmod dra7xx_l4_per1_hwmod = {
- .name = "l4_per1",
- .class = &dra7xx_l4_hwmod_class,
- .clkdm_name = "l4per_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER_L4_PER1_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* l4_per2 */
-static struct omap_hwmod dra7xx_l4_per2_hwmod = {
- .name = "l4_per2",
- .class = &dra7xx_l4_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER2_L4_PER2_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* l4_per3 */
-static struct omap_hwmod dra7xx_l4_per3_hwmod = {
- .name = "l4_per3",
- .class = &dra7xx_l4_hwmod_class,
- .clkdm_name = "l4per3_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER3_L4_PER3_CLKCTRL_OFFSET,
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/* l4_wkup */
-static struct omap_hwmod dra7xx_l4_wkup_hwmod = {
- .name = "l4_wkup",
- .class = &dra7xx_l4_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_WKUPAON_L4_WKUP_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_WKUPAON_L4_WKUP_CONTEXT_OFFSET,
- },
- },
-};
-
-/*
- * 'atl' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_atl_hwmod_class = {
- .name = "atl",
-};
-
-/* atl */
-static struct omap_hwmod dra7xx_atl_hwmod = {
- .name = "atl",
- .class = &dra7xx_atl_hwmod_class,
- .clkdm_name = "atl_clkdm",
- .main_clk = "atl_gfclk_mux",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_ATL_ATL_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_ATL_ATL_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'bb2d' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_bb2d_hwmod_class = {
- .name = "bb2d",
-};
-
-/* bb2d */
-static struct omap_hwmod dra7xx_bb2d_hwmod = {
- .name = "bb2d",
- .class = &dra7xx_bb2d_hwmod_class,
- .clkdm_name = "dss_clkdm",
- .main_clk = "dpll_core_h24x2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_DSS_BB2D_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_DSS_BB2D_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'ctrl_module' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_ctrl_module_hwmod_class = {
- .name = "ctrl_module",
-};
-
-/* ctrl_module_wkup */
-static struct omap_hwmod dra7xx_ctrl_module_wkup_hwmod = {
- .name = "ctrl_module_wkup",
- .class = &dra7xx_ctrl_module_hwmod_class,
- .clkdm_name = "wkupaon_clkdm",
- .prcm = {
- .omap4 = {
- .flags = HWMOD_OMAP4_NO_CONTEXT_LOSS_BIT,
- },
- },
-};
-
-/*
- * 'mpu' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_mpu_hwmod_class = {
- .name = "mpu",
-};
-
-/* mpu */
-static struct omap_hwmod dra7xx_mpu_hwmod = {
- .name = "mpu",
- .class = &dra7xx_mpu_hwmod_class,
- .clkdm_name = "mpu_clkdm",
- .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET,
- .main_clk = "dpll_mpu_m2_ck",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_MPU_MPU_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_MPU_MPU_CONTEXT_OFFSET,
- },
- },
-};
-
-
-/*
- * 'PCIE' class
- *
- */
-
-/*
- * As noted in documentation for _reset() in omap_hwmod.c, the stock reset
- * functionality of OMAP HWMOD layer does not deassert the hardreset lines
- * associated with an IP automatically leaving the driver to handle that
- * by itself. This does not work for PCIeSS which needs the reset lines
- * deasserted for the driver to start accessing registers.
- *
- * We use a PCIeSS HWMOD class specific reset handler to deassert the hardreset
- * lines after asserting them.
- */
-int dra7xx_pciess_reset(struct omap_hwmod *oh)
-{
- int i;
-
- for (i = 0; i < oh->rst_lines_cnt; i++) {
- omap_hwmod_assert_hardreset(oh, oh->rst_lines[i].name);
- omap_hwmod_deassert_hardreset(oh, oh->rst_lines[i].name);
- }
-
- return 0;
-}
-
-static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
- .name = "pcie",
- .reset = dra7xx_pciess_reset,
-};
-
-/* pcie1 */
-static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
- { .name = "pcie", .rst_shift = 0 },
-};
-
-static struct omap_hwmod dra7xx_pciess1_hwmod = {
- .name = "pcie1",
- .class = &dra7xx_pciess_hwmod_class,
- .clkdm_name = "pcie_clkdm",
- .rst_lines = dra7xx_pciess1_resets,
- .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
- .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/* pcie2 */
-static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
- { .name = "pcie", .rst_shift = 1 },
-};
-
-/* pcie2 */
-static struct omap_hwmod dra7xx_pciess2_hwmod = {
- .name = "pcie2",
- .class = &dra7xx_pciess_hwmod_class,
- .clkdm_name = "pcie_clkdm",
- .rst_lines = dra7xx_pciess2_resets,
- .rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
- .main_clk = "l4_root_clk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
- .rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'qspi' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_qspi_sysc = {
- .rev_offs = 0,
- .sysc_offs = 0x0010,
- .sysc_flags = SYSC_HAS_SIDLEMODE,
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_qspi_hwmod_class = {
- .name = "qspi",
- .sysc = &dra7xx_qspi_sysc,
-};
-
-/* qspi */
-static struct omap_hwmod dra7xx_qspi_hwmod = {
- .name = "qspi",
- .class = &dra7xx_qspi_hwmod_class,
- .clkdm_name = "l4per2_clkdm",
- .main_clk = "qspi_gfclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L4PER2_QSPI_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L4PER2_QSPI_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'sata' class
- *
- */
-
-static struct omap_hwmod_class_sysconfig dra7xx_sata_sysc = {
- .rev_offs = 0x00fc,
- .sysc_offs = 0x0000,
- .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE),
- .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
- SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO |
- MSTANDBY_SMART | MSTANDBY_SMART_WKUP),
- .sysc_fields = &omap_hwmod_sysc_type2,
-};
-
-static struct omap_hwmod_class dra7xx_sata_hwmod_class = {
- .name = "sata",
- .sysc = &dra7xx_sata_sysc,
-};
-
-/* sata */
-
-static struct omap_hwmod dra7xx_sata_hwmod = {
- .name = "sata",
- .class = &dra7xx_sata_hwmod_class,
- .clkdm_name = "l3init_clkdm",
- .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY,
- .main_clk = "func_48m_fclk",
- .mpu_rt_idx = 1,
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3INIT_SATA_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3INIT_SATA_CONTEXT_OFFSET,
- .modulemode = MODULEMODE_SWCTRL,
- },
- },
-};
-
-/*
- * 'vcp' class
- *
- */
-
-static struct omap_hwmod_class dra7xx_vcp_hwmod_class = {
- .name = "vcp",
-};
-
-/* vcp1 */
-static struct omap_hwmod dra7xx_vcp1_hwmod = {
- .name = "vcp1",
- .class = &dra7xx_vcp_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP1_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_VCP1_CONTEXT_OFFSET,
- },
- },
-};
-
-/* vcp2 */
-static struct omap_hwmod dra7xx_vcp2_hwmod = {
- .name = "vcp2",
- .class = &dra7xx_vcp_hwmod_class,
- .clkdm_name = "l3main1_clkdm",
- .main_clk = "l3_iclk_div",
- .prcm = {
- .omap4 = {
- .clkctrl_offs = DRA7XX_CM_L3MAIN1_VCP2_CLKCTRL_OFFSET,
- .context_offs = DRA7XX_RM_L3MAIN1_VCP2_CONTEXT_OFFSET,
- },
- },
-};
-
-
-
-/*
- * Interfaces
- */
-
-/* l3_main_1 -> dmm */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__dmm = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_dmm_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_SDMA,
-};
-
-/* l3_main_2 -> l3_instr */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_2__l3_instr = {
- .master = &dra7xx_l3_main_2_hwmod,
- .slave = &dra7xx_l3_instr_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> l3_main_1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_1 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_l3_main_1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* mpu -> l3_main_1 */
-static struct omap_hwmod_ocp_if dra7xx_mpu__l3_main_1 = {
- .master = &dra7xx_mpu_hwmod,
- .slave = &dra7xx_l3_main_1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l3_main_1 -> l3_main_2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l3_main_2 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_l3_main_2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU,
-};
-
-/* l4_cfg -> l3_main_2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__l3_main_2 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_l3_main_2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_cfg */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_cfg = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_l4_cfg_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_per1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per1 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_l4_per1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_per2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per2 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_l4_per2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_per3 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_per3 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_l4_per3_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> l4_wkup */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__l4_wkup = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_l4_wkup_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> atl */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__atl = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_atl_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> bb2d */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__bb2d = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_bb2d_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_wkup -> ctrl_module_wkup */
-static struct omap_hwmod_ocp_if dra7xx_l4_wkup__ctrl_module_wkup = {
- .master = &dra7xx_l4_wkup_hwmod,
- .slave = &dra7xx_ctrl_module_wkup_hwmod,
- .clk = "wkupaon_iclk_mux",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> mpu */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__mpu = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_mpu_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> pciess1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess1 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_pciess1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> pciess1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess1 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_pciess1_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> pciess2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__pciess2 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_pciess2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> pciess2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__pciess2 = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_pciess2_hwmod,
- .clk = "l4_root_clk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> qspi */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__qspi = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_qspi_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_cfg -> sata */
-static struct omap_hwmod_ocp_if dra7xx_l4_cfg__sata = {
- .master = &dra7xx_l4_cfg_hwmod,
- .slave = &dra7xx_sata_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> vcp1 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp1 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_vcp1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> vcp1 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp1 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_vcp1_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l3_main_1 -> vcp2 */
-static struct omap_hwmod_ocp_if dra7xx_l3_main_1__vcp2 = {
- .master = &dra7xx_l3_main_1_hwmod,
- .slave = &dra7xx_vcp2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-/* l4_per2 -> vcp2 */
-static struct omap_hwmod_ocp_if dra7xx_l4_per2__vcp2 = {
- .master = &dra7xx_l4_per2_hwmod,
- .slave = &dra7xx_vcp2_hwmod,
- .clk = "l3_iclk_div",
- .user = OCP_USER_MPU | OCP_USER_SDMA,
-};
-
-static struct omap_hwmod_ocp_if *dra7xx_hwmod_ocp_ifs[] __initdata = {
- &dra7xx_l3_main_1__dmm,
- &dra7xx_l3_main_2__l3_instr,
- &dra7xx_l4_cfg__l3_main_1,
- &dra7xx_mpu__l3_main_1,
- &dra7xx_l3_main_1__l3_main_2,
- &dra7xx_l4_cfg__l3_main_2,
- &dra7xx_l3_main_1__l4_cfg,
- &dra7xx_l3_main_1__l4_per1,
- &dra7xx_l3_main_1__l4_per2,
- &dra7xx_l3_main_1__l4_per3,
- &dra7xx_l3_main_1__l4_wkup,
- &dra7xx_l4_per2__atl,
- &dra7xx_l3_main_1__bb2d,
- &dra7xx_l4_wkup__ctrl_module_wkup,
- &dra7xx_l4_cfg__mpu,
- &dra7xx_l3_main_1__pciess1,
- &dra7xx_l4_cfg__pciess1,
- &dra7xx_l3_main_1__pciess2,
- &dra7xx_l4_cfg__pciess2,
- &dra7xx_l3_main_1__qspi,
- &dra7xx_l4_cfg__sata,
- &dra7xx_l3_main_1__vcp1,
- &dra7xx_l4_per2__vcp1,
- &dra7xx_l3_main_1__vcp2,
- &dra7xx_l4_per2__vcp2,
- NULL,
-};
-
-/* SoC variant specific hwmod links */
-static struct omap_hwmod_ocp_if *dra72x_hwmod_ocp_ifs[] __initdata = {
- NULL,
-};
-
-static struct omap_hwmod_ocp_if *rtc_hwmod_ocp_ifs[] __initdata = {
- NULL,
-};
-
-int __init dra7xx_hwmod_init(void)
-{
- int ret;
-
- omap_hwmod_init();
- ret = omap_hwmod_register_links(dra7xx_hwmod_ocp_ifs);
-
- if (!ret && soc_is_dra74x()) {
- ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
- } else if (!ret && soc_is_dra72x()) {
- ret = omap_hwmod_register_links(dra72x_hwmod_ocp_ifs);
- if (!ret && !of_machine_is_compatible("ti,dra718"))
- ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
- } else if (!ret && soc_is_dra76x()) {
- if (!ret && soc_is_dra76x_abz())
- ret = omap_hwmod_register_links(rtc_hwmod_ocp_ifs);
- }
-
- return ret;
-}
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