diff options
| -rw-r--r-- | drivers/gpu/drm/xe/xe_device_types.h | 2 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pat.c | 12 | ||||
| -rw-r--r-- | drivers/gpu/drm/xe/xe_pt_types.h | 1 |
3 files changed, 15 insertions, 0 deletions
diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index c4920631677b..1ee8410ec3b1 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -15,6 +15,7 @@ #include "xe_devcoredump_types.h" #include "xe_gt_types.h" #include "xe_platform_types.h" +#include "xe_pt_types.h" #include "xe_pmu.h" #include "xe_step_types.h" @@ -321,6 +322,7 @@ struct xe_device { const u32 *table; /** Number of PAT entries */ int n_entries; + u32 idx[__XE_CACHE_LEVEL_COUNT]; } pat; /** @d3cold: Encapsulate d3cold related stuff */ diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c index 4ab1b3dc4d5d..4668ca3932c5 100644 --- a/drivers/gpu/drm/xe/xe_pat.c +++ b/drivers/gpu/drm/xe/xe_pat.c @@ -108,10 +108,16 @@ void xe_pat_init_early(struct xe_device *xe) xe->pat.ops = &xelpg_pat_ops; xe->pat.table = xelpg_pat_table; xe->pat.n_entries = ARRAY_SIZE(xelpg_pat_table); + xe->pat.idx[XE_CACHE_NONE] = 2; + xe->pat.idx[XE_CACHE_WT] = 1; + xe->pat.idx[XE_CACHE_WB] = 3; } else if (xe->info.platform == XE_PVC) { xe->pat.ops = &xehp_pat_ops; xe->pat.table = xehpc_pat_table; xe->pat.n_entries = ARRAY_SIZE(xehpc_pat_table); + xe->pat.idx[XE_CACHE_NONE] = 0; + xe->pat.idx[XE_CACHE_WT] = 2; + xe->pat.idx[XE_CACHE_WB] = 3; } else if (xe->info.platform == XE_DG2) { /* * Table is the same as previous platforms, but programming @@ -120,10 +126,16 @@ void xe_pat_init_early(struct xe_device *xe) xe->pat.ops = &xehp_pat_ops; xe->pat.table = xelp_pat_table; xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table); + xe->pat.idx[XE_CACHE_NONE] = 3; + xe->pat.idx[XE_CACHE_WT] = 2; + xe->pat.idx[XE_CACHE_WB] = 0; } else if (GRAPHICS_VERx100(xe) <= 1210) { xe->pat.ops = &xelp_pat_ops; xe->pat.table = xelp_pat_table; xe->pat.n_entries = ARRAY_SIZE(xelp_pat_table); + xe->pat.idx[XE_CACHE_NONE] = 3; + xe->pat.idx[XE_CACHE_WT] = 2; + xe->pat.idx[XE_CACHE_WB] = 0; } else { /* * Going forward we expect to need new PAT settings for most diff --git a/drivers/gpu/drm/xe/xe_pt_types.h b/drivers/gpu/drm/xe/xe_pt_types.h index 64e3921a0f46..bf5000499251 100644 --- a/drivers/gpu/drm/xe/xe_pt_types.h +++ b/drivers/gpu/drm/xe/xe_pt_types.h @@ -17,6 +17,7 @@ enum xe_cache_level { XE_CACHE_NONE, XE_CACHE_WT, XE_CACHE_WB, + __XE_CACHE_LEVEL_COUNT, }; #define XE_VM_MAX_LEVEL 4 |