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| author | Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> | 2024-07-09 23:40:51 +0530 |
|---|---|---|
| committer | Greg Kroah-Hartman <gregkh@linuxfoundation.org> | 2024-07-10 13:56:36 +0200 |
| commit | d504bfa6cfd1a37efd257b00f49cc47a58ebdabe (patch) | |
| tree | c3618ce53867c750aa229a592cf923d3f32693ab /tools/testing/selftests/net/tcp_ao/lib/utils.c | |
| parent | 5af43708d21c30e2f418cb25d337779c56d235f6 (diff) | |
usb: dwc3: enable CCI support for AMD-xilinx DWC3 controller
The GSBUSCFG0 register bits [31:16] are used to configure the cache type
settings of the descriptor and data write/read transfers (Cacheable,
Bufferable/Posted). When CCI is enabled in the design, DWC3 core GSBUSCFG0
cache bits must be updated to support CCI enabled transfers in USB.
To program GSBUSCFG0 cache bits create a software node property
in AMD-xilinx dwc3 glue driver and pass it to dwc3 core. The core
then reads this property value and configures it in dwc3_core_init()
sequence.
Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Thinh Nguyen <Thinh.Nguyen@synopsys.com>
Link: https://lore.kernel.org/r/1720548651-726412-1-git-send-email-radhey.shyam.pandey@amd.com
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Diffstat (limited to 'tools/testing/selftests/net/tcp_ao/lib/utils.c')
0 files changed, 0 insertions, 0 deletions