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| author | Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> | 2022-06-22 19:17:22 +0100 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2022-07-05 09:15:52 +0200 |
| commit | 668d361c9d893be3cbd4f3650e1934a62b204def (patch) | |
| tree | 7aa835f8fe6ccb0408d0a2b6337fa8f1a665a545 /tools/testing/selftests/kvm/lib/perf_test_util.c | |
| parent | eb2789785428e2dbc3d5f413b16c67ff90d828c1 (diff) | |
dt-bindings: clock: r9a07g043-cpg: Add Renesas RZ/Five CPG Clock and Reset Definitions
Renesas RZ/Five SoC has almost the same clock structure compared to the
Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.h header file and just
amend the RZ/Five CPG clock and reset definitions.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220622181723.13033-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Diffstat (limited to 'tools/testing/selftests/kvm/lib/perf_test_util.c')
0 files changed, 0 insertions, 0 deletions