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| author | Daniel Borkmann <daniel@iogearbox.net> | 2019-05-29 13:31:06 +0200 |
|---|---|---|
| committer | Daniel Borkmann <daniel@iogearbox.net> | 2019-05-29 13:31:06 +0200 |
| commit | 10b3c44131982e0aa889016890ada36a514a58ca (patch) | |
| tree | d0cd9d846507593f603b06093730cf1c9c6a18c3 /tools/testing/selftests/bpf/verifier/basic_instr.c | |
| parent | bd95e678e0f6e18351ecdc147ca819145db9ed7b (diff) | |
| parent | c25d60c12534ada10312a43f1c584fa7384aa2e7 (diff) | |
Merge branch 'bpf-subreg-tests'
Jiong Wang says:
====================
JIT back-ends need to guarantee high 32-bit cleared whenever one eBPF insn
write low 32-bit sub-register only. It is possible that some JIT back-ends
have failed doing this and are silently generating wrong image.
This set completes the unit tests, so bug on this could be exposed in JITs.
====================
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Diffstat (limited to 'tools/testing/selftests/bpf/verifier/basic_instr.c')
| -rw-r--r-- | tools/testing/selftests/bpf/verifier/basic_instr.c | 39 |
1 files changed, 0 insertions, 39 deletions
diff --git a/tools/testing/selftests/bpf/verifier/basic_instr.c b/tools/testing/selftests/bpf/verifier/basic_instr.c index 4d844089938e..ed91a7b9a456 100644 --- a/tools/testing/selftests/bpf/verifier/basic_instr.c +++ b/tools/testing/selftests/bpf/verifier/basic_instr.c @@ -132,42 +132,3 @@ .prog_type = BPF_PROG_TYPE_SCHED_CLS, .result = ACCEPT, }, -{ - "and32 reg zero extend check", - .insns = { - BPF_MOV64_IMM(BPF_REG_0, -1), - BPF_MOV64_IMM(BPF_REG_2, -2), - BPF_ALU32_REG(BPF_AND, BPF_REG_0, BPF_REG_2), - BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), - BPF_EXIT_INSN(), - }, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, - .result = ACCEPT, - .retval = 0, -}, -{ - "or32 reg zero extend check", - .insns = { - BPF_MOV64_IMM(BPF_REG_0, -1), - BPF_MOV64_IMM(BPF_REG_2, -2), - BPF_ALU32_REG(BPF_OR, BPF_REG_0, BPF_REG_2), - BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), - BPF_EXIT_INSN(), - }, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, - .result = ACCEPT, - .retval = 0, -}, -{ - "xor32 reg zero extend check", - .insns = { - BPF_MOV64_IMM(BPF_REG_0, -1), - BPF_MOV64_IMM(BPF_REG_2, 0), - BPF_ALU32_REG(BPF_XOR, BPF_REG_0, BPF_REG_2), - BPF_ALU64_IMM(BPF_RSH, BPF_REG_0, 32), - BPF_EXIT_INSN(), - }, - .prog_type = BPF_PROG_TYPE_SCHED_CLS, - .result = ACCEPT, - .retval = 0, -}, |