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authorTerry Bowman <[email protected]>2023-10-18 19:17:06 +0200
committerDan Williams <[email protected]>2023-10-27 20:13:38 -0700
commitbf6c9fa846e2a0f7db2a2eabd52ad4f8d4335bcb (patch)
tree7229fef1c01d127e7250cf07606a2c6d24b23250 /tools/testing/selftests/bpf/progs/test_autoload.c
parent6777877eb7a3290cf0a8a6b621e46f72f9d94b6b (diff)
cxl/pci: Update CXL error logging to use RAS register address
The CXL error handler currently only logs endpoint RAS status. The CXL topology includes several components providing RAS details to be logged during error handling.[1] Update the current handler's RAS logging to use a RAS register address. Also, update the error handler function names to be consistent with correctable and uncorrectable RAS. This will allow for adding support to log other CXL component's RAS details in the future. [1] CXL3.0 Table 8-22 CXL_Capability_ID Assignment Co-developed-by: Robert Richter <[email protected]> Signed-off-by: Terry Bowman <[email protected]> Signed-off-by: Robert Richter <[email protected]> Reviewed-by: Jonathan Cameron <[email protected]> Reviewed-by: Dave Jiang <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Dan Williams <[email protected]>
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