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authorJamie Gibbons <[email protected]>2024-03-27 12:24:37 +0000
committerBartosz Golaszewski <[email protected]>2024-03-29 13:21:30 +0100
commit6e12a52c1459b791f27396a9b656b92aaa600065 (patch)
tree9992850252fd3bfb01f8029fa1c9d6b1f01f8918 /tools/testing/selftests/bpf/progs/test_autoload.c
parent4cece764965020c22cff7665b18a012006359095 (diff)
dt-bindings: gpio: mpfs: add coreGPIO support
The GPIO controllers on PolarFire SoC were based on the "soft" IP CoreGPIO, but the inp/outp registers are at different offsets. Add compatible to allow for support of both sets of offsets. The soft core will not always have interrupts wired up, so only enforce them for the "hard" core on PolarFire SoC. Signed-off-by: Jamie Gibbons <[email protected]> Signed-off-by: Conor Dooley <[email protected]> Reviewed-by: Rob Herring <[email protected]> Signed-off-by: Bartosz Golaszewski <[email protected]>
Diffstat (limited to 'tools/testing/selftests/bpf/progs/test_autoload.c')
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