diff options
| author | Tan, Tee Min <[email protected]> | 2022-11-07 21:08:11 -0500 |
|---|---|---|
| committer | Jakub Kicinski <[email protected]> | 2022-11-09 18:35:15 -0800 |
| commit | dcea1a8107c04b9521dee1dd37971757a22db162 (patch) | |
| tree | 202a2b94ba78869890c116cfb105fb1a4ae6dc45 /tools/testing/selftests/bpf/prog_tests/prog_array_init.c | |
| parent | d75aed1428da787cbe42bc073d76f1354f364d92 (diff) | |
stmmac: intel: Update PCH PTP clock rate from 200MHz to 204.8MHz
Current Intel platform has an output of ~976ms interval
when probed on 1 Pulse-per-Second(PPS) hardware pin.
The correct PTP clock frequency for PCH GbE should be 204.8MHz
instead of 200MHz. PSE GbE PTP clock rate remains at 200MHz.
Fixes: 58da0cfa6cf1 ("net: stmmac: create dwmac-intel.c to contain all Intel platform")
Signed-off-by: Ling Pei Lee <[email protected]>
Signed-off-by: Tan, Tee Min <[email protected]>
Signed-off-by: Voon Weifeng <[email protected]>
Signed-off-by: Gan Yi Fang <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Signed-off-by: Jakub Kicinski <[email protected]>
Diffstat (limited to 'tools/testing/selftests/bpf/prog_tests/prog_array_init.c')
0 files changed, 0 insertions, 0 deletions