diff options
| author | Ilya Bakoulin <[email protected]> | 2022-07-26 16:19:38 -0400 |
|---|---|---|
| committer | Alex Deucher <[email protected]> | 2022-08-16 18:07:21 -0400 |
| commit | 04fb918bf421b299feaee1006e82921d7d381f18 (patch) | |
| tree | e84fc88e2120da0270c19cc473bdcecfe0be2356 /tools/testing/selftests/bpf/prog_tests/autoload.c | |
| parent | 84435d1d912140958213beda37c708ec3072b5e1 (diff) | |
drm/amd/display: Fix pixel clock programming
[Why]
Some pixel clock values could cause HDMI TMDS SSCPs to be misaligned
between different HDMI lanes when using YCbCr420 10-bit pixel format.
BIOS functions for transmitter/encoder control take pixel clock in kHz
increments, whereas the function for setting the pixel clock is in 100Hz
increments. Setting pixel clock to a value that is not on a kHz boundary
will cause the issue.
[How]
Round pixel clock down to nearest kHz in 10/12-bpc cases.
Reviewed-by: Aric Cyr <[email protected]>
Acked-by: Brian Chang <[email protected]>
Signed-off-by: Ilya Bakoulin <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Diffstat (limited to 'tools/testing/selftests/bpf/prog_tests/autoload.c')
0 files changed, 0 insertions, 0 deletions