diff options
| author | Catalin Marinas <[email protected]> | 2010-12-07 16:52:04 +0100 |
|---|---|---|
| committer | Russell King <[email protected]> | 2010-12-12 23:25:58 +0000 |
| commit | f91e2c3bd427239c198351f44814dd39db91afe0 (patch) | |
| tree | a1e7a0083a3866264331abfc1da8526a35523af0 /tools/perf/util/trace-event-scripting.c | |
| parent | 6313e3c21743cc88bb5bd8aa72948ee1e83937b6 (diff) | |
ARM: 6527/1: Use CTR instead of CCSIDR for the D-cache line size on ARMv7
The current implementation of the dcache_line_size macro reads the L1
cache size from the CCSIDR register. This, however, is not guaranteed to
be the smallest cache line in the cache hierarchy. The patch changes to
the macro to use the more architecturally correct CTR register.
Reported-by: Kevin Sapp <[email protected]>
Signed-off-by: Catalin Marinas <[email protected]>
Signed-off-by: Russell King <[email protected]>
Diffstat (limited to 'tools/perf/util/trace-event-scripting.c')
0 files changed, 0 insertions, 0 deletions