diff options
author | Gregory CLEMENT <[email protected]> | 2012-11-06 01:58:07 +0100 |
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committer | Russell King <[email protected]> | 2012-11-06 19:47:35 +0000 |
commit | b8db6b886a1fecd6a5b1d13b190f3149247305ef (patch) | |
tree | 382e1fc446b99ee32e3f64d399f27e3af32d5782 /tools/perf/util/trace-event-scripting.c | |
parent | c3545236e8740ab556022f87685d18503c86e187 (diff) |
ARM: 7547/4: cache-l2x0: add support for Aurora L2 cache ctrl
Aurora Cache Controller was designed to be compatible with the ARM L2
Cache Controller. It comes with some difference or improvement such
as:
- no cache id part number available through hardware (need to get it
by the DT).
- always write through mode available.
- two flavors of the controller outer cache and system cache (meaning
maintenance operations on L1 are broadcasted to the L2 and L2
performs the same operation).
- in outer cache mode, the cache maintenance operations are improved and
can be done on a range inside a page and are not limited to a cache
line.
Tested-and-Reviewed-by: Lior Amsalem <[email protected]>
Signed-off-by: Gregory CLEMENT <[email protected]>
Signed-off-by: Yehuda Yitschak <[email protected]>
Reviewed-by: Will Deacon <[email protected]>
Signed-off-by: Russell King <[email protected]>
Diffstat (limited to 'tools/perf/util/trace-event-scripting.c')
0 files changed, 0 insertions, 0 deletions