diff options
| author | Sowjanya Komatineni <[email protected]> | 2020-05-04 19:31:52 -0700 |
|---|---|---|
| committer | Thierry Reding <[email protected]> | 2020-05-20 15:26:09 +0200 |
| commit | b4f99176a501ac34c7f5c9322910e248a2f43397 (patch) | |
| tree | 66287ece150a924027ff7e8fe446ad753bebd532 /tools/perf/util/trace-event-scripting.c | |
| parent | 4012ab12b3cbd3efbd7254f04de40903c624a237 (diff) | |
arm64: tegra: Fix SOR powergate clocks and reset
Tegra210 device tree lists CSI clock and reset under SOR powergate
node.
But Tegra210 has CSICIL in SOR partition and CSI in VENC partition.
So, this patch includes fix for SOR powergate node.
Signed-off-by: Sowjanya Komatineni <[email protected]>
Signed-off-by: Thierry Reding <[email protected]>
Diffstat (limited to 'tools/perf/util/trace-event-scripting.c')
0 files changed, 0 insertions, 0 deletions