diff options
| author | Jerome Brunet <[email protected]> | 2019-08-29 18:16:35 +0200 |
|---|---|---|
| committer | Marc Zyngier <[email protected]> | 2019-08-30 15:01:06 +0100 |
| commit | b2fb4b77994abc1107c35547f3e123dce8e9f67d (patch) | |
| tree | aa1c8286364337a62d499451b37681b55ef687d3 /tools/perf/util/trace-event-scripting.c | |
| parent | abc08aac82af0c71e30b446575f5810c9cc11640 (diff) | |
irqchip/meson-gpio: Add support for meson sm1 SoCs
The meson sm1 SoCs uses the same type of GPIO interrupt controller IP
block as the other meson SoCs, A total of 100 pins can be spied on:
- 223:100 undefined (no interrupt)
- 99:97 3 pins on bank GPIOE
- 96:77 20 pins on bank GPIOX
- 76:61 16 pins on bank GPIOA
- 60:53 8 pins on bank GPIOC
- 52:37 16 pins on bank BOOT
- 36:28 9 pins on bank GPIOH
- 27:12 16 pins on bank GPIOZ
- 11:0 12 pins in the AO domain
Mapping is the same as the g12a family but the sm1 controller
allows to trig an irq on both edges of the input signal. This was
not possible with the previous SoCs families
Signed-off-by: Jerome Brunet <[email protected]>
Signed-off-by: Marc Zyngier <[email protected]>
Tested-by: Kevin Hilman <[email protected]>
Reviewed-by: Kevin Hilman <[email protected]>
Link: https://lore.kernel.org/r/[email protected]
Diffstat (limited to 'tools/perf/util/trace-event-scripting.c')
0 files changed, 0 insertions, 0 deletions