diff options
| author | Yan, Zheng <[email protected]> | 2013-07-18 17:02:23 +0800 |
|---|---|---|
| committer | Ingo Molnar <[email protected]> | 2013-09-02 08:42:47 +0200 |
| commit | 53ad0447208d3f5897f673ca0b16c776583eedba (patch) | |
| tree | 6966be991efc98edce985854defe71b62ff4f116 /tools/perf/util/trace-event-scripting.c | |
| parent | ea79ca0de05198159bcb8a45479122a75e4a5861 (diff) | |
perf/x86: use INTEL_UEVENT_EXTRA_REG to define MSR_OFFCORE_RSP_X
Silvermont (22nm Atom) has two offcore response configuration MSRs,
unlike other Intel CPU, its event code for MSR_OFFCORE_RSP_1 is 0x02b7.
To avoid complicating intel_fixup_er(), use INTEL_UEVENT_EXTRA_REG to
define MSR_OFFCORE_RSP_X. So intel_fixup_er() can find the event code
for OFFCORE_RSP_N by x86_pmu.extra_regs[N].event.
Signed-off-by: Yan, Zheng <[email protected]>
Signed-off-by: Peter Zijlstra <[email protected]>
Link: http://lkml.kernel.org/r/[email protected]
Signed-off-by: Ingo Molnar <[email protected]>
Diffstat (limited to 'tools/perf/util/trace-event-scripting.c')
0 files changed, 0 insertions, 0 deletions