clk: meson: meson8b: use a separate clock table for Meson8m2

Meson8, Meson8b and Meson8m2 implement a similar clock controller.
However, there are a few differences between the three actual IP blocks.

One example where Meson8m2 differs from Meson8b is the VPU clock setup:
- the VPU input mux can choose between "fclk_div4", "fclk_div3",
  "fclk_div5" and "fclk_div7" on Meson8b
- however, on Meson8m2 it can choose between "fclk_div4", "fclk_div3",
  "fclk_div5" and "gp_pll" (GP_PLL only exists on Meson8m2, it's the
  predecessor of the GP0_PLL clock on GXBB/GXL/GXM))

Add a separate clk_hw_onecell_data table for Meson8m2 so these
differences can be implemented in our clock controller driver. For now
meson8m2_hw_onecell_data is a clone of our existing
meson8b_hw_onecell_data.

Signed-off-by: Martin Blumenstingl <[email protected]>
Reviewed-by: Neil Armstrong <[email protected]>
Acked-by: Jerome Brunet <[email protected]>
Signed-off-by: Neil Armstrong <[email protected]>
Link: https://lkml.kernel.org/r/[email protected]

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