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authorKan Liang <[email protected]>2019-10-08 08:50:09 -0700
committerIngo Molnar <[email protected]>2019-10-12 15:13:09 +0200
commit0917b95079af82c69d8f5bab301faeebcd2cb3cd (patch)
tree58240abdca52e93df0b760beea1fd95aa23a80a9 /tools/perf/util/trace-event-scripting.c
parent23645a76ba816652d6898def2ee69c6a6250c9b1 (diff)
perf/x86/msr: Add Tiger Lake CPU support
Tiger Lake is the followon to Ice Lake. PPERF and SMI_COUNT MSRs are also supported. The External Design Specification (EDS) is not published yet. It comes from an authoritative internal source. The patch has been tested on real hardware. Signed-off-by: Kan Liang <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Cc: Linus Torvalds <[email protected]> Cc: Peter Zijlstra <[email protected]> Cc: Thomas Gleixner <[email protected]> Link: https://lkml.kernel.org/r/[email protected] Signed-off-by: Ingo Molnar <[email protected]>
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