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authorRex-BC Chen <[email protected]>2022-05-23 17:33:29 +0800
committerStephen Boyd <[email protected]>2022-06-15 17:24:12 -0700
commitedabcf71d100fd433a0fc2d0c97057c446c33b2a (patch)
tree03502b77162e63a48a257924a523ab7a61b59dbc /tools/perf/util/scripting-engines/trace-event-python.c
parentb348c26c28a96d15f832974c5b54a3d6bbe4e7d8 (diff)
clk: mediatek: reset: Fix written reset bit offset
Original assert/deassert bit is BIT(0), but it's more resonable to modify them to BIT(id % 32) which is based on id. This patch will not influence any previous driver because the reset is only used for thermal. The id (MT8183_INFRACFG_AO_THERM_SW_RST) is 0. Fixes: 64ebb57a3df6 ("clk: reset: Modify reset-controller driver") Signed-off-by: Rex-BC Chen <[email protected]> Reviewed-by: Chen-Yu Tsai <[email protected]> Reviewed-by: AngeloGioacchino Del Regno <[email protected]> Reviewed-by: NĂ­colas F. R. A. Prado <[email protected]> Tested-by: NĂ­colas F. R. A. Prado <[email protected]> Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Stephen Boyd <[email protected]>
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