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authorCatalin Marinas <[email protected]>2018-05-11 13:33:12 +0100
committerCatalin Marinas <[email protected]>2018-05-15 13:29:55 +0100
commitebc7e21e0fa28c46b938baed292c77e2d3ef8165 (patch)
treefa415205a2ea1ff232aee0b7a6c4e998837b77ef /tools/perf/util/scripting-engines/trace-event-python.c
parentd93277b9839b0bde06238a7a7f644114edb2ad4a (diff)
arm64: Increase ARCH_DMA_MINALIGN to 128
This patch increases the ARCH_DMA_MINALIGN to 128 so that it covers the currently known Cache Writeback Granule (CTR_EL0.CWG) on arm64 and moves the fallback in cache_line_size() from L1_CACHE_BYTES to this constant. In addition, it warns (and taints) if the CWG is larger than ARCH_DMA_MINALIGN as this is not safe with non-coherent DMA. Cc: Will Deacon <[email protected]> Cc: Robin Murphy <[email protected]> Signed-off-by: Catalin Marinas <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
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