diff options
| author | Seungwon Jeon <[email protected]> | 2012-05-22 13:01:21 +0900 |
|---|---|---|
| committer | Chris Ball <[email protected]> | 2012-06-06 09:38:51 -0400 |
| commit | e419990b5e811027b1552cbc5b76a6cc180f7f48 (patch) | |
| tree | 12791ff201b9e56f74caaa86c22ce0964a8effcc /tools/perf/util/scripting-engines/trace-event-python.c | |
| parent | fda5f736864c46324dbc50246ef1ca0e84ebf4ae (diff) | |
mmc: dw_mmc: correct the calculation for CLKDIV
In case of "host->bus_hz < slot->clock", divider value is
miscalculated. And clock divider register value is multiple of 2. If
calculated divider value is odd number, result can be over-clocking.
Signed-off-by: Seungwon Jeon <[email protected]>
Acked-by: Will Newton <[email protected]>
Signed-off-by: Chris Ball <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
0 files changed, 0 insertions, 0 deletions