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authorQiuxu Zhuo <[email protected]>2017-05-23 08:07:31 +0800
committerBorislav Petkov <[email protected]>2017-05-25 14:37:21 +0200
commite2f747b1f42a2f6b0cf5416be1684c1b94a42f0f (patch)
tree2c9efd078b5e4041dc77a4e5a2424bbfc850ab5b /tools/perf/util/scripting-engines/trace-event-python.c
parent7fd562b75d7752ed50c61d65f27b558cd93a359b (diff)
EDAC, sb_edac: Assign EDAC memory controller per h/w controller
Tony pointed out: "currently the driver pretends there is one big 8-channel memory controller per socket instead of 2 4-channel controllers. This is fine with all memory controller populated with symmetrical DIMM configurations, but runs into difficulties on asymmetrical setups". Restructure the driver to assign an EDAC memory controller to each real h/w memory controller to resolve the issue. Signed-off-by: Qiuxu Zhuo <[email protected]> Cc: linux-edac <[email protected]> Link: http://lkml.kernel.org/r/[email protected] [ Break some lines at convenient points. ] Signed-off-by: Borislav Petkov <[email protected]>
Diffstat (limited to 'tools/perf/util/scripting-engines/trace-event-python.c')
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