clk: sunxi-ng: a80: fix the zero'ing of bits 16 and 18

The zero'ing of bits 16 and 18 is incorrect. Currently the code
is masking with the bitwise-and of BIT(16) & BIT(18) which is
0, so the updated value for val is always zero. Fix this by bitwise
and-ing value with the correct mask that will zero bits 16 and 18.

Addresses-Coverity: (" Suspicious &= or |= constant expression")
Fixes: b8eb71dcdd08 ("clk: sunxi-ng: Add A80 CCU")
Signed-off-by: Colin Ian King <[email protected]>
Signed-off-by: Maxime Ripard <[email protected]>

0 files changed, 0 insertions, 0 deletions